llvm.org GIT mirror llvm / c60a59c
ARM big endian function argument passing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208316 91177308-0d34-0410-b5e6-96231b3b80d8 Christian Pirker 5 years ago
9 changed file(s) with 412 addition(s) and 140 deletion(s). Raw diff Collapse all Expand all
12921292 InFlag);
12931293 Chain = Hi.getValue(1);
12941294 InFlag = Hi.getValue(2);
1295 if (!Subtarget->isLittle())
1296 std::swap (Lo, Hi);
12951297 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
12961298
12971299 if (VA.getLocVT() == MVT::v2f64) {
13071309 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
13081310 Chain = Hi.getValue(1);
13091311 InFlag = Hi.getValue(2);
1312 if (!Subtarget->isLittle())
1313 std::swap (Lo, Hi);
13101314 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
13111315 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
13121316 DAG.getConstant(1, MVT::i32));
13571361
13581362 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
13591363 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1360 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1364 unsigned id = Subtarget->isLittle() ? 0 : 1;
1365 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
13611366
13621367 if (NextVA.isRegLoc())
1363 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1368 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
13641369 else {
13651370 assert(NextVA.isMemLoc());
13661371 if (!StackPtr.getNode())
13671372 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
13681373
1369 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1374 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
13701375 dl, DAG, NextVA,
13711376 Flags));
13721377 }
20812086 SDValue Flag;
20822087 SmallVector RetOps;
20832088 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2089 bool isLittleEndian = Subtarget->isLittle();
20842090
20852091 // Copy the result values into the output registers.
20862092 for (unsigned i = 0, realRVLocIdx = 0;
21072113 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
21082114 DAG.getVTList(MVT::i32, MVT::i32), Half);
21092115
2110 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
2116 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2117 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2118 Flag);
21112119 Flag = Chain.getValue(1);
21122120 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
21132121 VA = RVLocs[++i]; // skip ahead to next loc
21142122 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2115 HalfGPRs.getValue(1), Flag);
2123 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2124 Flag);
21162125 Flag = Chain.getValue(1);
21172126 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
21182127 VA = RVLocs[++i]; // skip ahead to next loc
21252134 // available.
21262135 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
21272136 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2128 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2137 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2138 fmrrd.getValue(isLittleEndian ? 0 : 1),
2139 Flag);
21292140 Flag = Chain.getValue(1);
21302141 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
21312142 VA = RVLocs[++i]; // skip ahead to next loc
2132 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2143 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2144 fmrrd.getValue(isLittleEndian ? 1 : 0),
21332145 Flag);
21342146 } else
21352147 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
26602672 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
26612673 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
26622674 }
2663
2675 if (!Subtarget->isLittle())
2676 std::swap (ArgValue, ArgValue2);
26642677 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
26652678 }
26662679
83138326 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
83148327 StVal.getNode()->hasOneUse()) {
83158328 SelectionDAG &DAG = DCI.DAG;
8329 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
83168330 SDLoc DL(St);
83178331 SDValue BasePtr = St->getBasePtr();
83188332 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8319 StVal.getNode()->getOperand(0), BasePtr,
8320 St->getPointerInfo(), St->isVolatile(),
8333 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
8334 BasePtr, St->getPointerInfo(), St->isVolatile(),
83218335 St->isNonTemporal(), St->getAlignment());
83228336
83238337 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
83248338 DAG.getConstant(4, MVT::i32));
8325 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
8339 return DAG.getStore(NewST1.getValue(0), DL,
8340 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
83268341 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
83278342 St->isNonTemporal(),
83288343 std::min(4U, St->getAlignment() / 2));
1053810553
1053910554 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
1054010555 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
10556 if (!Subtarget->isLittle())
10557 std::swap (Lo, Hi);
1054110558 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
1054210559 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
1054310560 return Builder.CreateOr(
1057110588
1057210589 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
1057310590 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
10591 if (!Subtarget->isLittle())
10592 std::swap (Lo, Hi);
1057410593 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
1057510594 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
1057610595 }
None ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
1 ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-THUMB
0 ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
1 ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE
2 ; RUN: llc < %s -mtriple=armebv7 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
3 ; RUN: llc < %s -mtriple=thumbebv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-BE
24
35 define i64 @test1(i64* %ptr, i64 %val) {
46 ; CHECK-LABEL: test1:
57 ; CHECK: dmb {{ish$}}
68 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
7 ; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
8 ; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
9 ; CHECK-LE: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
10 ; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
11 ; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]
12 ; CHECK-BE: adc [[REG3:(r[0-9]?[02468])]], [[REG1]]
913 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
1014 ; CHECK: cmp
1115 ; CHECK: bne
1418 ; CHECK-THUMB-LABEL: test1:
1519 ; CHECK-THUMB: dmb {{ish$}}
1620 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
17 ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
18 ; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
21 ; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
22 ; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
23 ; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
24 ; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]
1925 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
2026 ; CHECK-THUMB: cmp
2127 ; CHECK-THUMB: bne
2935 ; CHECK-LABEL: test2:
3036 ; CHECK: dmb {{ish$}}
3137 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
32 ; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
33 ; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
38 ; CHECK-LE: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
39 ; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
40 ; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]
41 ; CHECK-BE: sbc [[REG3:(r[0-9]?[02468])]], [[REG1]]
3442 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
3543 ; CHECK: cmp
3644 ; CHECK: bne
3947 ; CHECK-THUMB-LABEL: test2:
4048 ; CHECK-THUMB: dmb {{ish$}}
4149 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
42 ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
43 ; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
50 ; CHECK-THUMB-LE: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
51 ; CHECK-THUMB-LE: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
52 ; CHECK-THUMB-BE: subs.w [[REG4:[a-z0-9]+]], [[REG2]]
53 ; CHECK-THUMB-BE: sbc.w [[REG3:[a-z0-9]+]], [[REG1]]
4454 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
4555 ; CHECK-THUMB: cmp
4656 ; CHECK-THUMB: bne
5464 ; CHECK-LABEL: test3:
5565 ; CHECK: dmb {{ish$}}
5666 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
57 ; CHECK-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
58 ; CHECK-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
67 ; CHECK-LE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
68 ; CHECK-LE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
69 ; CHECK-BE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
70 ; CHECK-BE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
5971 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
6072 ; CHECK: cmp
6173 ; CHECK: bne
6476 ; CHECK-THUMB-LABEL: test3:
6577 ; CHECK-THUMB: dmb {{ish$}}
6678 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
67 ; CHECK-THUMB-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
68 ; CHECK-THUMB-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
79 ; CHECK-THUMB-LE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
80 ; CHECK-THUMB-LE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
81 ; CHECK-THUMB-BE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
82 ; CHECK-THUMB-BE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
6983 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
7084 ; CHECK-THUMB: cmp
7185 ; CHECK-THUMB: bne
7993 ; CHECK-LABEL: test4:
8094 ; CHECK: dmb {{ish$}}
8195 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
82 ; CHECK-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
83 ; CHECK-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
96 ; CHECK-LE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
97 ; CHECK-LE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
98 ; CHECK-BE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
99 ; CHECK-BE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
84100 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
85101 ; CHECK: cmp
86102 ; CHECK: bne
89105 ; CHECK-THUMB-LABEL: test4:
90106 ; CHECK-THUMB: dmb {{ish$}}
91107 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
92 ; CHECK-THUMB-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
93 ; CHECK-THUMB-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
108 ; CHECK-THUMB-LE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
109 ; CHECK-THUMB-LE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
110 ; CHECK-THUMB-BE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
111 ; CHECK-THUMB-BE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
94112 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
95113 ; CHECK-THUMB: cmp
96114 ; CHECK-THUMB: bne
104122 ; CHECK-LABEL: test5:
105123 ; CHECK: dmb {{ish$}}
106124 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
107 ; CHECK-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
108 ; CHECK-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
125 ; CHECK-LE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
126 ; CHECK-LE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
127 ; CHECK-BE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
128 ; CHECK-BE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
109129 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
110130 ; CHECK: cmp
111131 ; CHECK: bne
114134 ; CHECK-THUMB-LABEL: test5:
115135 ; CHECK-THUMB: dmb {{ish$}}
116136 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
117 ; CHECK-THUMB-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
118 ; CHECK-THUMB-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
137 ; CHECK-THUMB-LE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
138 ; CHECK-THUMB-LE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
139 ; CHECK-THUMB-BE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
140 ; CHECK-THUMB-BE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
119141 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
120142 ; CHECK-THUMB: cmp
121143 ; CHECK-THUMB: bne
150172 ; CHECK-LABEL: test7:
151173 ; CHECK: dmb {{ish$}}
152174 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
153 ; CHECK-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG1]], r1
154 ; CHECK-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG2]], r2
175 ; CHECK-LE-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG1]], r1
176 ; CHECK-LE-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG2]], r2
177 ; CHECK-BE-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG2]], r2
178 ; CHECK-BE-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG1]], r1
155179 ; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
156180 ; CHECK: bne
157181 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
162186 ; CHECK-THUMB-LABEL: test7:
163187 ; CHECK-THUMB: dmb {{ish$}}
164188 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
165 ; CHECK-THUMB-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2
166 ; CHECK-THUMB-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3
189 ; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2
190 ; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3
191 ; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG1]]
192 ; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG2]]
167193 ; CHECK-THUMB: orrs [[MISMATCH_HI]], [[MISMATCH_LO]]
168194 ; CHECK-THUMB: bne
169195 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
219245 ; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
220246 ; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
221247 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
222 ; CHECK: cmp [[REG1]], r1
248 ; CHECK-LE: cmp [[REG1]], r1
249 ; CHECK-BE: cmp [[REG2]], r2
223250 ; CHECK: movwls [[CARRY_LO]], #1
224 ; CHECK: cmp [[REG2]], r2
251 ; CHECK-LE: cmp [[REG2]], r2
252 ; CHECK-BE: cmp [[REG1]], r1
225253 ; CHECK: movwle [[CARRY_HI]], #1
226254 ; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
227255 ; CHECK: cmp [[CARRY_HI]], #0
236264 ; CHECK-THUMB-LABEL: test10:
237265 ; CHECK-THUMB: dmb {{ish$}}
238266 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
239 ; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
240 ; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
241 ; CHECK-THUMB: cmp [[REG1]], r2
267 ; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+|lr]], #0
268 ; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+|lr]], #0
269 ; CHECK-THUMB-LE: cmp [[REG1]], r2
270 ; CHECK-THUMB-BE: cmp [[REG2]], r3
242271 ; CHECK-THUMB: movls.w [[CARRY_LO]], #1
243 ; CHECK-THUMB: cmp [[REG2]], r3
272 ; CHECK-THUMB-LE: cmp [[REG2]], r3
273 ; CHECK-THUMB-BE: cmp [[REG1]], r2
244274 ; CHECK-THUMB: movle [[CARRY_HI]], #1
245275 ; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
246276 ; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
264294 ; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
265295 ; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
266296 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
267 ; CHECK: cmp [[REG1]], r1
297 ; CHECK-LE: cmp [[REG1]], r1
298 ; CHECK-BE: cmp [[REG2]], r2
268299 ; CHECK: movwls [[CARRY_LO]], #1
269 ; CHECK: cmp [[REG2]], r2
300 ; CHECK-LE: cmp [[REG2]], r2
301 ; CHECK-BE: cmp [[REG1]], r1
270302 ; CHECK: movwls [[CARRY_HI]], #1
271303 ; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
272304 ; CHECK: cmp [[CARRY_HI]], #0
278310 ; CHECK: bne
279311 ; CHECK: dmb {{ish$}}
280312
281
282313 ; CHECK-THUMB-LABEL: test11:
283314 ; CHECK-THUMB: dmb {{ish$}}
284315 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
285316 ; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
286317 ; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
287 ; CHECK-THUMB: cmp [[REG1]], r2
318 ; CHECK-THUMB-LE: cmp [[REG1]], r2
319 ; CHECK-THUMB-BE: cmp [[REG2]], r3
288320 ; CHECK-THUMB: movls.w [[CARRY_LO]], #1
289 ; CHECK-THUMB: cmp [[REG2]], r3
321 ; CHECK-THUMB-LE: cmp [[REG2]], r3
322 ; CHECK-THUMB-BE: cmp [[REG1]], r2
290323 ; CHECK-THUMB: movls [[CARRY_HI]], #1
291324 ; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
292325 ; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
310343 ; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
311344 ; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
312345 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
313 ; CHECK: cmp [[REG1]], r1
346 ; CHECK-LE: cmp [[REG1]], r1
347 ; CHECK-BE: cmp [[REG2]], r2
314348 ; CHECK: movwhi [[CARRY_LO]], #1
315 ; CHECK: cmp [[REG2]], r2
349 ; CHECK-LE: cmp [[REG2]], r2
350 ; CHECK-BE: cmp [[REG1]], r1
316351 ; CHECK: movwgt [[CARRY_HI]], #1
317352 ; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
318353 ; CHECK: cmp [[CARRY_HI]], #0
329364 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
330365 ; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
331366 ; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
332 ; CHECK-THUMB: cmp [[REG1]], r2
367 ; CHECK-THUMB-LE: cmp [[REG1]], r2
368 ; CHECK-THUMB-BE: cmp [[REG2]], r3
333369 ; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
334 ; CHECK-THUMB: cmp [[REG2]], r3
370 ; CHECK-THUMB-LE: cmp [[REG2]], r3
371 ; CHECK-THUMB-BE: cmp [[REG1]], r2
335372 ; CHECK-THUMB: movgt [[CARRY_HI]], #1
336373 ; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
337374 ; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
355392 ; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
356393 ; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
357394 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
358 ; CHECK: cmp [[REG1]], r1
395 ; CHECK-LE: cmp [[REG1]], r1
396 ; CHECK-BE: cmp [[REG2]], r2
359397 ; CHECK: movwhi [[CARRY_LO]], #1
360 ; CHECK: cmp [[REG2]], r2
398 ; CHECK-LE: cmp [[REG2]], r2
399 ; CHECK-BE: cmp [[REG1]], r1
361400 ; CHECK: movwhi [[CARRY_HI]], #1
362401 ; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
363402 ; CHECK: cmp [[CARRY_HI]], #0
374413 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
375414 ; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
376415 ; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
377 ; CHECK-THUMB: cmp [[REG1]], r2
416 ; CHECK-THUMB-LE: cmp [[REG1]], r2
417 ; CHECK-THUMB-BE: cmp [[REG2]], r3
378418 ; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
379 ; CHECK-THUMB: cmp [[REG2]], r3
419 ; CHECK-THUMB-LE: cmp [[REG2]], r3
420 ; CHECK-THUMB-BE: cmp [[REG1]], r2
380421 ; CHECK-THUMB: movhi [[CARRY_HI]], #1
381422 ; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
382423 ; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
None ; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
1 ; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-THUMB
0 ; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM-LE
1 ; RUN: llc -mtriple=armebv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM-BE
2 ; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE
3 ; RUN: llc -mtriple=thumbebv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-BE
24
35 @var8 = global i8 0
46 @var16 = global i16 0
8688 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
8789 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
8890 ; function there.
89 ; CHECK-NEXT: adds{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
90 ; CHECK-NEXT: adc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
91 ; CHECK-LE-NEXT: adds{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
92 ; CHECK-LE-NEXT: adc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
93 ; CHECK-BE-NEXT: adds{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
94 ; CHECK-BE-NEXT: adc{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
9195 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
9296 ; CHECK-NEXT: cmp [[STATUS]], #0
9397 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
180184 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
181185 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
182186 ; function there.
183 ; CHECK-NEXT: subs{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
184 ; CHECK-NEXT: sbc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
187 ; CHECK-LE-NEXT: subs{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
188 ; CHECK-LE-NEXT: sbc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
189 ; CHECK-BE-NEXT: subs{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
190 ; CHECK-BE-NEXT: sbc{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
185191 ; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
186192 ; CHECK-NEXT: cmp [[STATUS]], #0
187193 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
274280 ; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
275281 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
276282 ; function there.
277 ; CHECK-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
278 ; CHECK-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
283 ; CHECK-LE-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
284 ; CHECK-LE-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
285 ; CHECK-BE-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
286 ; CHECK-BE-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
279287 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
280288 ; CHECK-NEXT: cmp [[STATUS]], #0
281289 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
368376 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
369377 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
370378 ; function there.
371 ; CHECK-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
372 ; CHECK-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
379 ; CHECK-LE-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
380 ; CHECK-LE-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
381 ; CHECK-BE-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
382 ; CHECK-BE-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
373383 ; CHECK: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
374384 ; CHECK-NEXT: cmp [[STATUS]], #0
375385 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
462472 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
463473 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
464474 ; function there.
465 ; CHECK-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
466 ; CHECK-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
475 ; CHECK-LE-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
476 ; CHECK-LE-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
477 ; CHECK-BE-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
478 ; CHECK-BE-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
467479 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
468480 ; CHECK-NEXT: cmp [[STATUS]], #0
469481 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
656668 ; function there.
657669 ; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
658670 ; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
659 ; CHECK-ARM: cmp [[OLD1]], r0
660 ; CHECK-ARM: movwls [[LOCARRY]], #1
661 ; CHECK-ARM: cmp [[OLD2]], r1
662 ; CHECK-ARM: movwle [[HICARRY]], #1
671 ; CHECK-ARM-LE: cmp [[OLD1]], r0
672 ; CHECK-ARM-LE: movwls [[LOCARRY]], #1
673 ; CHECK-ARM-LE: cmp [[OLD2]], r1
674 ; CHECK-ARM-LE: movwle [[HICARRY]], #1
675 ; CHECK-ARM-BE: cmp [[OLD2]], r1
676 ; CHECK-ARM-BE: movwls [[LOCARRY]], #1
677 ; CHECK-ARM-BE: cmp [[OLD1]], r0
678 ; CHECK-ARM-BE: movwle [[HICARRY]], #1
663679 ; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
664680 ; CHECK-ARM: cmp [[HICARRY]], #0
665681 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
770786 ; function there.
771787 ; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
772788 ; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
773 ; CHECK-ARM: cmp [[OLD1]], r0
774 ; CHECK-ARM: movwhi [[LOCARRY]], #1
775 ; CHECK-ARM: cmp [[OLD2]], r1
776 ; CHECK-ARM: movwgt [[HICARRY]], #1
789 ; CHECK-ARM-LE: cmp [[OLD1]], r0
790 ; CHECK-ARM-LE: movwhi [[LOCARRY]], #1
791 ; CHECK-ARM-LE: cmp [[OLD2]], r1
792 ; CHECK-ARM-LE: movwgt [[HICARRY]], #1
793 ; CHECK-ARM-BE: cmp [[OLD2]], r1
794 ; CHECK-ARM-BE: movwhi [[LOCARRY]], #1
795 ; CHECK-ARM-BE: cmp [[OLD1]], r0
796 ; CHECK-ARM-BE: movwgt [[HICARRY]], #1
777797 ; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
778798 ; CHECK-ARM: cmp [[HICARRY]], #0
779799 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
884904 ; function there.
885905 ; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
886906 ; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
887 ; CHECK-ARM: cmp [[OLD1]], r0
888 ; CHECK-ARM: movwls [[LOCARRY]], #1
889 ; CHECK-ARM: cmp [[OLD2]], r1
890 ; CHECK-ARM: movwls [[HICARRY]], #1
907 ; CHECK-ARM-LE: cmp [[OLD1]], r0
908 ; CHECK-ARM-LE: movwls [[LOCARRY]], #1
909 ; CHECK-ARM-LE: cmp [[OLD2]], r1
910 ; CHECK-ARM-LE: movwls [[HICARRY]], #1
911 ; CHECK-ARM-BE: cmp [[OLD2]], r1
912 ; CHECK-ARM-BE: movwls [[LOCARRY]], #1
913 ; CHECK-ARM-BE: cmp [[OLD1]], r0
914 ; CHECK-ARM-BE: movwls [[HICARRY]], #1
891915 ; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
892916 ; CHECK-ARM: cmp [[HICARRY]], #0
893917 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
9981022 ; function there.
9991023 ; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0
10001024 ; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0
1001 ; CHECK-ARM: cmp [[OLD1]], r0
1002 ; CHECK-ARM: movwhi [[LOCARRY]], #1
1003 ; CHECK-ARM: cmp [[OLD2]], r1
1004 ; CHECK-ARM: movwhi [[HICARRY]], #1
1025 ; CHECK-ARM-LE: cmp [[OLD1]], r0
1026 ; CHECK-ARM-LE: movwhi [[LOCARRY]], #1
1027 ; CHECK-ARM-LE: cmp [[OLD2]], r1
1028 ; CHECK-ARM-LE: movwhi [[HICARRY]], #1
1029 ; CHECK-ARM-BE: cmp [[OLD2]], r1
1030 ; CHECK-ARM-BE: movwhi [[LOCARRY]], #1
1031 ; CHECK-ARM-BE: cmp [[OLD1]], r0
1032 ; CHECK-ARM-BE: movwhi [[HICARRY]], #1
10051033 ; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]]
10061034 ; CHECK-ARM: cmp [[HICARRY]], #0
10071035 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
11111139 ; CHECK: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
11121140 ; r0, r1 below is a reasonable guess but could change: it certainly comes into the
11131141 ; function there.
1114 ; CHECK-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0
1115 ; CHECK-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1
1116 ; CHECK: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
1142 ; CHECK-LE-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0
1143 ; CHECK-LE-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1
1144 ; CHECK-LE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
1145 ; CHECK-BE-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1
1146 ; CHECK-BE-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0
1147 ; CHECK-BE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_HI]], [[MISMATCH_LO]]
11171148 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3
11181149 ; CHECK-NEXT: BB#2:
11191150 ; As above, r2, r3 is a reasonable guess.
11501181 %val = load atomic i8* %addr monotonic, align 1
11511182 ; CHECK-NOT: dmb
11521183 ; CHECK-NOT: mcr
1153 ; CHECK: ldrb r0, [r0, r2]
1184 ; CHECK-LE: ldrb r0, [r0, r2]
1185 ; CHECK-BE: ldrb r0, [r1, r3]
11541186 ; CHECK-NOT: dmb
11551187 ; CHECK-NOT: mcr
11561188
12171249 %val = load atomic i32* %addr monotonic, align 4
12181250 ; CHECK-NOT: dmb
12191251 ; CHECK-NOT: mcr
1220 ; CHECK: ldr r0, [r0, r2]
1252 ; CHECK-LE: ldr r0, [r0, r2]
1253 ; CHECK-BE: ldr r0, [r1, r3]
12211254 ; CHECK-NOT: dmb
12221255 ; CHECK-NOT: mcr
12231256
12581291 %addr = inttoptr i64 %addr_int to i8*
12591292
12601293 store atomic i8 %val, i8* %addr monotonic, align 1
1261 ; CHECK: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp]
1262 ; CHECK: strb [[VAL]], [r0, r2]
1294 ; CHECK-LE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp]
1295 ; CHECK-LE: strb [[VAL]], [r0, r2]
1296 ; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3]
1297 ; CHECK-BE: strb [[VAL]], [r1, r3]
12631298
12641299 ret void
12651300 }
13271362 ; CHECK: ldr [[VAL:r[0-9]+]], [sp]
13281363 ; CHECK-NOT: dmb
13291364 ; CHECK-NOT: mcr
1330 ; CHECK: str [[VAL]], [r0, r2]
1365 ; CHECK-LE: str [[VAL]], [r0, r2]
1366 ; CHECK-BE: str [[VAL]], [r1, r3]
13311367 ; CHECK-NOT: dmb
13321368 ; CHECK-NOT: mcr
13331369
None ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s
0 ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
1 ; RUN: llc < %s -mtriple=thumbeb -mattr=v7,neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
12
23 ; PR15525
34 ; CHECK-LABEL: test1:
45 ; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
5 ; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2
6 ; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
6 ; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r1, r2
7 ; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
8 ; CHECK-BE-NEXT: vmov {{d[0-9]+}}, r2, r1
9 ; CHECK-BE-NEXT: vmov {{d[0-9]+}}, [[REG]], r3
710 ; CHECK-NEXT: vst1.8 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0]
811 ; CHECK-NEXT: bx lr
912 define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
0 ; RUN: llc -verify-machineinstrs < %s -march=arm -mattr=v7,neon | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
1 ; RUN: llc -verify-machineinstrs < %s -march=armeb -mattr=v7,neon | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
2
3 @var32 = global i32 0
4 @vardouble = global double 0.0
5
6 define void @arg_longint( i64 %val ) {
7 ; CHECK-LABEL: arg_longint:
8 ; CHECK-LE: str r0, [r1]
9 ; CHECK-BE: str r1, [r0]
10 %tmp = trunc i64 %val to i32
11 store i32 %tmp, i32* @var32
12 ret void
13 }
14
15 define void @arg_double( double %val ) {
16 ; CHECK-LABEL: arg_double:
17 ; CHECK: strd r0, r1, [r2]
18 store double %val, double* @vardouble
19 ret void
20 }
21
22 define void @arg_v4i32(<4 x i32> %vec ) {
23 ; CHECK-LABEL: arg_v4i32:
24 ; CHECK-LE: vmov d17, r2, r3
25 ; CHECK-LE: vmov d16, r0, r1
26 ; CHECK-BE: vmov d17, r3, r2
27 ; CHECK-BE: vmov d16, r1, r0
28 ; CHECK: vst1.32 {d16[0]}, [r0:32]
29 %tmp = extractelement <4 x i32> %vec, i32 0
30 store i32 %tmp, i32* @var32
31 ret void
32 }
33
34 define void @arg_v2f64(<2 x double> %vec ) {
35 ; CHECK-LABEL: arg_v2f64:
36 ; CHECK: strd r0, r1, [r2]
37 %tmp = extractelement <2 x double> %vec, i32 0
38 store double %tmp, double* @vardouble
39 ret void
40 }
41
42 define i64 @return_longint() {
43 ; CHECK-LABEL: return_longint:
44 ; CHECK-LE: mov r0, #42
45 ; CHECK-LE: mov r1, #0
46 ; CHECK-BE: mov r0, #0
47 ; CHECK-BE: mov r1, #42
48 ret i64 42
49 }
50
51 define double @return_double() {
52 ; CHECK-LABEL: return_double:
53 ; CHECK-LE: vmov r0, r1, d16
54 ; CHECK-BE: vmov r1, r0, d16
55 ret double 1.0
56 }
57
58 define <4 x i32> @return_v4i32() {
59 ; CHECK-LABEL: return_v4i32:
60 ; CHECK-LE: vmov r0, r1, d16
61 ; CHECK-LE: vmov r2, r3, d17
62 ; CHECK-BE: vmov r1, r0, d16
63 ; CHECK-BE: vmov r3, r2, d17
64 ret < 4 x i32> < i32 42, i32 43, i32 44, i32 45 >
65 }
66
67 define <2 x double> @return_v2f64() {
68 ; CHECK-LABEL: return_v2f64:
69 ; CHECK-LE: vmov r0, r1, d16
70 ; CHECK-LE: vmov r2, r3, d17
71 ; CHECK-BE: vmov r1, r0, d16
72 ; CHECK-BE: vmov r3, r2, d17
73 ret <2 x double> < double 3.14, double 6.28 >
74 }
75
76 define void @caller_arg_longint() {
77 ; CHECK-LABEL: caller_arg_longint:
78 ; CHECK-LE: mov r0, #42
79 ; CHECK-LE: mov r1, #0
80 ; CHECK-BE: mov r0, #0
81 ; CHECK-BE: mov r1, #42
82 call void @arg_longint( i64 42 )
83 ret void
84 }
85
86 define void @caller_arg_double() {
87 ; CHECK-LABEL: caller_arg_double:
88 ; CHECK-LE: vmov r0, r1, d16
89 ; CHECK-BE: vmov r1, r0, d16
90 call void @arg_double( double 1.0 )
91 ret void
92 }
93
94 define void @caller_return_longint() {
95 ; CHECK-LABEL: caller_return_longint:
96 ; CHECK-LE: str r0, [r1]
97 ; CHECK-BE: str r1, [r0]
98 %val = call i64 @return_longint()
99 %tmp = trunc i64 %val to i32
100 store i32 %tmp, i32* @var32
101 ret void
102 }
103
104 define void @caller_return_double() {
105 ; CHECK-LABEL: caller_return_double:
106 ; CHECK-LE: vmov d17, r0, r1
107 ; CHECK-BE: vmov d17, r1, r0
108 %val = call double @return_double( )
109 %tmp = fadd double %val, 3.14
110 store double %tmp, double* @vardouble
111 ret void
112 }
113
114 define void @caller_return_v2f64() {
115 ; CHECK-LABEL: caller_return_v2f64:
116 ; CHECK: strd r0, r1, [r2]
117 %val = call <2 x double> @return_v2f64( )
118 %tmp = extractelement <2 x double> %val, i32 0
119 store double %tmp, double* @vardouble
120 ret void
121 }
122
123
None ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
1 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE
2 ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
3 ; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE
24 ; Check generated signed and unsigned multiply accumulate long.
35
46 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
5254 ; function, both after the umlal. With it, *some* move has to happen
5355 ; before the umlal.
5456 define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) {
55 ; CHECK-V7-LABEL: MACLongTest5:
56 ; CHECK-V7-LABEL: umlal r0, r1, r0, r0
57 ; CHECK-V7-LE-LABEL: MACLongTest5:
58 ; CHECK-V7-LE-LABEL: umlal r0, r1, r0, r0
59 ; CHECK-V7-BE-LABEL: MACLongTest5:
60 ; CHECK-V7-BE-LABEL: umlal r1, r0, r1, r1
5761
5862 ; CHECK-LABEL: MACLongTest5:
59 ; CHECK: mov [[RDLO:r[0-9]+]], r0
60 ; CHECK: umlal [[RDLO]], r1, r0, r0
61 ; CHECK: mov r0, [[RDLO]]
63 ; CHECK-LE: mov [[RDLO:r[0-9]+]], r0
64 ; CHECK-LE: umlal [[RDLO]], r1, r0, r0
65 ; CHECK-LE: mov r0, [[RDLO]]
66 ; CHECK-BE: mov [[RDLO:r[0-9]+]], r1
67 ; CHECK-BE: umlal [[RDLO]], r0, r1, r1
68 ; CHECK-BE: mov r1, [[RDLO]]
6269
6370 %conv.trunc = trunc i64 %c to i32
6471 %conv = zext i32 %conv.trunc to i64
None ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
1 ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
12
23 define i64 @f0(i64 %A, i64 %B) {
34 ; CHECK-LABEL: f0:
4 ; CHECK: lsrs r3, r3, #1
5 ; CHECK-NEXT: rrx r2, r2
6 ; CHECK-NEXT: subs r0, r0, r2
7 ; CHECK-NEXT: sbc r1, r1, r3
5 ; CHECK-LE: lsrs r3, r3, #1
6 ; CHECK-LE-NEXT: rrx r2, r2
7 ; CHECK-LE-NEXT: subs r0, r0, r2
8 ; CHECK-LE-NEXT: sbc r1, r1, r3
9 ; CHECK-BE: lsrs r2, r2, #1
10 ; CHECK-BE-NEXT: rrx r3, r3
11 ; CHECK-BE-NEXT: subs r1, r1, r3
12 ; CHECK-BE-NEXT: sbc r0, r0, r2
813 %tmp = bitcast i64 %A to i64
914 %tmp2 = lshr i64 %B, 1
1015 %tmp3 = sub i64 %tmp, %tmp2
1318
1419 define i32 @f1(i64 %x, i64 %y) {
1520 ; CHECK-LABEL: f1:
16 ; CHECK: lsl{{.*}}r2
21 ; CHECK-LE: lsl{{.*}}r2
22 ; CHECK-BE: lsl{{.*}}r3
1723 %a = shl i64 %x, %y
1824 %b = trunc i64 %a to i32
1925 ret i32 %b
2127
2228 define i32 @f2(i64 %x, i64 %y) {
2329 ; CHECK-LABEL: f2:
24 ; CHECK: lsr{{.*}}r2
25 ; CHECK-NEXT: rsb r3, r2, #32
26 ; CHECK-NEXT: sub r2, r2, #32
27 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
28 ; CHECK-NEXT: cmp r2, #0
29 ; CHECK-NEXT: asrge r0, r1, r2
30 ; CHECK-LE: lsr{{.*}}r2
31 ; CHECK-LE-NEXT: rsb r3, r2, #32
32 ; CHECK-LE-NEXT: sub r2, r2, #32
33 ; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
34 ; CHECK-LE-NEXT: cmp r2, #0
35 ; CHECK-LE-NEXT: asrge r0, r1, r2
36
37 ; CHECK-BE: lsr{{.*}}r3
38 ; CHECK-BE-NEXT: rsb r2, r3, #32
39 ; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
40 ; CHECK-BE-NEXT: sub r2, r3, #32
41 ; CHECK-BE-NEXT: cmp r2, #0
42 ; CHECK-BE-NEXT: asrge r1, r0, r2
43
3044 %a = ashr i64 %x, %y
3145 %b = trunc i64 %a to i32
3246 ret i32 %b
3448
3549 define i32 @f3(i64 %x, i64 %y) {
3650 ; CHECK-LABEL: f3:
37 ; CHECK: lsr{{.*}}r2
38 ; CHECK-NEXT: rsb r3, r2, #32
39 ; CHECK-NEXT: sub r2, r2, #32
40 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
41 ; CHECK-NEXT: cmp r2, #0
42 ; CHECK-NEXT: lsrge r0, r1, r2
51 ; CHECK-LE: lsr{{.*}}r2
52 ; CHECK-LE-NEXT: rsb r3, r2, #32
53 ; CHECK-LE-NEXT: sub r2, r2, #32
54 ; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
55 ; CHECK-LE-NEXT: cmp r2, #0
56 ; CHECK-LE-NEXT: lsrge r0, r1, r2
57
58 ; CHECK-BE: lsr{{.*}}r3
59 ; CHECK-BE-NEXT: rsb r2, r3, #32
60 ; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
61 ; CHECK-BE-NEXT: sub r2, r3, #32
62 ; CHECK-BE-NEXT: cmp r2, #0
63 ; CHECK-BE-NEXT: lsrge r1, r0, r2
64
4365 %a = lshr i64 %x, %y
4466 %b = trunc i64 %a to i32
4567 ret i32 %b
None ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
1 ; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
12
23 ; 171 = 0x000000ab
34 define i64 @f1(i64 %a) {
45 ; CHECK: f1
5 ; CHECK: subs r0, r0, #171
6 ; CHECK: sbc r1, r1, #0
6 ; CHECK-LE: subs r0, r0, #171
7 ; CHECK-LE: sbc r1, r1, #0
8 ; CHECK-BE: subs r1, r1, #171
9 ; CHECK-BE: sbc r0, r0, #0
710 %tmp = sub i64 %a, 171
811 ret i64 %tmp
912 }
1114 ; 66846720 = 0x03fc0000
1215 define i64 @f2(i64 %a) {
1316 ; CHECK: f2
14 ; CHECK: subs r0, r0, #66846720
15 ; CHECK: sbc r1, r1, #0
17 ; CHECK-LE: subs r0, r0, #66846720
18 ; CHECK-LE: sbc r1, r1, #0
19 ; CHECK-BE: subs r1, r1, #66846720
20 ; CHECK-BE: sbc r0, r0, #0
1621 %tmp = sub i64 %a, 66846720
1722 ret i64 %tmp
1823 }
2025 ; 734439407618 = 0x000000ab00000002
2126 define i64 @f3(i64 %a) {
2227 ; CHECK: f3
23 ; CHECK: subs r0, r0, #2
24 ; CHECK: sbc r1, r1, #171
28 ; CHECK-LE: subs r0, r0, #2
29 ; CHECK-LE: sbc r1, r1, #171
30 ; CHECK-BE: subs r1, r1, #2
31 ; CHECK-BE: sbc r0, r0, #171
2532 %tmp = sub i64 %a, 734439407618
2633 ret i64 %tmp
2734 }
None ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
1 ; RUN: llc -mtriple=armeb-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
12
23 define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
34 ; CHECK: vcombine8
4 ; CHECK: vmov r0, r1, d16
5 ; CHECK: vmov r2, r3, d17
5 ; CHECK-LE: vmov r0, r1, d16
6 ; CHECK-LE: vmov r2, r3, d17
7 ; CHECK-BE: vmov r1, r0, d16
8 ; CHECK-BE: vmov r3, r2, d17
69 %tmp1 = load <8 x i8>* %A
710 %tmp2 = load <8 x i8>* %B
811 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32>
1114
1215 define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
1316 ; CHECK: vcombine16
14 ; CHECK: vmov r0, r1, d16
15 ; CHECK: vmov r2, r3, d17
17 ; CHECK-LE: vmov r0, r1, d16
18 ; CHECK-LE: vmov r2, r3, d17
19 ; CHECK-BE: vmov r1, r0, d16
20 ; CHECK-BE: vmov r3, r2, d17
1621 %tmp1 = load <4 x i16>* %A
1722 %tmp2 = load <4 x i16>* %B
1823 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32>
2126
2227 define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
2328 ; CHECK: vcombine32
24 ; CHECK: vmov r0, r1, d16
25 ; CHECK: vmov r2, r3, d17
29 ; CHECK-LE: vmov r0, r1, d16
30 ; CHECK-LE: vmov r2, r3, d17
31 ; CHECK-BE: vmov r1, r0, d16
32 ; CHECK-BE: vmov r3, r2, d17
2633 %tmp1 = load <2 x i32>* %A
2734 %tmp2 = load <2 x i32>* %B
2835 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32>
3138
3239 define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
3340 ; CHECK: vcombinefloat
34 ; CHECK: vmov r0, r1, d16
35 ; CHECK: vmov r2, r3, d17
41 ; CHECK-LE: vmov r0, r1, d16
42 ; CHECK-LE: vmov r2, r3, d17
43 ; CHECK-BE: vmov r1, r0, d16
44 ; CHECK-BE: vmov r3, r2, d17
3645 %tmp1 = load <2 x float>* %A
3746 %tmp2 = load <2 x float>* %B
3847 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32>
4150
4251 define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
4352 ; CHECK: vcombine64
44 ; CHECK: vmov r0, r1, d16
45 ; CHECK: vmov r2, r3, d17
53 ; CHECK-LE: vmov r0, r1, d16
54 ; CHECK-LE: vmov r2, r3, d17
55 ; CHECK-BE: vmov r1, r0, d16
56 ; CHECK-BE: vmov r3, r2, d17
4657 %tmp1 = load <1 x i64>* %A
4758 %tmp2 = load <1 x i64>* %B
4859 %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32>
5566 define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind {
5667 ; CHECK: vget_low16
5768 ; CHECK-NOT: vst
58 ; CHECK: vmov r0, r1, d16
69 ; CHECK-LE: vmov r0, r1, d16
70 ; CHECK-BE: vmov r1, r0, d16
5971 %tmp1 = load <8 x i16>* %A
6072 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32>
6173 ret <4 x i16> %tmp2
6476 define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind {
6577 ; CHECK: vget_high8
6678 ; CHECK-NOT: vst
67 ; CHECK: vmov r0, r1, d17
79 ; CHECK-LE: vmov r0, r1, d17
80 ; CHECK-BE: vmov r1, r0, d17
6881 %tmp1 = load <16 x i8>* %A
6982 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32>
7083 ret <8 x i8> %tmp2