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80 column cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 10 years ago
3 changed file(s) with 37 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
5252 "Disable VFP MAC instructions">;
5353 // Some processors benefit from using NEON instructions for scalar
5454 // single-precision FP operations.
55 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
56 "true",
57 "Use NEON for single precision FP">;
55 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
56 "true",
57 "Use NEON for single precision FP">;
5858
5959 // Disable 32-bit to 16-bit narrowing for experimentation.
6060 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
23252325 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
23262326 Defs = [CPSR] in {
23272327 def BCCi64 : PseudoInst<(outs),
2328 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2329 IIC_Br,
2328 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2329 IIC_Br,
23302330 "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc",
23312331 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
23322332
17301730 // Extra precision multiplies with low / high results
17311731 let neverHasSideEffects = 1 in {
17321732 let isCommutable = 1 in {
1733 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1733 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1734 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
17341735 "smull", "\t$ldst, $hdst, $a, $b", []> {
17351736 let Inst{31-27} = 0b11111;
17361737 let Inst{26-23} = 0b0111;
17381739 let Inst{7-4} = 0b0000;
17391740 }
17401741
1741 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1742 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1743 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
17421744 "umull", "\t$ldst, $hdst, $a, $b", []> {
17431745 let Inst{31-27} = 0b11111;
17441746 let Inst{26-23} = 0b0111;
17481750 } // isCommutable
17491751
17501752 // Multiply + accumulate
1751 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1753 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1754 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
17521755 "smlal", "\t$ldst, $hdst, $a, $b", []>{
17531756 let Inst{31-27} = 0b11111;
17541757 let Inst{26-23} = 0b0111;
17561759 let Inst{7-4} = 0b0000;
17571760 }
17581761
1759 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1762 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1763 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
17601764 "umlal", "\t$ldst, $hdst, $a, $b", []>{
17611765 let Inst{31-27} = 0b11111;
17621766 let Inst{26-23} = 0b0111;
17641768 let Inst{7-4} = 0b0000;
17651769 }
17661770
1767 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1771 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1772 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
17681773 "umaal", "\t$ldst, $hdst, $a, $b", []>{
17691774 let Inst{31-27} = 0b11111;
17701775 let Inst{26-23} = 0b0111;
18051810 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
18061811 }
18071812
1808 def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1813 def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
18091814 "smmlar", "\t$dst, $a, $b, $c", []> {
18101815 let Inst{31-27} = 0b11111;
18111816 let Inst{26-23} = 0b0110;
18141819 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
18151820 }
18161821
1817 def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1822 def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
18181823 "smmls", "\t$dst, $a, $b, $c",
18191824 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
18201825 let Inst{31-27} = 0b11111;
18241829 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
18251830 }
18261831
1827 def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1832 def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
18281833 "smmlsr", "\t$dst, $a, $b, $c", []> {
18291834 let Inst{31-27} = 0b11111;
18301835 let Inst{26-23} = 0b0110;
19251930 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
19261931 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
19271932 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1928 (sra rGPR:$b, (i32 16)))))]> {
1933 (sra rGPR:$b, (i32 16)))))]> {
19291934 let Inst{31-27} = 0b11111;
19301935 let Inst{26-23} = 0b0110;
19311936 let Inst{22-20} = 0b001;
19371942 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
19381943 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
19391944 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1940 (sext_inreg rGPR:$b, i16))))]> {
1945 (sext_inreg rGPR:$b, i16))))]> {
19411946 let Inst{31-27} = 0b11111;
19421947 let Inst{26-23} = 0b0110;
19431948 let Inst{22-20} = 0b001;
19491954 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
19501955 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
19511956 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1952 (sra rGPR:$b, (i32 16)))))]> {
1957 (sra rGPR:$b, (i32 16)))))]> {
19531958 let Inst{31-27} = 0b11111;
19541959 let Inst{26-23} = 0b0110;
19551960 let Inst{22-20} = 0b001;
19611966 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
19621967 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
19631968 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1964 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
1969 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
19651970 let Inst{31-27} = 0b11111;
19661971 let Inst{26-23} = 0b0110;
19671972 let Inst{22-20} = 0b011;
19731978 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
19741979 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
19751980 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1976 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
1981 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
19771982 let Inst{31-27} = 0b11111;
19781983 let Inst{26-23} = 0b0110;
19791984 let Inst{22-20} = 0b011;
19881993
19891994 // Halfword multiple accumulate long: SMLAL -- for disassembly only
19901995 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
1991 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1996 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
19921997 [/* For disassembly only; pattern left blank */]>;
19931998 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
1994 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1999 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
19952000 [/* For disassembly only; pattern left blank */]>;
19962001 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
1997 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2002 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
19982003 [/* For disassembly only; pattern left blank */]>;
19992004 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2000 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2005 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
20012006 [/* For disassembly only; pattern left blank */]>;
20022007
20032008 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
20042009 // These are for disassembly only.
20052010
2006 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2007 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2011 def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2012 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
20082013 let Inst{15-12} = 0b1111;
20092014 }
2010 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2011 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2015 def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2016 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
20122017 let Inst{15-12} = 0b1111;
20132018 }
2014 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2015 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2019 def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2020 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
20162021 let Inst{15-12} = 0b1111;
20172022 }
2018 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2019 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2023 def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2024 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
20202025 let Inst{15-12} = 0b1111;
20212026 }
20222027 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
20672072 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
20682073
20692074 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2070 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2075 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
20712076
20722077 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
20732078 "rev16", ".w\t$dst, $src",
20752080 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
20762081 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
20772082 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2078 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2083 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
20792084
20802085 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
20812086 "revsh", ".w\t$dst, $src",