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[ARM] VQSUB instruction Same as VQADD, VQSUB can be selected from llvm.ssub.sat intrinsics. Differential Revision: https://reviews.llvm.org/D68567 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374377 91177308-0d34-0410-b5e6-96231b3b80d8 David Green 11 months ago
3 changed file(s) with 16 addition(s) and 51 deletion(s). Raw diff Collapse all Expand all
266266 setOperationAction(ISD::BSWAP, VT, Legal);
267267 setOperationAction(ISD::SADDSAT, VT, Legal);
268268 setOperationAction(ISD::UADDSAT, VT, Legal);
269 setOperationAction(ISD::SSUBSAT, VT, Legal);
270 setOperationAction(ISD::USUBSAT, VT, Legal);
269271
270272 // No native support for these.
271273 setOperationAction(ISD::UDIV, VT, Expand);
15651565 foreach instr = [MVE_VQADDs8, MVE_VQADDs16, MVE_VQADDs32] in
15661566 foreach VT = [instr.VT] in
15671567 def : Pat<(VT (saddsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
1568 (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
1569 foreach instr = [MVE_VQSUBu8, MVE_VQSUBu16, MVE_VQSUBu32] in
1570 foreach VT = [instr.VT] in
1571 def : Pat<(VT (usubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
1572 (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
1573 foreach instr = [MVE_VQSUBs8, MVE_VQSUBs16, MVE_VQSUBs32] in
1574 foreach VT = [instr.VT] in
1575 def : Pat<(VT (ssubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
15681576 (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
15691577 }
15701578
190190 define arm_aapcs_vfpcc <16 x i8> @ssub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
191191 ; CHECK-LABEL: ssub_int8_t:
192192 ; CHECK: @ %bb.0: @ %entry
193 ; CHECK-NEXT: .vsave {d8, d9}
194 ; CHECK-NEXT: vpush {d8, d9}
195 ; CHECK-NEXT: vsub.i8 q2, q0, q1
196 ; CHECK-NEXT: vmov.i8 q3, #0x80
197 ; CHECK-NEXT: vcmp.s8 lt, q2, zr
198 ; CHECK-NEXT: vmov.i8 q4, #0x7f
199 ; CHECK-NEXT: vpsel q3, q4, q3
200 ; CHECK-NEXT: vcmp.s8 gt, q0, q2
201 ; CHECK-NEXT: vmrs r0, p0
202 ; CHECK-NEXT: vcmp.s8 gt, q1, zr
203 ; CHECK-NEXT: vmrs r1, p0
204 ; CHECK-NEXT: eors r0, r1
205 ; CHECK-NEXT: vmsr p0, r0
206 ; CHECK-NEXT: vpsel q0, q3, q2
207 ; CHECK-NEXT: vpop {d8, d9}
193 ; CHECK-NEXT: vqsub.s8 q0, q0, q1
208194 ; CHECK-NEXT: bx lr
209195 entry:
210196 %0 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
214200 define arm_aapcs_vfpcc <8 x i16> @ssub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
215201 ; CHECK-LABEL: ssub_int16_t:
216202 ; CHECK: @ %bb.0: @ %entry
217 ; CHECK-NEXT: .vsave {d8, d9}
218 ; CHECK-NEXT: vpush {d8, d9}
219 ; CHECK-NEXT: vsub.i16 q2, q0, q1
220 ; CHECK-NEXT: vmov.i16 q3, #0x8000
221 ; CHECK-NEXT: vcmp.s16 lt, q2, zr
222 ; CHECK-NEXT: vmvn.i16 q4, #0x8000
223 ; CHECK-NEXT: vpsel q3, q4, q3
224 ; CHECK-NEXT: vcmp.s16 gt, q0, q2
225 ; CHECK-NEXT: vmrs r0, p0
226 ; CHECK-NEXT: vcmp.s16 gt, q1, zr
227 ; CHECK-NEXT: vmrs r1, p0
228 ; CHECK-NEXT: eors r0, r1
229 ; CHECK-NEXT: vmsr p0, r0
230 ; CHECK-NEXT: vpsel q0, q3, q2
231 ; CHECK-NEXT: vpop {d8, d9}
203 ; CHECK-NEXT: vqsub.s16 q0, q0, q1
232204 ; CHECK-NEXT: bx lr
233205 entry:
234206 %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
238210 define arm_aapcs_vfpcc <4 x i32> @ssub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
239211 ; CHECK-LABEL: ssub_int32_t:
240212 ; CHECK: @ %bb.0: @ %entry
241 ; CHECK-NEXT: .vsave {d8, d9}
242 ; CHECK-NEXT: vpush {d8, d9}
243 ; CHECK-NEXT: vsub.i32 q2, q0, q1
244 ; CHECK-NEXT: vmov.i32 q3, #0x80000000
245 ; CHECK-NEXT: vcmp.s32 lt, q2, zr
246 ; CHECK-NEXT: vmvn.i32 q4, #0x80000000
247 ; CHECK-NEXT: vpsel q3, q4, q3
248 ; CHECK-NEXT: vcmp.s32 gt, q0, q2
249 ; CHECK-NEXT: vmrs r0, p0
250 ; CHECK-NEXT: vcmp.s32 gt, q1, zr
251 ; CHECK-NEXT: vmrs r1, p0
252 ; CHECK-NEXT: eors r0, r1
253 ; CHECK-NEXT: vmsr p0, r0
254 ; CHECK-NEXT: vpsel q0, q3, q2
255 ; CHECK-NEXT: vpop {d8, d9}
213 ; CHECK-NEXT: vqsub.s32 q0, q0, q1
256214 ; CHECK-NEXT: bx lr
257215 entry:
258216 %0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
357315 define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
358316 ; CHECK-LABEL: usub_int8_t:
359317 ; CHECK: @ %bb.0: @ %entry
360 ; CHECK-NEXT: vmax.u8 q0, q0, q1
361 ; CHECK-NEXT: vsub.i8 q0, q0, q1
318 ; CHECK-NEXT: vqsub.u8 q0, q0, q1
362319 ; CHECK-NEXT: bx lr
363320 entry:
364321 %0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
368325 define arm_aapcs_vfpcc <8 x i16> @usub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
369326 ; CHECK-LABEL: usub_int16_t:
370327 ; CHECK: @ %bb.0: @ %entry
371 ; CHECK-NEXT: vmax.u16 q0, q0, q1
372 ; CHECK-NEXT: vsub.i16 q0, q0, q1
328 ; CHECK-NEXT: vqsub.u16 q0, q0, q1
373329 ; CHECK-NEXT: bx lr
374330 entry:
375331 %0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
379335 define arm_aapcs_vfpcc <4 x i32> @usub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
380336 ; CHECK-LABEL: usub_int32_t:
381337 ; CHECK: @ %bb.0: @ %entry
382 ; CHECK-NEXT: vmax.u32 q0, q0, q1
383 ; CHECK-NEXT: vsub.i32 q0, q0, q1
338 ; CHECK-NEXT: vqsub.u32 q0, q0, q1
384339 ; CHECK-NEXT: bx lr
385340 entry:
386341 %0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)