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Merging r214716: ------------------------------------------------------------------------ r214716 | uweigand | 2014-08-04 08:27:12 -0500 (Mon, 04 Aug 2014) | 9 lines [PowerPC] MULHU/MULHS are not legal for vector types I ran into some test failures where common code changed vector division by constant into a multiply-high operation (MULHU). But these are not implemented by the back-end, so we failed to recognize the insn. Fixed by marking MULHU/MULHS as Expand for vector types. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214818 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 6 years ago
2 changed file(s) with 12 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
452452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
453453 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
454454 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
455 setOperationAction(ISD::MULHU, VT, Expand);
456 setOperationAction(ISD::MULHS, VT, Expand);
455457 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
456458 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
457459 setOperationAction(ISD::UDIVREM, VT, Expand);
0 ; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s
1
2 ; Common code used to replace the urem by a mulhu, and compilation would
3 ; then crash since mulhu isn't supported on vector types.
4
5 define <4 x i32> @test(<4 x i32> %x) {
6 entry:
7 %0 = urem <4 x i32> %x,
8 ret <4 x i32> %0
9 }