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[RISCV] Codegen support for materializing constants Differential Revision: https://reviews.llvm.org/D39101 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317684 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 11 months ago
3 changed file(s) with 71 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
8484 let EncoderMethod = "getImmOpValueAsr1";
8585 let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
8686 }
87
88 // Standalone (codegen-only) immleaf patterns.
89 def simm32 : ImmLeaf(Imm);}]>;
90
91 // Extract least significant 12 bits from an immediate value and sign extend
92 // them.
93 def LO12Sext : SDNodeXForm
94 return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),
95 SDLoc(N), N->getValueType(0));
96 }]>;
97
98 // Extract the most significant 20 bits from an immediate value. Add 1 if bit
99 // 11 is 1, to compensate for the low 12 bits in the matching immediate addi
100 // or ld/st being negative.
101 def HI20 : SDNodeXForm
102 return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
103 SDLoc(N), N->getValueType(0));
104 }]>;
87105
88106 //===----------------------------------------------------------------------===//
89107 // Instruction Class Templates
255273 class PatGprUimm5
256274 : Pat<(OpNode GPR:$rs1, uimm5:$shamt),
257275 (Inst GPR:$rs1, uimm5:$shamt)>;
276
277 /// Immediates
278
279 def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
280 // TODO: Add a pattern for immediates with all zeroes in the lower 12 bits.
281 def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
258282
259283 /// Simple arithmetic operations
260284
66 ; RV32I-LABEL: addi:
77 ; RV32I: addi a0, a0, 1
88 ; RV32I: jalr zero, ra, 0
9 ; TODO: check support for materialising larger constants
109 %1 = add i32 %a, 1
1110 ret i32 %1
1211 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
2 ; RUN: | FileCheck %s -check-prefix=RV32I
3
4 ; Materializing constants
5
6 define i32 @zero() nounwind {
7 ; RV32I-LABEL: zero:
8 ; RV32I: # BB#0:
9 ; RV32I-NEXT: addi a0, zero, 0
10 ; RV32I-NEXT: jalr zero, ra, 0
11 ret i32 0
12 }
13
14 define i32 @pos_small() nounwind {
15 ; RV32I-LABEL: pos_small:
16 ; RV32I: # BB#0:
17 ; RV32I-NEXT: addi a0, zero, 2047
18 ; RV32I-NEXT: jalr zero, ra, 0
19 ret i32 2047
20 }
21
22 define i32 @neg_small() nounwind {
23 ; RV32I-LABEL: neg_small:
24 ; RV32I: # BB#0:
25 ; RV32I-NEXT: addi a0, zero, -2048
26 ; RV32I-NEXT: jalr zero, ra, 0
27 ret i32 -2048
28 }
29
30 define i32 @pos_i32() nounwind {
31 ; RV32I-LABEL: pos_i32:
32 ; RV32I: # BB#0:
33 ; RV32I-NEXT: lui a0, 423811
34 ; RV32I-NEXT: addi a0, a0, -1297
35 ; RV32I-NEXT: jalr zero, ra, 0
36 ret i32 1735928559
37 }
38
39 define i32 @neg_i32() nounwind {
40 ; RV32I-LABEL: neg_i32:
41 ; RV32I: # BB#0:
42 ; RV32I-NEXT: lui a0, 912092
43 ; RV32I-NEXT: addi a0, a0, -273
44 ; RV32I-NEXT: jalr zero, ra, 0
45 ret i32 -559038737
46 }