llvm.org GIT mirror llvm / c5a2a33
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 7 years ago
3 changed file(s) with 76 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
26892689 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
26902690 unsigned align = fieldFromInstruction32(Insn, 4, 1);
26912691 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2692 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
26932692 align *= 2*size;
26942693
26952694 switch (Inst.getOpcode()) {
27202719 return MCDisassembler::Fail;
27212720 Inst.addOperand(MCOperand::CreateImm(align));
27222721
2723 if (Rm == 0xD)
2724 Inst.addOperand(MCOperand::CreateReg(0));
2725 else if (Rm != 0xF) {
2722 if (Rm != 0xD && Rm != 0xF) {
27262723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
27272724 return MCDisassembler::Fail;
27282725 }
2729
2730 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2731 return MCDisassembler::Fail;
27322726
27332727 return S;
27342728 }
22422242 # CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
22432243 0x8f 0x81 0x24 0xf4
22442244 # CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
2245
2246 # rdar://11256967
2247 0x0f 0x0d 0xa2 0xf4
2248 # CHECK: vld2.8 {d0[], d1[]}, [r2]
2249 0x4f 0x0d 0xa2 0xf4
2250 # CHECK: vld2.16 {d0[], d1[]}, [r2]
2251 0x8f 0x0d 0xa2 0xf4
2252 # CHECK: vld2.32 {d0[], d1[]}, [r2]
2253 0x0d 0x0d 0xa2 0xf4
2254 # CHECK: vld2.8 {d0[], d1[]}, [r2]!
2255 0x4d 0x0d 0xa2 0xf4
2256 # CHECK: vld2.16 {d0[], d1[]}, [r2]!
2257 0x8d 0x0d 0xa2 0xf4
2258 # CHECK: vld2.32 {d0[], d1[]}, [r2]!
2259 0x03 0x0d 0xa2 0xf4
2260 # CHECK: vld2.8 {d0[], d1[]}, [r2], r3
2261 0x43 0x0d 0xa2 0xf4
2262 # CHECK: vld2.16 {d0[], d1[]}, [r2], r3
2263 0x83 0x0d 0xa2 0xf4
2264 # CHECK: vld2.32 {d0[], d1[]}, [r2], r3
2265 0x2f 0x0d 0xa3 0xf4
2266 # CHECK: vld2.8 {d0[], d2[]}, [r3]
2267 0x6f 0x0d 0xa3 0xf4
2268 # CHECK: vld2.16 {d0[], d2[]}, [r3]
2269 0xaf 0x0d 0xa3 0xf4
2270 # CHECK: vld2.32 {d0[], d2[]}, [r3]
2271 0x2d 0x0d 0xa3 0xf4
2272 # CHECK: vld2.8 {d0[], d2[]}, [r3]!
2273 0x6d 0x0d 0xa3 0xf4
2274 # CHECK: vld2.16 {d0[], d2[]}, [r3]!
2275 0xad 0x0d 0xa3 0xf4
2276 # CHECK: vld2.32 {d0[], d2[]}, [r3]!
2277 0x24 0x0d 0xa3 0xf4
2278 # CHECK: vld2.8 {d0[], d2[]}, [r3], r4
2279 0x64 0x0d 0xa3 0xf4
2280 0xa4 0x0d 0xa3 0xf4
2281 # CHECK: vld2.32 {d0[], d2[]}, [r3], r4
19591959 # CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
19601960 0x24 0xf9 0x8f 0x81
19611961 # CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
1962
1963 # rdar://11256967
1964 0xa2 0xf9 0x0f 0x0d
1965 # CHECK: vld2.8 {d0[], d1[]}, [r2]
1966 0xa2 0xf9 0x4f 0x0d
1967 # CHECK: vld2.16 {d0[], d1[]}, [r2]
1968 0xa2 0xf9 0x8f 0x0d
1969 # CHECK: vld2.32 {d0[], d1[]}, [r2]
1970 0xa2 0xf9 0x0d 0x0d
1971 # CHECK: vld2.8 {d0[], d1[]}, [r2]!
1972 0xa2 0xf9 0x4d 0x0d
1973 # CHECK: vld2.16 {d0[], d1[]}, [r2]!
1974 0xa2 0xf9 0x8d 0x0d
1975 # CHECK: vld2.32 {d0[], d1[]}, [r2]!
1976 0xa2 0xf9 0x03 0x0d
1977 # CHECK: vld2.8 {d0[], d1[]}, [r2], r3
1978 0xa2 0xf9 0x43 0x0d
1979 # CHECK: vld2.16 {d0[], d1[]}, [r2], r3
1980 0xa2 0xf9 0x83 0x0d
1981 # CHECK: vld2.32 {d0[], d1[]}, [r2], r3
1982 0xa3 0xf9 0x2f 0x0d
1983 # CHECK: vld2.8 {d0[], d2[]}, [r3]
1984 0xa3 0xf9 0x6f 0x0d
1985 # CHECK: vld2.16 {d0[], d2[]}, [r3]
1986 0xa3 0xf9 0xaf 0x0d
1987 # CHECK: vld2.32 {d0[], d2[]}, [r3]
1988 0xa3 0xf9 0x2d 0x0d
1989 # CHECK: vld2.8 {d0[], d2[]}, [r3]!
1990 0xa3 0xf9 0x6d 0x0d
1991 # CHECK: vld2.16 {d0[], d2[]}, [r3]!
1992 0xa3 0xf9 0xad 0x0d
1993 # CHECK: vld2.32 {d0[], d2[]}, [r3]!
1994 0xa3 0xf9 0x24 0x0d
1995 # CHECK: vld2.8 {d0[], d2[]}, [r3], r4
1996 0xa3 0xf9 0x64 0x0d
1997 # CHECK: vld2.16 {d0[], d2[]}, [r3], r4
1998 0xa3 0xf9 0xa4 0x0d
1999 # CHECK: vld2.32 {d0[], d2[]}, [r3], r4