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Stub out a PostMachineScheduler pass. Placeholder and boilerplate for a PostRA MachineScheduler pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198120 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 6 years ago
5 changed file(s) with 96 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
206206 /// Fully developed targets will not generally override this.
207207 virtual void addMachinePasses();
208208
209 /// createTargetScheduler - Create an instance of ScheduleDAGInstrs to be run
210 /// within the standard MachineScheduler pass for this function and target at
211 /// the current optimization level.
209 /// Create an instance of ScheduleDAGInstrs to be run within the standard
210 /// MachineScheduler pass for this function and target at the current
211 /// optimization level.
212212 ///
213213 /// This can also be used to plug a new MachineSchedStrategy into an instance
214214 /// of the standard ScheduleDAGMI:
217217 /// Return NULL to select the default (generic) machine scheduler.
218218 virtual ScheduleDAGInstrs *
219219 createMachineScheduler(MachineSchedContext *C) const {
220 return 0;
221 }
222
223 /// Similar to createMachineScheduler but used when postRA machine scheduling
224 /// is enabled.
225 virtual ScheduleDAGInstrs *
226 createPostMachineScheduler(MachineSchedContext *C) const {
220227 return 0;
221228 }
222229
402409 /// MachineScheduler - This pass schedules machine instructions.
403410 extern char &MachineSchedulerID;
404411
412 /// PostMachineScheduler - This pass schedules machine instructions postRA.
413 extern char &PostMachineSchedulerID;
414
405415 /// SpillPlacement analysis. Suggest optimal placement of spill code between
406416 /// basic blocks.
407417 extern char &SpillPlacementID;
209209 void initializePostDomViewerPass(PassRegistry&);
210210 void initializePostDominatorTreePass(PassRegistry&);
211211 void initializePostRASchedulerPass(PassRegistry&);
212 void initializePostMachineSchedulerPass(PassRegistry&);
212213 void initializePreVerifierPass(PassRegistry&);
213214 void initializePrintFunctionPassPass(PassRegistry&);
214215 void initializePrintModulePassPass(PassRegistry&);
5050 initializeOptimizePHIsPass(Registry);
5151 initializePHIEliminationPass(Registry);
5252 initializePeepholeOptimizerPass(Registry);
53 initializePostMachineSchedulerPass(Registry);
5354 initializePostRASchedulerPass(Registry);
5455 initializeProcessImplicitDefsPass(Registry);
5556 initializePEIPass(Registry);
115115 protected:
116116 ScheduleDAGInstrs *createMachineScheduler();
117117 };
118
119 /// PostMachineScheduler runs after shortly before code emission.
120 class PostMachineScheduler : public MachineSchedulerBase {
121 public:
122 PostMachineScheduler();
123
124 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
125
126 virtual bool runOnMachineFunction(MachineFunction&);
127
128 static char ID; // Class identification, replacement for typeinfo
129
130 protected:
131 ScheduleDAGInstrs *createPostMachineScheduler();
132 };
118133 } // namespace
119134
120135 char MachineScheduler::ID = 0;
147162 MachineFunctionPass::getAnalysisUsage(AU);
148163 }
149164
165 char PostMachineScheduler::ID = 0;
166
167 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
168
169 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
170 "PostRA Machine Instruction Scheduler", false, false);
171
172 PostMachineScheduler::PostMachineScheduler()
173 : MachineSchedulerBase(ID) {
174 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
175 }
176
177 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
178 AU.setPreservesCFG();
179 AU.addRequiredID(MachineDominatorsID);
180 AU.addRequired();
181 AU.addRequired();
182 MachineFunctionPass::getAnalysisUsage(AU);
183 }
184
150185 MachinePassRegistry MachineSchedRegistry::Registry;
151186
152187 /// A dummy default scheduler factory indicates whether the scheduler
229264
230265 // Default to GenericScheduler.
231266 return createGenericSched(this);
267 }
268
269 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
270 /// the caller. We don't have a command line option to override the postRA
271 /// scheduler. The Target must configure it.
272 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
273 // Get the postRA scheduler set by the target for this function.
274 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
275 if (Scheduler)
276 return Scheduler;
277
278 // Default to GenericScheduler.
279 // return createRawGenericSched(this);
280 return NULL;
232281 }
233282
234283 /// Top-level MachineScheduler pass driver.
273322 DEBUG(LIS->dump());
274323 if (VerifyScheduling)
275324 MF->verify(this, "After machine scheduling.");
325 return true;
326 }
327
328 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
329 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
330
331 // Initialize the context of the pass.
332 MF = &mf;
333 PassConfig = &getAnalysis();
334
335 if (VerifyScheduling)
336 MF->verify(this, "Before post machine scheduling.");
337
338 // Instantiate the selected scheduler for this target, function, and
339 // optimization level.
340 OwningPtr Scheduler(createPostMachineScheduler());
341 scheduleRegions(*Scheduler);
342
343 if (VerifyScheduling)
344 MF->verify(this, "After post machine scheduling.");
276345 return true;
277346 }
278347
8787 cl::desc("Print machine instrs"),
8888 cl::value_desc("pass-name"), cl::init("option-unspecified"));
8989
90 // Temporary option to allow experimenting with MachineScheduler as a post-RA
91 // scheduler. Targets can "properly" enable this with
92 // substitutePass(&PostRASchedulerID, &MachineSchedulerID); Ideally it wouldn't
93 // be part of the standard pass pipeline, and the target would just add a PostRA
94 // scheduling pass wherever it wants.
95 static cl::opt MISchedPostRA("misched-postra", cl::Hidden,
96 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
97
9098 // Experimental option to run live interval analysis early.
9199 static cl::opt EarlyLiveIntervals("early-live-intervals", cl::Hidden,
92100 cl::desc("Run live interval analysis earlier in the pipeline"));
524532
525533 // Second pass scheduler.
526534 if (getOptLevel() != CodeGenOpt::None) {
527 addPass(&PostRASchedulerID);
535 if (MISchedPostRA)
536 addPass(&PostMachineSchedulerID);
537 else
538 addPass(&PostRASchedulerID);
528539 printAndVerify("After PostRAScheduler");
529540 }
530541