llvm.org GIT mirror llvm / c50f986
AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperand I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210427 91177308-0d34-0410-b5e6-96231b3b80d8 David Blaikie 5 years ago
13 changed file(s) with 1009 addition(s) and 1146 deletion(s). Raw diff Collapse all Expand all
1313 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
1414 #include "llvm/MC/MCTargetOptions.h"
1515
16 #include
17
1618 namespace llvm {
1719 class AsmToken;
1820 class MCInst;
2123 class SMLoc;
2224 class StringRef;
2325 template class SmallVectorImpl;
26
27 typedef SmallVectorImpl> OperandVector;
2428
2529 enum AsmRewriteKind {
2630 AOK_Delete = 0, // Rewrite should be ignored.
130134 /// ownership of them to the caller.
131135 /// \return True on failure.
132136 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
133 SMLoc NameLoc,
134 SmallVectorImpl &Operands) = 0;
137 SMLoc NameLoc, OperandVector &Operands) = 0;
135138
136139 /// ParseDirective - Parse a target specific assembler directive
137140 ///
155158 ///
156159 /// On failure, the target parser is responsible for emitting a diagnostic
157160 /// explaining the match failure.
158 virtual bool
159 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
160 SmallVectorImpl &Operands,
161 MCStreamer &Out, unsigned &ErrorInfo,
162 bool MatchingInlineAsm) = 0;
161 virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
162 OperandVector &Operands, MCStreamer &Out,
163 unsigned &ErrorInfo,
164 bool MatchingInlineAsm) = 0;
163165
164166 /// Allow a target to add special case operand matching for things that
165167 /// tblgen doesn't/can't handle effectively. For example, literal
166168 /// immediates on ARM. TableGen expects a token operand, but the parser
167169 /// will recognize them as immediates.
168 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
170 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
169171 unsigned Kind) {
170172 return Match_InvalidOperand;
171173 }
177179 }
178180
179181 virtual void convertToMapAndConstraints(unsigned Kind,
180 const SmallVectorImpl &Operands) = 0;
182 const OperandVector &Operands) = 0;
181183
182184 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
183185 MCSymbolRefExpr::VariantKind,
101101
102102 struct ParseStatementInfo {
103103 /// \brief The parsed operands from the last parsed statement.
104 SmallVector<MCParsedAsmOperand*, 8> ParsedOperands;
104 SmallVector<std::unique_ptr, 8> ParsedOperands;
105105
106106 /// \brief The opcode from the last parsed instruction.
107107 unsigned Opcode;
114114 ParseStatementInfo() : Opcode(~0U), ParseError(false), AsmRewrites(nullptr) {}
115115 ParseStatementInfo(SmallVectorImpl *rewrites)
116116 : Opcode(~0), ParseError(false), AsmRewrites(rewrites) {}
117
118 ~ParseStatementInfo() {
119 // Free any parsed operands.
120 for (unsigned i = 0, e = ParsedOperands.size(); i != e; ++i)
121 delete ParsedOperands[i];
122 ParsedOperands.clear();
123 }
124117 };
125118
126119 /// \brief The concrete assembly parser instance.
44644457
44654458 // Build the list of clobbers, outputs and inputs.
44664459 for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
4467 MCParsedAsmOperand *Operand = Info.ParsedOperands[i];
4460 MCParsedAsmOperand &Operand = *Info.ParsedOperands[i];
44684461
44694462 // Immediate.
4470 if (Operand->isImm())
4463 if (Operand.isImm())
44714464 continue;
44724465
44734466 // Register operand.
4474 if (Operand->isReg() && !Operand->needAddressOf()) {
4467 if (Operand.isReg() && !Operand.needAddressOf()) {
44754468 unsigned NumDefs = Desc.getNumDefs();
44764469 // Clobber.
4477 if (NumDefs && Operand->getMCOperandNum() < NumDefs)
4478 ClobberRegs.push_back(Operand->getReg());
4470 if (NumDefs && Operand.getMCOperandNum() < NumDefs)
4471 ClobberRegs.push_back(Operand.getReg());
44794472 continue;
44804473 }
44814474
44824475 // Expr/Input or Output.
4483 StringRef SymName = Operand->getSymName();
4476 StringRef SymName = Operand.getSymName();
44844477 if (SymName.empty())
44854478 continue;
44864479
4487 void *OpDecl = Operand->getOpDecl();
4480 void *OpDecl = Operand.getOpDecl();
44884481 if (!OpDecl)
44894482 continue;
44904483
44934486 if (isOutput) {
44944487 ++InputIdx;
44954488 OutputDecls.push_back(OpDecl);
4496 OutputDeclsAddressOf.push_back(Operand->needAddressOf());
4497 OutputConstraints.push_back('=' + Operand->getConstraint().str());
4489 OutputDeclsAddressOf.push_back(Operand.needAddressOf());
4490 OutputConstraints.push_back('=' + Operand.getConstraint().str());
44984491 AsmStrRewrites.push_back(AsmRewrite(AOK_Output, Start, SymName.size()));
44994492 } else {
45004493 InputDecls.push_back(OpDecl);
4501 InputDeclsAddressOf.push_back(Operand->needAddressOf());
4502 InputConstraints.push_back(Operand->getConstraint().str());
4494 InputDeclsAddressOf.push_back(Operand.needAddressOf());
4495 InputConstraints.push_back(Operand.getConstraint().str());
45034496 AsmStrRewrites.push_back(AsmRewrite(AOK_Input, Start, SymName.size()));
45044497 }
45054498 }
3737 class AArch64Operand;
3838
3939 class AArch64AsmParser : public MCTargetAsmParser {
40 public:
41 typedef SmallVectorImpl OperandVector;
42
4340 private:
4441 StringRef Mnemonic; ///< Instruction mnemonic.
4542 MCSubtargetInfo &STI;
116113 SMLoc NameLoc, OperandVector &Operands) override;
117114 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
118115 bool ParseDirective(AsmToken DirectiveID) override;
119 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
116 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
120117 unsigned Kind) override;
121118
122119 static bool classifySymbolRef(const MCExpr *Expr,
239236 // the add<>Operands() calls.
240237 MCContext &Ctx;
241238
239 public:
242240 AArch64Operand(KindTy K, MCContext &_Ctx)
243241 : MCParsedAsmOperand(), Kind(K), Ctx(_Ctx) {}
244242
245 public:
246243 AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand(), Ctx(o.Ctx) {
247244 Kind = o.Kind;
248245 StartLoc = o.StartLoc;
15221519
15231520 void print(raw_ostream &OS) const override;
15241521
1525 static AArch64Operand *CreateToken(StringRef Str, bool IsSuffix, SMLoc S,
1526 MCContext &Ctx) {
1527 AArch64Operand *Op = new AArch64Operand(k_Token, Ctx);
1522 static std::unique_ptr
1523 CreateToken(StringRef Str, bool IsSuffix, SMLoc S, MCContext &Ctx) {
1524 auto Op = make_unique(k_Token, Ctx);
15281525 Op->Tok.Data = Str.data();
15291526 Op->Tok.Length = Str.size();
15301527 Op->Tok.IsSuffix = IsSuffix;
15331530 return Op;
15341531 }
15351532
1536 static AArch64Operand *CreateReg(unsigned RegNum, bool isVector, SMLoc S,
1537 SMLoc E, MCContext &Ctx) {
1538 AArch64Operand *Op = new AArch64Operand(k_Register, Ctx);
1533 static std::unique_ptr
1534 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) {
1535 auto Op = make_unique(k_Register, Ctx);
15391536 Op->Reg.RegNum = RegNum;
15401537 Op->Reg.isVector = isVector;
15411538 Op->StartLoc = S;
15431540 return Op;
15441541 }
15451542
1546 static AArch64Operand *CreateVectorList(unsigned RegNum, unsigned Count,
1547 unsigned NumElements, char ElementKind,
1548 SMLoc S, SMLoc E, MCContext &Ctx) {
1549 AArch64Operand *Op = new AArch64Operand(k_VectorList, Ctx);
1543 static std::unique_ptr
1544 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements,
1545 char ElementKind, SMLoc S, SMLoc E, MCContext &Ctx) {
1546 auto Op = make_unique(k_VectorList, Ctx);
15501547 Op->VectorList.RegNum = RegNum;
15511548 Op->VectorList.Count = Count;
15521549 Op->VectorList.NumElements = NumElements;
15561553 return Op;
15571554 }
15581555
1559 static AArch64Operand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1560 MCContext &Ctx) {
1561 AArch64Operand *Op = new AArch64Operand(k_VectorIndex, Ctx);
1556 static std::unique_ptr
1557 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
1558 auto Op = make_unique(k_VectorIndex, Ctx);
15621559 Op->VectorIndex.Val = Idx;
15631560 Op->StartLoc = S;
15641561 Op->EndLoc = E;
15651562 return Op;
15661563 }
15671564
1568 static AArch64Operand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
1569 MCContext &Ctx) {
1570 AArch64Operand *Op = new AArch64Operand(k_Immediate, Ctx);
1565 static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S,
1566 SMLoc E, MCContext &Ctx) {
1567 auto Op = make_unique(k_Immediate, Ctx);
15711568 Op->Imm.Val = Val;
15721569 Op->StartLoc = S;
15731570 Op->EndLoc = E;
15741571 return Op;
15751572 }
15761573
1577 static AArch64Operand *CreateShiftedImm(const MCExpr *Val,
1578 unsigned ShiftAmount, SMLoc S,
1579 SMLoc E, MCContext &Ctx) {
1580 AArch64Operand *Op = new AArch64Operand(k_ShiftedImm, Ctx);
1574 static std::unique_ptr CreateShiftedImm(const MCExpr *Val,
1575 unsigned ShiftAmount,
1576 SMLoc S, SMLoc E,
1577 MCContext &Ctx) {
1578 auto Op = make_unique(k_ShiftedImm, Ctx);
15811579 Op->ShiftedImm .Val = Val;
15821580 Op->ShiftedImm.ShiftAmount = ShiftAmount;
15831581 Op->StartLoc = S;
15851583 return Op;
15861584 }
15871585
1588 static AArch64Operand *CreateCondCode(AArch64CC::CondCode Code, SMLoc S,
1589 SMLoc E, MCContext &Ctx) {
1590 AArch64Operand *Op = new AArch64Operand(k_CondCode, Ctx);
1586 static std::unique_ptr
1587 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) {
1588 auto Op = make_unique(k_CondCode, Ctx);
15911589 Op->CondCode.Code = Code;
15921590 Op->StartLoc = S;
15931591 Op->EndLoc = E;
15941592 return Op;
15951593 }
15961594
1597 static AArch64Operand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1598 AArch64Operand *Op = new AArch64Operand(k_FPImm, Ctx);
1595 static std::unique_ptr CreateFPImm(unsigned Val, SMLoc S,
1596 MCContext &Ctx) {
1597 auto Op = make_unique(k_FPImm, Ctx);
15991598 Op->FPImm.Val = Val;
16001599 Op->StartLoc = S;
16011600 Op->EndLoc = S;
16021601 return Op;
16031602 }
16041603
1605 static AArch64Operand *CreateBarrier(unsigned Val, SMLoc S, MCContext &Ctx) {
1606 AArch64Operand *Op = new AArch64Operand(k_Barrier, Ctx);
1604 static std::unique_ptr CreateBarrier(unsigned Val, SMLoc S,
1605 MCContext &Ctx) {
1606 auto Op = make_unique(k_Barrier, Ctx);
16071607 Op->Barrier.Val = Val;
16081608 Op->StartLoc = S;
16091609 Op->EndLoc = S;
16101610 return Op;
16111611 }
16121612
1613 static AArch64Operand *CreateSysReg(StringRef Str, SMLoc S,
1614 uint64_t FeatureBits, MCContext &Ctx) {
1615 AArch64Operand *Op = new AArch64Operand(k_SysReg, Ctx);
1613 static std::unique_ptr
1614 CreateSysReg(StringRef Str, SMLoc S, uint64_t FeatureBits, MCContext &Ctx) {
1615 auto Op = make_unique(k_SysReg, Ctx);
16161616 Op->SysReg.Data = Str.data();
16171617 Op->SysReg.Length = Str.size();
16181618 Op->SysReg.FeatureBits = FeatureBits;
16211621 return Op;
16221622 }
16231623
1624 static AArch64Operand *CreateSysCR(unsigned Val, SMLoc S, SMLoc E,
1625 MCContext &Ctx) {
1626 AArch64Operand *Op = new AArch64Operand(k_SysCR, Ctx);
1624 static std::unique_ptr CreateSysCR(unsigned Val, SMLoc S,
1625 SMLoc E, MCContext &Ctx) {
1626 auto Op = make_unique(k_SysCR, Ctx);
16271627 Op->SysCRImm.Val = Val;
16281628 Op->StartLoc = S;
16291629 Op->EndLoc = E;
16301630 return Op;
16311631 }
16321632
1633 static AArch64Operand *CreatePrefetch(unsigned Val, SMLoc S, MCContext &Ctx) {
1634 AArch64Operand *Op = new AArch64Operand(k_Prefetch, Ctx);
1633 static std::unique_ptr CreatePrefetch(unsigned Val, SMLoc S,
1634 MCContext &Ctx) {
1635 auto Op = make_unique(k_Prefetch, Ctx);
16351636 Op->Prefetch.Val = Val;
16361637 Op->StartLoc = S;
16371638 Op->EndLoc = S;
16381639 return Op;
16391640 }
16401641
1641 static AArch64Operand *CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp,
1642 unsigned Val, bool HasExplicitAmount,
1643 SMLoc S, SMLoc E, MCContext &Ctx) {
1644 AArch64Operand *Op = new AArch64Operand(k_ShiftExtend, Ctx);
1642 static std::unique_ptr
1643 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,
1644 bool HasExplicitAmount, SMLoc S, SMLoc E, MCContext &Ctx) {
1645 auto Op = make_unique(k_ShiftExtend, Ctx);
16451646 Op->ShiftExtend.Type = ShOp;
16461647 Op->ShiftExtend.Amount = Val;
16471648 Op->ShiftExtend.HasExplicitAmount = HasExplicitAmount;
34553456 unsigned &ErrorInfo,
34563457 bool MatchingInlineAsm) {
34573458 assert(!Operands.empty() && "Unexpect empty operand list!");
3458 AArch64Operand *Op = static_cast(Operands[0]);
3459 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
3460
3461 StringRef Tok = Op->getToken();
3459 AArch64Operand &Op = static_cast(*Operands[0]);
3460 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
3461
3462 StringRef Tok = Op.getToken();
34623463 unsigned NumOperands = Operands.size();
34633464
34643465 if (NumOperands == 4 && Tok == "lsl") {
3465 AArch64Operand *Op2 = static_cast(Operands[2]);
3466 AArch64Operand *Op3 = static_cast(Operands[3]);
3467 if (Op2->isReg() && Op3->isImm()) {
3468 const MCConstantExpr *Op3CE = dyn_cast(Op3->getImm());
3466 AArch64Operand &Op2 = static_cast(*Operands[2]);
3467 AArch64Operand &Op3 = static_cast(*Operands[3]);
3468 if (Op2.isReg() && Op3.isImm()) {
3469 const MCConstantExpr *Op3CE = dyn_cast(Op3.getImm());
34693470 if (Op3CE) {
34703471 uint64_t Op3Val = Op3CE->getValue();
34713472 uint64_t NewOp3Val = 0;
34723473 uint64_t NewOp4Val = 0;
34733474 if (AArch64MCRegisterClasses[AArch64::GPR32allRegClassID].contains(
3474 Op2->getReg())) {
3475 Op2.getReg())) {
34753476 NewOp3Val = (32 - Op3Val) & 0x1f;
34763477 NewOp4Val = 31 - Op3Val;
34773478 } else {
34833484 const MCExpr *NewOp4 = MCConstantExpr::Create(NewOp4Val, getContext());
34843485
34853486 Operands[0] = AArch64Operand::CreateToken(
3486 "ubfm", false, Op->getStartLoc(), getContext());
3487 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3->getStartLoc(),
3488 Op3->getEndLoc(), getContext());
3487 "ubfm", false, Op.getStartLoc(), getContext());
34893488 Operands.push_back(AArch64Operand::CreateImm(
3490 NewOp4, Op3->getStartLoc(), Op3->getEndLoc(), getContext()));
3491 delete Op3;
3492 delete Op;
3489 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext()));
3490 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(),
3491 Op3.getEndLoc(), getContext());
34933492 }
34943493 }
34953494 } else if (NumOperands == 5) {
34963495 // FIXME: Horrible hack to handle the BFI -> BFM, SBFIZ->SBFM, and
34973496 // UBFIZ -> UBFM aliases.
34983497 if (Tok == "bfi" || Tok == "sbfiz" || Tok == "ubfiz") {
3499 AArch64Operand *Op1 = static_cast(Operands[1]);
3500 AArch64Operand *Op3 = static_cast(Operands[3]);
3501 AArch64Operand *Op4 = static_cast(Operands[4]);
3502
3503 if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
3504 const MCConstantExpr *Op3CE = dyn_cast(Op3->getImm());
3505 const MCConstantExpr *Op4CE = dyn_cast(Op4->getImm());
3498 AArch64Operand &Op1 = static_cast(*Operands[1]);
3499 AArch64Operand &Op3 = static_cast(*Operands[3]);
3500 AArch64Operand &Op4 = static_cast(*Operands[4]);
3501
3502 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) {
3503 const MCConstantExpr *Op3CE = dyn_cast(Op3.getImm());
3504 const MCConstantExpr *Op4CE = dyn_cast(Op4.getImm());
35063505
35073506 if (Op3CE && Op4CE) {
35083507 uint64_t Op3Val = Op3CE->getValue();
35103509
35113510 uint64_t RegWidth = 0;
35123511 if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3513 Op1->getReg()))
3512 Op1.getReg()))
35143513 RegWidth = 64;
35153514 else
35163515 RegWidth = 32;
35173516
35183517 if (Op3Val >= RegWidth)
3519 return Error(Op3->getStartLoc(),
3518 return Error(Op3.getStartLoc(),
35203519 "expected integer in range [0, 31]");
35213520 if (Op4Val < 1 || Op4Val > RegWidth)
3522 return Error(Op4->getStartLoc(),
3521 return Error(Op4.getStartLoc(),
35233522 "expected integer in range [1, 32]");
35243523
35253524 uint64_t NewOp3Val = 0;
35263525 if (AArch64MCRegisterClasses[AArch64::GPR32allRegClassID].contains(
3527 Op1->getReg()))
3526 Op1.getReg()))
35283527 NewOp3Val = (32 - Op3Val) & 0x1f;
35293528 else
35303529 NewOp3Val = (64 - Op3Val) & 0x3f;
35323531 uint64_t NewOp4Val = Op4Val - 1;
35333532
35343533 if (NewOp3Val != 0 && NewOp4Val >= NewOp3Val)
3535 return Error(Op4->getStartLoc(),
3534 return Error(Op4.getStartLoc(),
35363535 "requested insert overflows register");
35373536
35383537 const MCExpr *NewOp3 =
35403539 const MCExpr *NewOp4 =
35413540 MCConstantExpr::Create(NewOp4Val, getContext());
35423541 Operands[3] = AArch64Operand::CreateImm(
3543 NewOp3, Op3->getStartLoc(), Op3->getEndLoc(), getContext());
3542 NewOp3, Op3.getStartLoc(), Op3.getEndLoc(), getContext());
35443543 Operands[4] = AArch64Operand::CreateImm(
3545 NewOp4, Op4->getStartLoc(), Op4->getEndLoc(), getContext());
3544 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext());
35463545 if (Tok == "bfi")
35473546 Operands[0] = AArch64Operand::CreateToken(
3548 "bfm", false, Op->getStartLoc(), getContext());
3547 "bfm", false, Op.getStartLoc(), getContext());
35493548 else if (Tok == "sbfiz")
35503549 Operands[0] = AArch64Operand::CreateToken(
3551 "sbfm", false, Op->getStartLoc(), getContext());
3550 "sbfm", false, Op.getStartLoc(), getContext());
35523551 else if (Tok == "ubfiz")
35533552 Operands[0] = AArch64Operand::CreateToken(
3554 "ubfm", false, Op->getStartLoc(), getContext());
3553 "ubfm", false, Op.getStartLoc(), getContext());
35553554 else
35563555 llvm_unreachable("No valid mnemonic for alias?");
3557
3558 delete Op;
3559 delete Op3;
3560 delete Op4;
35613556 }
35623557 }
35633558
35653560 // UBFX -> UBFM aliases.
35663561 } else if (NumOperands == 5 &&
35673562 (Tok == "bfxil" || Tok == "sbfx" || Tok == "ubfx")) {
3568 AArch64Operand *Op1 = static_cast(Operands[1]);
3569 AArch64Operand *Op3 = static_cast(Operands[3]);
3570 AArch64Operand *Op4 = static_cast(Operands[4]);
3571
3572 if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
3573 const MCConstantExpr *Op3CE = dyn_cast(Op3->getImm());
3574 const MCConstantExpr *Op4CE = dyn_cast(Op4->getImm());
3563 AArch64Operand &Op1 = static_cast(*Operands[1]);
3564 AArch64Operand &Op3 = static_cast(*Operands[3]);
3565 AArch64Operand &Op4 = static_cast(*Operands[4]);
3566
3567 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) {
3568 const MCConstantExpr *Op3CE = dyn_cast(Op3.getImm());
3569 const MCConstantExpr *Op4CE = dyn_cast(Op4.getImm());
35753570
35763571 if (Op3CE && Op4CE) {
35773572 uint64_t Op3Val = Op3CE->getValue();
35793574
35803575 uint64_t RegWidth = 0;
35813576 if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3582 Op1->getReg()))
3577 Op1.getReg()))
35833578 RegWidth = 64;
35843579 else
35853580 RegWidth = 32;
35863581
35873582 if (Op3Val >= RegWidth)
3588 return Error(Op3->getStartLoc(),
3583 return Error(Op3.getStartLoc(),
35893584 "expected integer in range [0, 31]");
35903585 if (Op4Val < 1 || Op4Val > RegWidth)
3591 return Error(Op4->getStartLoc(),
3586 return Error(Op4.getStartLoc(),
35923587 "expected integer in range [1, 32]");
35933588
35943589 uint64_t NewOp4Val = Op3Val + Op4Val - 1;
35953590
35963591 if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val)
3597 return Error(Op4->getStartLoc(),
3592 return Error(Op4.getStartLoc(),
35983593 "requested extract overflows register");
35993594
36003595 const MCExpr *NewOp4 =
36013596 MCConstantExpr::Create(NewOp4Val, getContext());
36023597 Operands[4] = AArch64Operand::CreateImm(
3603 NewOp4, Op4->getStartLoc(), Op4->getEndLoc(), getContext());
3598 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext());
36043599 if (Tok == "bfxil")
36053600 Operands[0] = AArch64Operand::CreateToken(
3606 "bfm", false, Op->getStartLoc(), getContext());
3601 "bfm", false, Op.getStartLoc(), getContext());
36073602 else if (Tok == "sbfx")
36083603 Operands[0] = AArch64Operand::CreateToken(
3609 "sbfm", false, Op->getStartLoc(), getContext());
3604 "sbfm", false, Op.getStartLoc(), getContext());
36103605 else if (Tok == "ubfx")
36113606 Operands[0] = AArch64Operand::CreateToken(
3612 "ubfm", false, Op->getStartLoc(), getContext());
3607 "ubfm", false, Op.getStartLoc(), getContext());
36133608 else
36143609 llvm_unreachable("No valid mnemonic for alias?");
3615
3616 delete Op;
3617 delete Op4;
36183610 }
36193611 }
36203612 }
36253617 if (NumOperands == 3 && (Tok == "sxtw" || Tok == "uxtw")) {
36263618 // The source register can be Wn here, but the matcher expects a
36273619 // GPR64. Twiddle it here if necessary.
3628 AArch64Operand *Op = static_cast(Operands[2]);
3629 if (Op->isReg()) {
3630 unsigned Reg = getXRegFromWReg(Op->getReg());
3631 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op->getStartLoc(),
3632 Op->getEndLoc(), getContext());
3633 delete Op;
3620 AArch64Operand &Op = static_cast(*Operands[2]);
3621 if (Op.isReg()) {
3622 unsigned Reg = getXRegFromWReg(Op.getReg());
3623 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3624 Op.getEndLoc(), getContext());
36343625 }
36353626 }
36363627 // FIXME: Likewise for sxt[bh] with a Xd dst operand
36373628 else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
3638 AArch64Operand *Op = static_cast(Operands[1]);
3639 if (Op->isReg() &&
3629 AArch64Operand &Op = static_cast(*Operands[1]);
3630 if (Op.isReg() &&
36403631 AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3641 Op->getReg())) {
3632 Op.getReg())) {
36423633 // The source register can be Wn here, but the matcher expects a
36433634 // GPR64. Twiddle it here if necessary.
3644 AArch64Operand *Op = static_cast(Operands[2]);
3645 if (Op->isReg()) {
3646 unsigned Reg = getXRegFromWReg(Op->getReg());
3647 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op->getStartLoc(),
3648 Op->getEndLoc(), getContext());
3649 delete Op;
3635 AArch64Operand &Op = static_cast(*Operands[2]);
3636 if (Op.isReg()) {
3637 unsigned Reg = getXRegFromWReg(Op.getReg());
3638 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3639 Op.getEndLoc(), getContext());
36503640 }
36513641 }
36523642 }
36533643 // FIXME: Likewise for uxt[bh] with a Xd dst operand
36543644 else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
3655 AArch64Operand *Op = static_cast(Operands[1]);
3656 if (Op->isReg() &&
3645 AArch64Operand &Op = static_cast(*Operands[1]);
3646 if (Op.isReg() &&
36573647 AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3658 Op->getReg())) {
3648 Op.getReg())) {
36593649 // The source register can be Wn here, but the matcher expects a
36603650 // GPR32. Twiddle it here if necessary.
3661 AArch64Operand *Op = static_cast(Operands[1]);
3662 if (Op->isReg()) {
3663 unsigned Reg = getWRegFromXReg(Op->getReg());
3664 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op->getStartLoc(),
3665 Op->getEndLoc(), getContext());
3666 delete Op;
3651 AArch64Operand &Op = static_cast(*Operands[1]);
3652 if (Op.isReg()) {
3653 unsigned Reg = getWRegFromXReg(Op.getReg());
3654 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3655 Op.getEndLoc(), getContext());
36673656 }
36683657 }
36693658 }
36703659
36713660 // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
36723661 if (NumOperands == 3 && Tok == "fmov") {
3673 AArch64Operand *RegOp = static_cast(Operands[1]);
3674 AArch64Operand *ImmOp = static_cast(Operands[2]);
3675 if (RegOp->isReg() && ImmOp->isFPImm() &&
3676 ImmOp->getFPImm() == (unsigned)-1) {
3662 AArch64Operand &RegOp = static_cast(*Operands[1]);
3663 AArch64Operand &ImmOp = static_cast(*Operands[2]);
3664 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) {
36773665 unsigned zreg =
36783666 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].contains(
3679 RegOp->getReg())
3667 RegOp.getReg())
36803668 ? AArch64::WZR
36813669 : AArch64::XZR;
3682 Operands[2] = AArch64Operand::CreateReg(zreg, false, Op->getStartLoc(),
3683 Op->getEndLoc(), getContext());
3684 delete ImmOp;
3670 Operands[2] = AArch64Operand::CreateReg(zreg, false, Op.getStartLoc(),
3671 Op.getEndLoc(), getContext());
36853672 }
36863673 }
36873674
37343721 if (ErrorInfo >= Operands.size())
37353722 return Error(IDLoc, "too few operands for instruction");
37363723
3737 ErrorLoc = ((AArch64Operand *)Operands[ErrorInfo])->getStartLoc();
3724 ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
37383725 if (ErrorLoc == SMLoc())
37393726 ErrorLoc = IDLoc;
37403727 }
37413728 // If the match failed on a suffix token operand, tweak the diagnostic
37423729 // accordingly.
3743 if (((AArch64Operand *)Operands[ErrorInfo])->isToken() &&
3744 ((AArch64Operand *)Operands[ErrorInfo])->isTokenSuffix())
3730 if (((AArch64Operand &)*Operands[ErrorInfo]).isToken() &&
3731 ((AArch64Operand &)*Operands[ErrorInfo]).isTokenSuffix())
37453732 MatchResult = Match_InvalidSuffix;
37463733
37473734 return showMatchError(ErrorLoc, MatchResult);
37973784 return Error(IDLoc, "too few operands for instruction");
37983785 // Any time we get here, there's nothing fancy to do. Just get the
37993786 // operand SMLoc and display the diagnostic.
3800 SMLoc ErrorLoc = ((AArch64Operand *)Operands[ErrorInfo])->getStartLoc();
3787 SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
38013788 if (ErrorLoc == SMLoc())
38023789 ErrorLoc = IDLoc;
38033790 return showMatchError(ErrorLoc, MatchResult);
39873974
39883975 // Define this matcher function after the auto-generated include so we
39893976 // have the match class enum definitions.
3990 unsigned AArch64AsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
3977 unsigned AArch64AsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
39913978 unsigned Kind) {
3992 AArch64Operand *Op = static_cast>(AsmOp);
3979 AArch64Operand &Op = static_cast>(AsmOp);
39933980 // If the kind is a token for a literal immediate, check if our asm
39943981 // operand matches. This is for InstAliases which have a fixed-value
39953982 // immediate in the syntax.
40374024 ExpectedVal = 8;
40384025 break;
40394026 }
4040 if (!Op->isImm())
4027 if (!Op.isImm())
40414028 return Match_InvalidOperand;
4042 const MCConstantExpr *CE = dyn_cast(Op->getImm());
4029 const MCConstantExpr *CE = dyn_cast(Op.getImm());
40434030 if (!CE)
40444031 return Match_InvalidOperand;
40454032 if (CE->getValue() == ExpectedVal)
189189 }
190190
191191 int tryParseRegister();
192 bool tryParseRegisterWithWriteBack(SmallVectorImpl &);
193 int tryParseShiftRegister(SmallVectorImpl &);
194 bool parseRegisterList(SmallVectorImpl &);
195 bool parseMemory(SmallVectorImpl &);
196 bool parseOperand(SmallVectorImpl &, StringRef Mnemonic);
192 bool tryParseRegisterWithWriteBack(OperandVector &);
193 int tryParseShiftRegister(OperandVector &);
194 bool parseRegisterList(OperandVector &);
195 bool parseMemory(OperandVector &);
196 bool parseOperand(OperandVector &, StringRef Mnemonic);
197197 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
198198 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
199199 unsigned &ShiftAmount);
281281
282282 /// }
283283
284 OperandMatchResultTy parseITCondCode(SmallVectorImpl&);
285 OperandMatchResultTy parseCoprocNumOperand(
286 SmallVectorImpl&);
287 OperandMatchResultTy parseCoprocRegOperand(
288 SmallVectorImpl&);
289 OperandMatchResultTy parseCoprocOptionOperand(
290 SmallVectorImpl&);
291 OperandMatchResultTy parseMemBarrierOptOperand(
292 SmallVectorImpl&);
293 OperandMatchResultTy parseInstSyncBarrierOptOperand(
294 SmallVectorImpl&);
295 OperandMatchResultTy parseProcIFlagsOperand(
296 SmallVectorImpl&);
297 OperandMatchResultTy parseMSRMaskOperand(
298 SmallVectorImpl&);
299 OperandMatchResultTy parsePKHImm(SmallVectorImpl &O,
300 StringRef Op, int Low, int High);
301 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl &O) {
284 OperandMatchResultTy parseITCondCode(OperandVector &);
285 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
286 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
287 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
288 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
289 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
290 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
291 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
292 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
293 int High);
294 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
302295 return parsePKHImm(O, "lsl", 0, 31);
303296 }
304 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl &O) {
297 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
305298 return parsePKHImm(O, "asr", 1, 32);
306299 }
307 OperandMatchResultTy parseSetEndImm(SmallVectorImpl&);
308 OperandMatchResultTy parseShifterImm(SmallVectorImpl&);
309 OperandMatchResultTy parseRotImm(SmallVectorImpl&);
310 OperandMatchResultTy parseBitfield(SmallVectorImpl&);
311 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl&);
312 OperandMatchResultTy parseAM3Offset(SmallVectorImpl&);
313 OperandMatchResultTy parseFPImm(SmallVectorImpl&);
314 OperandMatchResultTy parseVectorList(SmallVectorImpl&);
300 OperandMatchResultTy parseSetEndImm(OperandVector &);
301 OperandMatchResultTy parseShifterImm(OperandVector &);
302 OperandMatchResultTy parseRotImm(OperandVector &);
303 OperandMatchResultTy parseBitfield(OperandVector &);
304 OperandMatchResultTy parsePostIdxReg(OperandVector &);
305 OperandMatchResultTy parseAM3Offset(OperandVector &);
306 OperandMatchResultTy parseFPImm(OperandVector &);
307 OperandMatchResultTy parseVectorList(OperandVector &);
315308 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
316309 SMLoc &EndLoc);
317310
318311 // Asm Match Converter Methods
319 void cvtThumbMultiply(MCInst &Inst,
320 const SmallVectorImpl &);
321 void cvtThumbBranches(MCInst &Inst,
322 const SmallVectorImpl &);
323
324 bool validateInstruction(MCInst &Inst,
325 const SmallVectorImpl &Ops);
326 bool processInstruction(MCInst &Inst,
327 const SmallVectorImpl &Ops);
328 bool shouldOmitCCOutOperand(StringRef Mnemonic,
329 SmallVectorImpl &Operands);
330 bool shouldOmitPredicateOperand(StringRef Mnemonic,
331 SmallVectorImpl &Operands);
312 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
313 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
314
315 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
316 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
317 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
318 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
319
332320 public:
333321 enum ARMMatchResultTy {
334322 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
360348
361349 // Implementation of the MCTargetAsmParser interface:
362350 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
363 bool
364 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
365 SMLoc NameLoc,
366 SmallVectorImpl &Operands) override;
351 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
352 SMLoc NameLoc, OperandVector &Operands) override;
367353 bool ParseDirective(AsmToken DirectiveID) override;
368354
369 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
355 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
370356 unsigned Kind) override;
371357 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
372358
373359 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
374 SmallVectorImpl &Operands,
375 MCStreamer &Out, unsigned &ErrorInfo,
360 OperandVector &Operands, MCStreamer &Out,
361 unsigned &ErrorInfo,
376362 bool MatchingInlineAsm) override;
377363 void onLabelParsed(MCSymbol *Symbol) override;
378364 };
544530 struct BitfieldOp Bitfield;
545531 };
546532
533 public:
547534 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
548 public:
549535 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
550536 Kind = o.Kind;
551537 StartLoc = o.StartLoc;
24802466
24812467 void print(raw_ostream &OS) const override;
24822468
2483 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2484 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2469 static std::unique_ptr CreateITMask(unsigned Mask, SMLoc S) {
2470 auto Op = make_unique(k_ITCondMask);
24852471 Op->ITMask.Mask = Mask;
24862472 Op->StartLoc = S;
24872473 Op->EndLoc = S;
24882474 return Op;
24892475 }
24902476
2491 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2492 ARMOperand *Op = new ARMOperand(k_CondCode);
2477 static std::unique_ptr CreateCondCode(ARMCC::CondCodes CC,
2478 SMLoc S) {
2479 auto Op = make_unique(k_CondCode);
24932480 Op->CC.Val = CC;
24942481 Op->StartLoc = S;
24952482 Op->EndLoc = S;
24962483 return Op;
24972484 }
24982485
2499 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2500 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2486 static std::unique_ptr CreateCoprocNum(unsigned CopVal, SMLoc S) {
2487 auto Op = make_unique(k_CoprocNum);
25012488 Op->Cop.Val = CopVal;
25022489 Op->StartLoc = S;
25032490 Op->EndLoc = S;
25042491 return Op;
25052492 }
25062493
2507 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2508 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2494 static std::unique_ptr CreateCoprocReg(unsigned CopVal, SMLoc S) {
2495 auto Op = make_unique(k_CoprocReg);
25092496 Op->Cop.Val = CopVal;
25102497 Op->StartLoc = S;
25112498 Op->EndLoc = S;
25122499 return Op;
25132500 }
25142501
2515 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2516 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2502 static std::unique_ptr CreateCoprocOption(unsigned Val, SMLoc S,
2503 SMLoc E) {
2504 auto Op = make_unique(k_CoprocOption);
25172505 Op->Cop.Val = Val;
25182506 Op->StartLoc = S;
25192507 Op->EndLoc = E;
25202508 return Op;
25212509 }
25222510
2523 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2524 ARMOperand *Op = new ARMOperand(k_CCOut);
2511 static std::unique_ptr CreateCCOut(unsigned RegNum, SMLoc S) {
2512 auto Op = make_unique(k_CCOut);
25252513 Op->Reg.RegNum = RegNum;
25262514 Op->StartLoc = S;
25272515 Op->EndLoc = S;
25282516 return Op;
25292517 }
25302518
2531 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2532 ARMOperand *Op = new ARMOperand(k_Token);
2519 static std::unique_ptr CreateToken(StringRef Str, SMLoc S) {
2520 auto Op = make_unique(k_Token);
25332521 Op->Tok.Data = Str.data();
25342522 Op->Tok.Length = Str.size();
25352523 Op->StartLoc = S;
25372525 return Op;
25382526 }
25392527
2540 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2541 ARMOperand *Op = new ARMOperand(k_Register);
2528 static std::unique_ptr CreateReg(unsigned RegNum, SMLoc S,
2529 SMLoc E) {
2530 auto Op = make_unique(k_Register);
25422531 Op->Reg.RegNum = RegNum;
25432532 Op->StartLoc = S;
25442533 Op->EndLoc = E;
25452534 return Op;
25462535 }
25472536
2548 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2549 unsigned SrcReg,
2550 unsigned ShiftReg,
2551 unsigned ShiftImm,
2552 SMLoc S, SMLoc E) {
2553 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2537 static std::unique_ptr
2538 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2539 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2540 SMLoc E) {
2541 auto Op = make_unique(k_ShiftedRegister);
25542542 Op->RegShiftedReg.ShiftTy = ShTy;
25552543 Op->RegShiftedReg.SrcReg = SrcReg;
25562544 Op->RegShiftedReg.ShiftReg = ShiftReg;
25602548 return Op;
25612549 }
25622550
2563 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2564 unsigned SrcReg,
2565 unsigned ShiftImm,
2566 SMLoc S, SMLoc E) {
2567 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2551 static std::unique_ptr
2552 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2553 unsigned ShiftImm, SMLoc S, SMLoc E) {
2554 auto Op = make_unique(k_ShiftedImmediate);
25682555 Op->RegShiftedImm.ShiftTy = ShTy;
25692556 Op->RegShiftedImm.SrcReg = SrcReg;
25702557 Op->RegShiftedImm.ShiftImm = ShiftImm;
25732560 return Op;
25742561 }
25752562
2576 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2577 SMLoc S, SMLoc E) {
2578 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2563 static std::unique_ptr CreateShifterImm(bool isASR, unsigned Imm,
2564 SMLoc S, SMLoc E) {
2565 auto Op = make_unique(k_ShifterImmediate);
25792566 Op->ShifterImm.isASR = isASR;
25802567 Op->ShifterImm.Imm = Imm;
25812568 Op->StartLoc = S;
25832570 return Op;
25842571 }
25852572
2586 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2587 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2573 static std::unique_ptr CreateRotImm(unsigned Imm, SMLoc S,
2574 SMLoc E) {
2575 auto Op = make_unique(k_RotateImmediate);
25882576 Op->RotImm.Imm = Imm;
25892577 Op->StartLoc = S;
25902578 Op->EndLoc = E;
25912579 return Op;
25922580 }
25932581
2594 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2595 SMLoc S, SMLoc E) {
2596 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2582 static std::unique_ptr
2583 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2584 auto Op = make_unique(k_BitfieldDescriptor);
25972585 Op->Bitfield.LSB = LSB;
25982586 Op->Bitfield.Width = Width;
25992587 Op->StartLoc = S;
26012589 return Op;
26022590 }
26032591
2604 static ARMOperand *
2605 CreateRegList(SmallVectorImpl > &Regs,
2592 static std::unique_ptr
2593 CreateRegList(SmallVectorImpl> &Regs,
26062594 SMLoc StartLoc, SMLoc EndLoc) {
26072595 assert (Regs.size() > 0 && "RegList contains no registers?");
26082596 KindTy Kind = k_RegisterList;
26162604 // Sort based on the register encoding values.
26172605 array_pod_sort(Regs.begin(), Regs.end());
26182606
2619 ARMOperand *Op = new ARMOperand(Kind);
2607 auto Op = make_unique(Kind);
26202608 for (SmallVectorImpl >::const_iterator
26212609 I = Regs.begin(), E = Regs.end(); I != E; ++I)
26222610 Op->Registers.push_back(I->second);
26252613 return Op;
26262614 }
26272615
2628 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2629 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2630 ARMOperand *Op = new ARMOperand(k_VectorList);
2616 static std::unique_ptr CreateVectorList(unsigned RegNum,
2617 unsigned Count,
2618 bool isDoubleSpaced,
2619 SMLoc S, SMLoc E) {
2620 auto Op = make_unique(k_VectorList);
26312621 Op->VectorList.RegNum = RegNum;
26322622 Op->VectorList.Count = Count;
26332623 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
26362626 return Op;
26372627 }
26382628
2639 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2640 bool isDoubleSpaced,
2641 SMLoc S, SMLoc E) {
2642 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2629 static std::unique_ptr
2630 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2631 SMLoc S, SMLoc E) {
2632 auto Op = make_unique(k_VectorListAllLanes);
26432633 Op->VectorList.RegNum = RegNum;
26442634 Op->VectorList.Count = Count;
26452635 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
26482638 return Op;
26492639 }
26502640
2651 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2652 unsigned Index,
2653 bool isDoubleSpaced,
2654 SMLoc S, SMLoc E) {
2655 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2641 static std::unique_ptr
2642 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2643 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2644 auto Op = make_unique(k_VectorListIndexed);
26562645 Op->VectorList.RegNum = RegNum;
26572646 Op->VectorList.Count = Count;
26582647 Op->VectorList.LaneIndex = Index;
26622651 return Op;
26632652 }
26642653
2665 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2666 MCContext &Ctx) {
2667 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2654 static std::unique_ptr
2655 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2656 auto Op = make_unique(k_VectorIndex);
26682657 Op->VectorIndex.Val = Idx;
26692658 Op->StartLoc = S;
26702659 Op->EndLoc = E;
26712660 return Op;
26722661 }
26732662
2674 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2675 ARMOperand *Op = new ARMOperand(k_Immediate);
2663 static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S,
2664 SMLoc E) {
2665 auto Op = make_unique(k_Immediate);
26762666 Op->Imm.Val = Val;
26772667 Op->StartLoc = S;
26782668 Op->EndLoc = E;
26792669 return Op;
26802670 }
26812671
2682 static ARMOperand *CreateMem(unsigned BaseRegNum,
2683 const MCConstantExpr *OffsetImm,
2684 unsigned OffsetRegNum,
2685 ARM_AM::ShiftOpc ShiftType,
2686 unsigned ShiftImm,
2687 unsigned Alignment,
2688 bool isNegative,
2689 SMLoc S, SMLoc E,
2690 SMLoc AlignmentLoc = SMLoc()) {
2691 ARMOperand *Op = new ARMOperand(k_Memory);
2672 static std::unique_ptr
2673 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2674 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2675 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2676 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2677 auto Op = make_unique(k_Memory);
26922678 Op->Memory.BaseRegNum = BaseRegNum;
26932679 Op->Memory.OffsetImm = OffsetImm;
26942680 Op->Memory.OffsetRegNum = OffsetRegNum;
27022688 return Op;
27032689 }
27042690
2705 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2706 ARM_AM::ShiftOpc ShiftTy,
2707 unsigned ShiftImm,
2708 SMLoc S, SMLoc E) {
2709 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2691 static std::unique_ptr
2692 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2693 unsigned ShiftImm, SMLoc S, SMLoc E) {
2694 auto Op = make_unique(k_PostIndexRegister);
27102695 Op->PostIdxReg.RegNum = RegNum;
27112696 Op->PostIdxReg.isAdd = isAdd;
27122697 Op->PostIdxReg.ShiftTy = ShiftTy;
27162701 return Op;
27172702 }
27182703
2719 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2720 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2704 static std::unique_ptr CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2705 SMLoc S) {
2706 auto Op = make_unique(k_MemBarrierOpt);
27212707 Op->MBOpt.Val = Opt;
27222708 Op->StartLoc = S;
27232709 Op->EndLoc = S;
27242710 return Op;
27252711 }
27262712
2727 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2728 SMLoc S) {
2729 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2713 static std::unique_ptr
2714 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2715 auto Op = make_unique(k_InstSyncBarrierOpt);
27302716 Op->ISBOpt.Val = Opt;
27312717 Op->StartLoc = S;
27322718 Op->EndLoc = S;
27332719 return Op;
27342720 }
27352721
2736 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2737 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2722 static std::unique_ptr CreateProcIFlags(ARM_PROC::IFlags IFlags,
2723 SMLoc S) {
2724 auto Op = make_unique(k_ProcIFlags);
27382725 Op->IFlags.Val = IFlags;
27392726 Op->StartLoc = S;
27402727 Op->EndLoc = S;
27412728 return Op;
27422729 }
27432730
2744 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2745 ARMOperand *Op = new ARMOperand(k_MSRMask);
2731 static std::unique_ptr CreateMSRMask(unsigned MMask, SMLoc S) {
2732 auto Op = make_unique(k_MSRMask);
27462733 Op->MMask.Val = MMask;
27472734 Op->StartLoc = S;
27482735 Op->EndLoc = S;
29462933 // occurs, return -1. An irrecoverable error is one where tokens have been
29472934 // consumed in the process of trying to parse the shifter (i.e., when it is
29482935 // indeed a shifter operand, but malformed).
2949 int ARMAsmParser::tryParseShiftRegister(
2950 SmallVectorImpl &Operands) {
2936 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
29512937 SMLoc S = Parser.getTok().getLoc();
29522938 const AsmToken &Tok = Parser.getTok();
29532939 if (Tok.isNot(AsmToken::Identifier))
29712957 // The source register for the shift has already been added to the
29722958 // operand list, so we need to pop it off and combine it into the shifted
29732959 // register operand instead.
2974 std::unique_ptr PrevOp((ARMOperand*)Operands.pop_back_val());
2960 std::unique_ptr PrevOp(
2961 (ARMOperand *)Operands.pop_back_val().release());
29752962 if (!PrevOp->isReg())
29762963 return Error(PrevOp->getStartLoc(), "shift must be of a register");
29772964 int SrcReg = PrevOp->getReg();
30483035 ///
30493036 /// TODO this is likely to change to allow different register types and or to
30503037 /// parse for a specific register type.
3051 bool ARMAsmParser::
3052 tryParseRegisterWithWriteBack(SmallVectorImpl &Operands) {
3038 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
30533039 const AsmToken &RegTok = Parser.getTok();
30543040 int RegNo = tryParseRegister();
30553041 if (RegNo == -1)
31353121 }
31363122
31373123 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3138 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3139 parseITCondCode(SmallVectorImpl &Operands) {
3124 ARMAsmParser::OperandMatchResultTy
3125 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
31403126 SMLoc S = Parser.getTok().getLoc();
31413127 const AsmToken &Tok = Parser.getTok();
31423128 if (!Tok.is(AsmToken::Identifier))
31723158 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
31733159 /// token must be an Identifier when called, and if it is a coprocessor
31743160 /// number, the token is eaten and the operand is added to the operand list.
3175 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3176 parseCoprocNumOperand(SmallVectorImpl &Operands) {
3161 ARMAsmParser::OperandMatchResultTy
3162 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
31773163 SMLoc S = Parser.getTok().getLoc();
31783164 const AsmToken &Tok = Parser.getTok();
31793165 if (Tok.isNot(AsmToken::Identifier))
31913177 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
31923178 /// token must be an Identifier when called, and if it is a coprocessor
31933179 /// number, the token is eaten and the operand is added to the operand list.
3194 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3195 parseCoprocRegOperand(SmallVectorImpl &Operands) {
3180 ARMAsmParser::OperandMatchResultTy
3181 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
31963182 SMLoc S = Parser.getTok().getLoc();
31973183 const AsmToken &Tok = Parser.getTok();
31983184 if (Tok.isNot(AsmToken::Identifier))
32093195
32103196 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
32113197 /// coproc_option : '{' imm0_255 '}'
3212 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3213 parseCoprocOptionOperand(SmallVectorImpl &Operands) {
3198 ARMAsmParser::OperandMatchResultTy
3199 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
32143200 SMLoc S = Parser.getTok().getLoc();
32153201
32163202 // If this isn't a '{', this isn't a coprocessor immediate operand.
32873273 }
32883274
32893275 /// Parse a register list.
3290 bool ARMAsmParser::
3291 parseRegisterList(SmallVectorImpl &Operands) {
3276 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
32923277 assert(Parser.getTok().is(AsmToken::LCurly) &&
32933278 "Token is not a Left Curly Brace");
32943279 SMLoc S = Parser.getTok().getLoc();
34693454 }
34703455
34713456 // parse a vector register list
3472 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3473 parseVectorList(SmallVectorImpl &Operands) {
3457 ARMAsmParser::OperandMatchResultTy
3458 ARMAsmParser::parseVectorList(OperandVector &Operands) {
34743459 VectorLaneTy LaneKind;
34753460 unsigned LaneIndex;
34763461 SMLoc S = Parser.getTok().getLoc();
37203705 }
37213706
37223707 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3723 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3724 parseMemBarrierOptOperand(SmallVectorImpl &Operands) {
3708 ARMAsmParser::OperandMatchResultTy
3709 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
37253710 SMLoc S = Parser.getTok().getLoc();
37263711 const AsmToken &Tok = Parser.getTok();
37273712 unsigned Opt;
37913776 }
37923777
37933778 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3794 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3795 parseInstSyncBarrierOptOperand(SmallVectorImpl &Operands) {
3779 ARMAsmParser::OperandMatchResultTy
3780 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
37963781 SMLoc S = Parser.getTok().getLoc();
37973782 const AsmToken &Tok = Parser.getTok();
37983783 unsigned Opt;
38423827
38433828
38443829 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3845 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3846 parseProcIFlagsOperand(SmallVectorImpl &Operands) {
3830 ARMAsmParser::OperandMatchResultTy
3831 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
38473832 SMLoc S = Parser.getTok().getLoc();
38483833 const AsmToken &Tok = Parser.getTok();
38493834 if (!Tok.is(AsmToken::Identifier))
38763861 }
38773862
38783863 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3879 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3880 parseMSRMaskOperand(SmallVectorImpl &Operands) {
3864 ARMAsmParser::OperandMatchResultTy
3865 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
38813866 SMLoc S = Parser.getTok().getLoc();
38823867 const AsmToken &Tok = Parser.getTok();
38833868 if (!Tok.is(AsmToken::Identifier))
40043989 return MatchOperand_Success;
40053990 }
40063991
4007 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4008 parsePKHImm(SmallVectorImpl &Operands, StringRef Op,
4009 int Low, int High) {
3992 ARMAsmParser::OperandMatchResultTy
3993 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
3994 int High) {
40103995 const AsmToken &Tok = Parser.getTok();
40113996 if (Tok.isNot(AsmToken::Identifier)) {
40123997 Error(Parser.getTok().getLoc(), Op + " operand expected.");
40524037 return MatchOperand_Success;
40534038 }
40544039
4055 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4056 parseSetEndImm(SmallVectorImpl &Operands) {
4040 ARMAsmParser::OperandMatchResultTy
4041 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
40574042 const AsmToken &Tok = Parser.getTok();
40584043 SMLoc S = Tok.getLoc();
40594044 if (Tok.isNot(AsmToken::Identifier)) {
40814066 /// lsl #n 'n' in [0,31]
40824067 /// asr #n 'n' in [1,32]
40834068 /// n == 32 encoded as n == 0.
4084 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4085 parseShifterImm(SmallVectorImpl &Operands) {
4069 ARMAsmParser::OperandMatchResultTy
4070 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
40864071 const AsmToken &Tok = Parser.getTok();
40874072 SMLoc S = Tok.getLoc();
40884073 if (Tok.isNot(AsmToken::Identifier)) {
41514136 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
41524137 /// of instructions. Legal values are:
41534138 /// ror #n 'n' in {0, 8, 16, 24}
4154 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4155 parseRotImm(SmallVectorImpl &Operands) {
4139 ARMAsmParser::OperandMatchResultTy
4140 ARMAsmParser::parseRotImm(OperandVector &Operands) {
41564141 const AsmToken &Tok = Parser.getTok();
41574142 SMLoc S = Tok.getLoc();
41584143 if (Tok.isNot(AsmToken::Identifier))
41974182 return MatchOperand_Success;
41984183 }
41994184
4200 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4201 parseBitfield(SmallVectorImpl &Operands) {
4185 ARMAsmParser::OperandMatchResultTy
4186 ARMAsmParser::parseBitfield(OperandVector &Operands) {
42024187 SMLoc S = Parser.getTok().getLoc();
42034188 // The bitfield descriptor is really two operands, the LSB and the width.
42044189 if (Parser.getTok().isNot(AsmToken::Hash) &&
42654250 return MatchOperand_Success;
42664251 }
42674252
4268 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4269 parsePostIdxReg(SmallVectorImpl &Operands) {
4253 ARMAsmParser::OperandMatchResultTy
4254 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
42704255 // Check for a post-index addressing register operand. Specifically:
42714256 // postidx_reg := '+' register {, shift}
42724257 // | '-' register {, shift}
43144299 return MatchOperand_Success;
43154300 }
43164301
4317 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4318 parseAM3Offset(SmallVectorImpl &Operands) {
4302 ARMAsmParser::OperandMatchResultTy
4303 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
43194304 // Check for a post-index addressing register operand. Specifically:
43204305 // am3offset := '+' register
43214306 // | '-' register
43874372 /// Convert parsed operands to MCInst. Needed here because this instruction
43884373 /// only has two register operands, but multiplication is commutative so
43894374 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4390 void ARMAsmParser::
4391 cvtThumbMultiply(MCInst &Inst,
4392 const SmallVectorImpl &Operands) {
4393 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4394 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4375 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4376 const OperandVector &Operands) {
4377 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4378 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
43954379 // If we have a three-operand form, make sure to set Rn to be the operand
43964380 // that isn't the same as Rd.
43974381 unsigned RegOp = 4;
43984382 if (Operands.size() == 6 &&
4399 ((ARMOperand*)Operands[4])->getReg() ==
4400 ((ARMOperand*)Operands[3])->getReg())
4383 ((ARMOperand &)*Operands[4]).getReg() ==
4384 ((ARMOperand &)*Operands[3]).getReg())
44014385 RegOp = 5;
4402 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4386 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
44034387 Inst.addOperand(Inst.getOperand(0));
4404 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4388 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
44054389 }
44064390
4407 void ARMAsmParser::
4408 cvtThumbBranches(MCInst &Inst,
4409 const SmallVectorImpl &Operands) {
4391 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4392 const OperandVector &Operands) {
44104393 int CondOp = -1, ImmOp = -1;
44114394 switch(Inst.getOpcode()) {
44124395 case ARM::tB:
44294412 } else {
44304413 // outside IT blocks we can only have unconditional branches with AL
44314414 // condition code or conditional branches with non-AL condition code
4432 unsigned Cond = static_cast*>(Operands[CondOp])->getCondCode();
4415 unsigned Cond = static_cast &>(*Operands[CondOp]).getCondCode();
44334416 switch(Inst.getOpcode()) {
44344417 case ARM::tB:
44354418 case ARM::tBcc:
44464429 switch(Inst.getOpcode()) {
44474430 // classify tB as either t2B or t1B based on range of immediate operand
44484431 case ARM::tB: {
4449 ARMOperand* op = static_cast(Operands[ImmOp]);
4450 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4432 ARMOperand &op = static_cast(*Operands[ImmOp]);
4433 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
44514434 Inst.setOpcode(ARM::t2B);
44524435 break;
44534436 }
44544437 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
44554438 case ARM::tBcc: {
4456 ARMOperand* op = static_cast(Operands[ImmOp]);
4457 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4439 ARMOperand &op = static_cast(*Operands[ImmOp]);
4440 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
44584441 Inst.setOpcode(ARM::t2Bcc);
44594442 break;
44604443 }
44614444 }
4462 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4463 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4445 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4446 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
44644447 }
44654448
44664449 /// Parse an ARM memory expression, return false if successful else return true
44674450 /// or an error. The first token must be a '[' when called.
4468 bool ARMAsmParser::
4469 parseMemory(SmallVectorImpl &Operands) {
4451 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
44704452 SMLoc S, E;
44714453 assert(Parser.getTok().is(AsmToken::LBrac) &&
44724454 "Token is not a Left Bracket");
47164698 }
47174699
47184700 /// parseFPImm - A floating point immediate expression operand.
4719 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4720 parseFPImm(SmallVectorImpl &Operands) {
4701 ARMAsmParser::OperandMatchResultTy
4702 ARMAsmParser::parseFPImm(OperandVector &Operands) {
47214703 // Anything that can accept a floating point constant as an operand
47224704 // needs to go through here, as the regular parseExpression is
47234705 // integer only.
47434725 // integer constant. Make sure we don't try to parse an FPImm
47444726 // for these:
47454727 // vmov.i{8|16|32|64} , #imm
4746 ARMOperand *TyOp = static_cast(Operands[2]);
4747 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4748 TyOp->getToken() == ".f64");
4749 ARMOperand *Mnemonic = static_cast(Operands[0]);
4750 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4751 Mnemonic->getToken() == "fconsts");
4728 ARMOperand &TyOp = static_cast(*Operands[2]);
4729 bool isVmovf = TyOp.isToken() &&
4730 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4731 ARMOperand &Mnemonic = static_cast(*Operands[0]);
4732 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4733 Mnemonic.getToken() == "fconsts");
47524734 if (!(isVmovf || isFconst))
47534735 return MatchOperand_NoMatch;
47544736
47974779
47984780 /// Parse a arm instruction operand. For now this parses the operand regardless
47994781 /// of the mnemonic.
4800 bool ARMAsmParser::parseOperand(SmallVectorImpl &Operands,
4801 StringRef Mnemonic) {
4782 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
48024783 SMLoc S, E;
48034784
48044785 // Check if the current operand has a custom associated parser, if so, try to
51245105 }
51255106
51265107 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5127 SmallVectorImpl &Operands) {
5108 OperandVector &Operands) {
51285109 // FIXME: This is all horribly hacky. We really need a better way to deal
51295110 // with optional operands like this in the matcher table.
51305111
51375118 // conditionally adding the cc_out in the first place because we need
51385119 // to check the type of the parsed immediate operand.
51395120 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5140 !static_cast(Operands[4])->isARMSOImm() &&
5141 static_cast(Operands[4])->isImm0_65535Expr() &&
5142 static_cast(Operands[1])->getReg() == 0)
5121 !static_cast(*Operands[4]).isARMSOImm() &&
5122 static_cast(*Operands[4]).isImm0_65535Expr() &&
5123 static_cast(*Operands[1]).getReg() == 0)
51435124 return true;
51445125
51455126 // Register-register 'add' for thumb does not have a cc_out operand
51465127 // when there are only two register operands.
51475128 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5148 static_cast(Operands[3])->isReg() &&
5149 static_cast(Operands[4])->isReg() &&
5150 static_cast*>(Operands[1])->getReg() == 0)
5129 static_cast &>(*Operands[3]).isReg() &&
5130 static_cast(*Operands[4]).isReg() &&
5131 static_cast(*Operands[1]).getReg() == 0)
51515132 return true;
51525133 // Register-register 'add' for thumb does not have a cc_out operand
51535134 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
51555136 // that can handle a different range and has a cc_out operand.
51565137 if (((isThumb() && Mnemonic == "add") ||
51575138 (isThumbTwo() && Mnemonic == "sub")) &&
5158 Operands.size() == 6 &&
5159 static_cast(Operands[3])->isReg() &&
5160 static_cast(Operands[4])->isReg() &&
5161 static_cast(Operands[4])->getReg() == ARM::SP &&
5162 static_cast(Operands[1])->getReg() == 0 &&
5163 ((Mnemonic == "add" &&static_cast(Operands[5])->isReg()) ||
5164 static_cast(Operands[5])->isImm0_1020s4()))
5139 Operands.size() == 6 && static_cast(*Operands[3]).isReg() &&
5140 static_cast(*Operands[4]).isReg() &&
5141 static_cast(*Operands[4]).getReg() == ARM::SP &&
5142 static_cast(*Operands[1]).getReg() == 0 &&
5143 ((Mnemonic == "add" && static_cast(*Operands[5]).isReg()) ||
5144 static_cast(*Operands[5]).isImm0_1020s4()))
51655145 return true;
51665146 // For Thumb2, add/sub immediate does not have a cc_out operand for the
51675147 // imm0_4095 variant. That's the least-preferred variant when
51695149 // should remove the cc_out operand, we have to explicitly check that
51705150 // it's not one of the other variants. Ugh.
51715151 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5172 Operands.size() == 6 &&
5173 static_cast(Operands[3])->isReg() &&
5174 static_cast(Operands[4])->isReg() &&
5175 static_cast(Operands[5])->isImm()) {
5152 Operands.size() == 6 && static_cast(*Operands[3]).isReg() &&
5153 static_cast(*Operands[4]).isReg() &&
5154 static_cast(*Operands[5]).isImm()) {
51765155 // Nest conditions rather than one big 'if' statement for readability.
51775156 //
51785157 // If both registers are low, we're in an IT block, and the immediate is
51795158 // in range, we should use encoding T1 instead, which has a cc_out.
51805159 if (inITBlock() &&
5181 isARMLowRegister(static_cast(Operands[3])->getReg()) &&
5182 isARMLowRegister(static_cast(Operands[4])->getReg()) &&
5183 static_cast(Operands[5])->isImm0_7())
5160 isARMLowRegister(static_cast(*Operands[3]).getReg()) &&
5161 isARMLowRegister(static_cast(*Operands[4]).getReg()) &&
5162 static_cast(*Operands[5]).isImm0_7())
51845163 return false;
51855164 // Check against T3. If the second register is the PC, this is an
51865165 // alternate form of ADR, which uses encoding T4, so check for that too.
5187 if (static_cast(Operands[4])->getReg() != ARM::PC &&
5188 static_cast(Operands[5])->isT2SOImm())
5166 if (static_cast(*Operands[4]).getReg() != ARM::PC &&
5167 static_cast(*Operands[5]).isT2SOImm())
51895168 return false;
51905169
51915170 // Otherwise, we use encoding T4, which does not have a cc_out
51975176 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
51985177 // use the 16-bit encoding or not.
51995178 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5200 static_cast(Operands[1])->getReg() == 0 &&
5201 static_cast(Operands[3])->isReg() &&
5202 static_cast(Operands[4])->isReg() &&
5203 static_cast*>(Operands[5])->isReg() &&
5179 static_cast &>(*Operands[1]).getReg() == 0 &&
5180 static_cast(*Operands[3]).isReg() &&
5181 static_cast(*Operands[4]).isReg() &&
5182 static_cast(*Operands[5]).isReg() &&
52045183 // If the registers aren't low regs, the destination reg isn't the
52055184 // same as one of the source regs, or the cc_out operand is zero
52065185 // outside of an IT block, we have to use the 32-bit encoding, so
52075186 // remove the cc_out operand.
5208 (!isARMLowRegister(static_cast(Operands[3])->getReg()) ||
5209 !isARMLowRegister(static_cast(Operands[4])->getReg()) ||
5210 !isARMLowRegister(static_cast(Operands[5])->getReg()) ||
5211 !inITBlock() ||
5212 (static_cast(Operands[3])->getReg() !=
5213 static_cast(Operands[5])->getReg() &&
5214 static_cast(Operands[3])->getReg() !=
5215 static_cast(Operands[4])->getReg())))
5187 (!isARMLowRegister(static_cast(*Operands[3]).getReg()) ||
5188 !isARMLowRegister(static_cast(*Operands[4]).getReg()) ||
5189 !isARMLowRegister(static_cast(*Operands[5]).getReg()) ||
5190 !inITBlock() || (static_cast(*Operands[3]).getReg() !=
5191 static_cast(*Operands[5]).getReg() &&
5192 static_cast(*Operands[3]).getReg() !=
5193 static_cast(*Operands[4]).getReg())))
52165194 return true;
52175195
52185196 // Also check the 'mul' syntax variant that doesn't specify an explicit
52195197 // destination register.
52205198 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5221 static_cast(Operands[1])->getReg() == 0 &&
5222 static_cast(Operands[3])->isReg() &&
5223 static_cast*>(Operands[4])->isReg() &&
5199 static_cast &>(*Operands[1]).getReg() == 0 &&
5200 static_cast(*Operands[3]).isReg() &&
5201 static_cast(*Operands[4]).isReg() &&
52245202 // If the registers aren't low regs or the cc_out operand is zero
52255203 // outside of an IT block, we have to use the 32-bit encoding, so
52265204 // remove the cc_out operand.
5227 (!isARMLowRegister(static_cast(Operands[3])->getReg()) ||
5228 !isARMLowRegister(static_cast(Operands[4])->getReg()) ||
5205 (!isARMLowRegister(static_cast(*Operands[3]).getReg()) ||
5206 !isARMLowRegister(static_cast(*Operands[4]).getReg()) ||
52295207 !inITBlock()))
52305208 return true;
52315209
52385216 // anyway.
52395217 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
52405218 (Operands.size() == 5 || Operands.size() == 6) &&
5241 static_cast(Operands[3])->isReg() &&
5242 static_cast(Operands[3])->getReg() == ARM::SP &&
5243 static_cast(Operands[1])->getReg() == 0 &&
5244 (static_cast(Operands[4])->isImm() ||
5219 static_cast(*Operands[3]).isReg() &&
5220 static_cast(*Operands[3]).getReg() == ARM::SP &&
5221 static_cast(*Operands[1]).getReg() == 0 &&
5222 (static_cast(*Operands[4]).isImm() ||
52455223 (Operands.size() == 6 &&
5246 static_cast*>(Operands[5])->isImm())))
5224 static_cast &>(*Operands[5]).isImm())))
52475225 return true;
52485226
52495227 return false;
52505228 }
52515229
5252 bool ARMAsmParser::shouldOmitPredicateOperand(
5253 StringRef Mnemonic, SmallVectorImpl &Operands) {
5230 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5231 OperandVector &Operands) {
52545232 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
52555233 unsigned RegIdx = 3;
52565234 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5257 static_cast(Operands[2])->getToken() == ".f32") {
5258 if (static_cast(Operands[3])->isToken() &&
5259 static_cast(Operands[3])->getToken() == ".f32")
5235 static_cast(*Operands[2]).getToken() == ".f32") {
5236 if (static_cast(*Operands[3]).isToken() &&
5237 static_cast(*Operands[3]).getToken() == ".f32")
52605238 RegIdx = 4;
52615239
5262 if (static_cast(Operands[RegIdx])->isReg() &&
5263 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5264 .contains(static_cast(Operands[RegIdx])->getReg()) ||
5265 ARMMCRegisterClasses[ARM::QPRRegClassID]
5266 .contains(static_cast(Operands[RegIdx])->getReg())))
5240 if (static_cast(*Operands[RegIdx]).isReg() &&
5241 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5242 static_cast(*Operands[RegIdx]).getReg()) ||
5243 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5244 static_cast(*Operands[RegIdx]).getReg())))
52675245 return true;
52685246 }
52695247 return false;
53085286
53095287 /// Parse an arm instruction mnemonic followed by its operands.
53105288 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5311 SMLoc NameLoc,
5312 SmallVectorImpl &Operands) {
5289 SMLoc NameLoc, OperandVector &Operands) {
53135290 // FIXME: Can this be done via tablegen in some fashion?
53145291 bool RequireVFPRegisterListCheck;
53155292 bool AcceptSinglePrecisionOnly;
54885465 Parser.Lex(); // Consume the EndOfStatement
54895466
54905467 if (RequireVFPRegisterListCheck) {
5491 ARMOperand *Op = static_cast(Operands.back());
5492 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5493 return Error(Op->getStartLoc(),
5468 ARMOperand &Op = static_cast(*Operands.back());
5469 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5470 return Error(Op.getStartLoc(),
54945471 "VFP/Neon single precision register expected");
5495 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5496 return Error(Op->getStartLoc(),
5472 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5473 return Error(Op.getStartLoc(),
54975474 "VFP/Neon double precision register expected");
54985475 }
54995476
55045481 // try to remove a cc_out operand that was explicitly set on the the
55055482 // mnemonic, of course (CarrySetting == true). Reason number #317 the
55065483 // table driven matcher doesn't fit well with the ARM instruction set.
5507 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5508 ARMOperand *Op = static_cast(Operands[1]);
5484 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
55095485 Operands.erase(Operands.begin() + 1);
5510 delete Op;
5511 }
55125486
55135487 // Some instructions have the same mnemonic, but don't always
55145488 // have a predicate. Distinguish them here and delete the
55155489 // predicate if needed.
5516 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5517 ARMOperand *Op = static_cast(Operands[1]);
5490 if (shouldOmitPredicateOperand(Mnemonic, Operands))
55185491 Operands.erase(Operands.begin() + 1);
5519 delete Op;
5520 }
55215492
55225493 // ARM mode 'blx' need special handling, as the register operand version
55235494 // is predicable, but the label operand version is not. So, we can't rely
55255496 // a k_CondCode operand in the list. If we're trying to match the label
55265497 // version, remove the k_CondCode operand here.
55275498 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5528 static_cast(Operands[2])->isImm()) {
5529 ARMOperand *Op = static_cast(Operands[1]);
5499 static_cast(*Operands[2]).isImm())
55305500 Operands.erase(Operands.begin() + 1);
5531 delete Op;
5532 }
55335501
55345502 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
55355503 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
55425510 Mnemonic == "stlexd")) {
55435511 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
55445512 unsigned Idx = isLoad ? 2 : 3;
5545 ARMOperand* Op1 = static_cast(Operands[Idx]);
5546 ARMOperand* Op2 = static_cast(Operands[Idx+1]);
5513 ARMOperand &Op1 = static_cast(*Operands[Idx]);
5514 ARMOperand &Op2 = static_cast(*Operands[Idx + 1]);
55475515
55485516 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
55495517 // Adjust only if Op1 and Op2 are GPRs.
5550 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5551 MRC.contains(Op2->getReg())) {
5552 unsigned Reg1 = Op1->getReg();
5553 unsigned Reg2 = Op2->getReg();
5518 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5519 MRC.contains(Op2.getReg())) {
5520 unsigned Reg1 = Op1.getReg();
5521 unsigned Reg2 = Op2.getReg();
55545522 unsigned Rt = MRI->getEncodingValue(Reg1);
55555523 unsigned Rt2 = MRI->getEncodingValue(Reg2);
55565524
55575525 // Rt2 must be Rt + 1 and Rt must be even.
55585526 if (Rt + 1 != Rt2 || (Rt & 1)) {
5559 Error(Op2->getStartLoc(), isLoad ?
5560 "destination operands must be sequential" :
5561 "source operands must be sequential");
5527 Error(Op2.getStartLoc(), isLoad
5528 ? "destination operands must be sequential"
5529 : "source operands must be sequential");
55625530 return true;
55635531 }
55645532 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
55655533 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5566 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5567 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5568 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5569 delete Op1;
5570 delete Op2;
5534 Operands[Idx] =
5535 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5536 Operands.erase(Operands.begin() + Idx + 1);
55715537 }
55725538 }
55735539
55745540 // GNU Assembler extension (compatibility)
55755541 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5576 ARMOperand *Op2 = static_cast(Operands[2]);
5577 ARMOperand *Op3 = static_cast(Operands[3]);
5578 if (Op3->isMem()) {
5579 assert(Op2->isReg() && "expected register argument");
5542 ARMOperand &Op2 = static_cast(*Operands[2]);
5543 ARMOperand &Op3 = static_cast(*Operands[3]);
5544 if (Op3.isMem()) {
5545 assert(Op2.isReg() && "expected register argument");
55805546
55815547 unsigned SuperReg = MRI->getMatchingSuperReg(
5582 Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5548 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
55835549
55845550 assert(SuperReg && "expected register pair");
55855551
55865552 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
55875553
5588 Operands.insert(Operands.begin() + 3,
5589 ARMOperand::CreateReg(PairedReg,
5590 Op2->getStartLoc(),
5591 Op2->getEndLoc()));
5554 Operands.insert(
5555 Operands.begin() + 3,
5556 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
55925557 }
55935558 }
55945559
55985563 // so the Mnemonic is the original name "subs" and delete the predicate
55995564 // operand so it will match the table entry.
56005565 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5601 static_cast(Operands[3])->isReg() &&
5602 static_cast(Operands[3])->getReg() == ARM::PC &&
5603 static_cast(Operands[4])->isReg() &&
5604 static_cast(Operands[4])->getReg() == ARM::LR &&
5605 static_cast(Operands[5])->isImm()) {
5606 ARMOperand *Op0 = static_cast(Operands[0]);
5607 Operands.erase(Operands.begin());
5608 delete Op0;
5609 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5610
5611 ARMOperand *Op1 = static_cast(Operands[1]);
5566 static_cast(*Operands[3]).isReg() &&
5567 static_cast(*Operands[3]).getReg() == ARM::PC &&
5568 static_cast(*Operands[4]).isReg() &&
5569 static_cast(*Operands[4]).getReg() == ARM::LR &&
5570 static_cast(*Operands[5]).isImm()) {
5571 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
56125572 Operands.erase(Operands.begin() + 1);
5613 delete Op1;
56145573 }
56155574 return false;
56165575 }
56565615 }
56575616
56585617 // FIXME: We would really like to be able to tablegen'erate this.
5659 bool ARMAsmParser::
5660 validateInstruction(MCInst &Inst,
5661 const SmallVectorImpl &Operands) {
5618 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5619 const OperandVector &Operands) {
56625620 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
56635621 SMLoc Loc = Operands[0]->getStartLoc();
56645622
56815639 // Find the condition code Operand to get its SMLoc information.
56825640 SMLoc CondLoc;
56835641 for (unsigned I = 1; I < Operands.size(); ++I)
5684 if (static_cast*>(Operands[I])->isCondCode())
5642 if (static_cast &>(*Operands[I]).isCondCode())
56855643 CondLoc = Operands[I]->getStartLoc();
56865644 return Error(CondLoc, "incorrect condition in IT block; got '" +
56875645 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
57815739 // in the register list.
57825740 unsigned Rn = Inst.getOperand(0).getReg();
57835741 bool HasWritebackToken =
5784 (static_cast(Operands[3])->isToken() &&
5785 static_cast(Operands[3])->getToken() == "!");
5742 (static_cast(*Operands[3]).isToken() &&
5743 static_cast(*Operands[3]).getToken() == "!");
57865744 bool ListContainsBase;
57875745 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
57885746 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
58425800 // this first statement is always true for the new Inst. Essentially, the
58435801 // destination is unconditionally copied into the second source operand
58445802 // without checking to see if it matches what we actually parsed.
5845 if (Operands.size() == 6 &&
5846 (((ARMOperand*)Operands[3])->getReg() !=
5847 ((ARMOperand*)Operands[5])->getReg()) &&
5848 (((ARMOperand*)Operands[3])->getReg() !=
5849 ((ARMOperand*)Operands[4])->getReg())) {
5803 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5804 ((ARMOperand &)*Operands[5]).getReg()) &&
5805 (((ARMOperand &)*Operands[3]).getReg() !=
5806 ((ARMOperand &)*Operands[4]).getReg())) {
58505807 return Error(Operands[3]->getStartLoc(),
58515808 "destination register must match source register");
58525809 }
58995856 }
59005857 // Final range checking for Thumb unconditional branch instructions.
59015858 case ARM::tB:
5902 if (!(static_cast*>(Operands[2]))->isSignedOffset<11, 1>())
5859 if (!(static_cast &>(*Operands[2])).isSignedOffset<11, 1>())
59035860 return Error(Operands[2]->getStartLoc(), "branch target out of range");
59045861 break;
59055862 case ARM::t2B: {
59065863 int op = (Operands[2]->isImm()) ? 2 : 3;
5907 if (!(static_cast(Operands[op]))->isSignedOffset<24, 1>())
5864 if (!static_cast(*Operands[op]).isSignedOffset<24, 1>())
59085865 return Error(Operands[op]->getStartLoc(), "branch target out of range");
59095866 break;
59105867 }
59115868 // Final range checking for Thumb conditional branch instructions.
59125869 case ARM::tBcc:
5913 if (!(static_cast(Operands[2]))->isSignedOffset<8, 1>())
5870 if (!static_cast(*Operands[2]).isSignedOffset<8, 1>())
59145871 return Error(Operands[2]->getStartLoc(), "branch target out of range");
59155872 break;
59165873 case ARM::t2Bcc: {
59175874 int Op = (Operands[2]->isImm()) ? 2 : 3;
5918 if (!(static_cast(Operands[Op]))->isSignedOffset<20, 1>())
5875 if (!static_cast(*Operands[Op]).isSignedOffset<20, 1>())
59195876 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
59205877 break;
59215878 }
59305887 // lead to bugs that are difficult to find since this is an easy mistake
59315888 // to make.
59325889 int i = (Operands[3]->isImm()) ? 3 : 4;
5933 ARMOperand *Op = static_cast(Operands[i]);
5934 const MCConstantExpr *CE = dyn_cast(Op->getImm());
5890 ARMOperand &Op = static_cast(*Operands[i]);
5891 const MCConstantExpr *CE = dyn_cast(Op.getImm());
59355892 if (CE) break;
5936 const MCExpr *E = dyn_cast(Op->getImm());
5893 const MCExpr *E = dyn_cast(Op.getImm());
59375894 if (!E) break;
59385895 const ARMMCExpr *ARM16Expr = dyn_cast(E);
59395896 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5940 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) {
5941 return Error(Op->getStartLoc(),
5942 "immediate expression for mov requires :lower16: or :upper16");
5943 break;
5944 }
5945 }
5897 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
5898 return Error(
5899 Op.getStartLoc(),
5900 "immediate expression for mov requires :lower16: or :upper16");
5901 break;
5902 }
59465903 }
59475904
59485905 return false;
62046161 }
62056162 }
62066163
6207 bool ARMAsmParser::
6208 processInstruction(MCInst &Inst,
6209 const SmallVectorImpl &Operands) {
6164 bool ARMAsmParser::processInstruction(MCInst &Inst,
6165 const OperandVector &Operands) {
62106166 switch (Inst.getOpcode()) {
62116167 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
62126168 case ARM::LDRT_POST:
62636219 // Select the narrow version if the immediate will fit.
62646220 if (Inst.getOperand(1).getImm() > 0 &&
62656221 Inst.getOperand(1).getImm() <= 0xff &&
6266 !(static_cast(Operands[2])->isToken() &&
6267 static_cast(Operands[2])->getToken() == ".w"))
6222 !(static_cast(*Operands[2]).isToken() &&
6223 static_cast(*Operands[2]).getToken() == ".w"))
62686224 Inst.setOpcode(ARM::tLDRpci);
62696225 else
62706226 Inst.setOpcode(ARM::t2LDRpci);
73547310 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
73557311 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
73567312 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7357 !(static_cast(Operands[3])->isToken() &&
7358 static_cast(Operands[3])->getToken() == ".w")) {
7313 !(static_cast(*Operands[3]).isToken() &&
7314 static_cast(*Operands[3]).getToken() == ".w")) {
73597315 unsigned NewOpc;
73607316 switch (Inst.getOpcode()) {
73617317 default: llvm_unreachable("unexpected opcode");
75587514 case ARM::LDMIA_UPD:
75597515 // If this is a load of a single register via a 'pop', then we should use
75607516 // a post-indexed LDR instruction instead, per the ARM ARM.
7561 if (static_cast*>(Operands[0])->getToken() == "pop" &&
7517 if (static_cast &>(*Operands[0]).getToken() == "pop" &&
75627518 Inst.getNumOperands() == 5) {
75637519 MCInst TmpInst;
75647520 TmpInst.setOpcode(ARM::LDR_POST_IMM);
75767532 case ARM::STMDB_UPD:
75777533 // If this is a store of a single register via a 'push', then we should use
75787534 // a pre-indexed STR instruction instead, per the ARM ARM.
7579 if (static_cast*>(Operands[0])->getToken() == "push" &&
7535 if (static_cast &>(*Operands[0]).getToken() == "push" &&
75807536 Inst.getNumOperands() == 5) {
75817537 MCInst TmpInst;
75827538 TmpInst.setOpcode(ARM::STR_PRE_IMM);
75927548 case ARM::t2ADDri12:
75937549 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
75947550 // mnemonic was used (not "addw"), encoding T3 is preferred.
7595 if (static_cast*>(Operands[0])->getToken() != "add" ||
7551 if (static_cast &>(*Operands[0]).getToken() != "add" ||
75967552 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
75977553 break;
75987554 Inst.setOpcode(ARM::t2ADDri);
76017557 case ARM::t2SUBri12:
76027558 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
76037559 // mnemonic was used (not "subw"), encoding T3 is preferred.
7604 if (static_cast*>(Operands[0])->getToken() != "sub" ||
7560 if (static_cast &>(*Operands[0]).getToken() != "sub" ||
76057561 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
76067562 break;
76077563 Inst.setOpcode(ARM::t2SUBri);
76377593 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
76387594 (unsigned)Inst.getOperand(2).getImm() > 255 ||
76397595 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7640 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7641 (static_cast(Operands[3])->isToken() &&
7642 static_cast(Operands[3])->getToken() == ".w"))
7596 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7597 (static_cast(*Operands[3]).isToken() &&
7598 static_cast(*Operands[3]).getToken() == ".w"))
76437599 break;
76447600 MCInst TmpInst;
76457601 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
76607616 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
76617617 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
76627618 Inst.getOperand(5).getReg() != 0 ||
7663 (static_cast(Operands[3])->isToken() &&
7664 static_cast(Operands[3])->getToken() == ".w"))
7619 (static_cast(*Operands[3]).isToken() &&
7620 static_cast(*Operands[3]).getToken() == ".w"))
76657621 break;
76667622 MCInst TmpInst;
76677623 TmpInst.setOpcode(ARM::tADDhirr);
77187674 // an error in validateInstruction().
77197675 unsigned Rn = Inst.getOperand(0).getReg();
77207676 bool hasWritebackToken =
7721 (static_cast(Operands[3])->isToken() &&
7722 static_cast(Operands[3])->getToken() == "!");
7677 (static_cast(*Operands[3]).isToken() &&
7678 static_cast(*Operands[3]).getToken() == "!");
77237679 bool listContainsBase;
77247680 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
77257681 (!listContainsBase && !hasWritebackToken) ||
77817737 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
77827738 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
77837739 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7784 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7785 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7786 (!static_cast(Operands[2])->isToken() ||
7787 static_cast(Operands[2])->getToken() != ".w")) {
7740 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7741 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7742 (!static_cast(*Operands[2]).isToken() ||
7743 static_cast(*Operands[2]).getToken() != ".w")) {
77887744 // The operands aren't in the same order for tMOVi8...
77897745 MCInst TmpInst;
77907746 TmpInst.setOpcode(ARM::tMOVi8);
78057761 isARMLowRegister(Inst.getOperand(1).getReg()) &&
78067762 Inst.getOperand(2).getImm() == ARMCC::AL &&
78077763 Inst.getOperand(4).getReg() == ARM::CPSR &&
7808 (!static_cast(Operands[2])->isToken() ||
7809 static_cast(Operands[2])->getToken() != ".w")) {
7764 (!static_cast(*Operands[2]).isToken() ||
7765 static_cast(*Operands[2]).getToken() != ".w")) {
78107766 // The operands aren't the same for tMOV[S]r... (no cc_out)
78117767 MCInst TmpInst;
78127768 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
78287784 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
78297785 isARMLowRegister(Inst.getOperand(1).getReg()) &&
78307786 Inst.getOperand(2).getImm() == 0 &&
7831 (!static_cast(Operands[2])->isToken() ||
7832 static_cast(Operands[2])->getToken() != ".w")) {
7787 (!static_cast(*Operands[2]).isToken() ||
7788 static_cast(*Operands[2]).getToken() != ".w")) {
78337789 unsigned NewOpc;
78347790 switch (Inst.getOpcode()) {
78357791 default: llvm_unreachable("Illegal opcode!");
79417897 isARMLowRegister(Inst.getOperand(2).getReg())) &&
79427898 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
79437899 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7944 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7945 (!static_cast(Operands[3])->isToken() ||
7946 !static_cast(Operands[3])->getToken().equals_lower(".w"))) {
7900 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7901 (!static_cast(*Operands[3]).isToken() ||
7902 !static_cast(*Operands[3]).getToken().equals_lower(
7903 ".w"))) {
79477904 unsigned NewOpc;
79487905 switch (Inst.getOpcode()) {
79497906 default: llvm_unreachable("unexpected opcode");
79807937 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
79817938 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
79827939 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7983 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7984 (!static_cast(Operands[3])->isToken() ||
7985 !static_cast(Operands[3])->getToken().equals_lower(".w"))) {
7940 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7941 (!static_cast(*Operands[3]).isToken() ||
7942 !static_cast(*Operands[3]).getToken().equals_lower(
7943 ".w"))) {
79867944 unsigned NewOpc;
79877945 switch (Inst.getOpcode()) {
79887946 default: llvm_unreachable("unexpected opcode");
80628020 }
80638021
80648022 static const char *getSubtargetFeatureName(unsigned Val);
8065 bool ARMAsmParser::
8066 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8067 SmallVectorImpl &Operands,
8068 MCStreamer &Out, unsigned &ErrorInfo,
8069 bool MatchingInlineAsm) {
8023 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8024 OperandVector &Operands,
8025 MCStreamer &Out, unsigned &ErrorInfo,
8026 bool MatchingInlineAsm) {
80708027 MCInst Inst;
80718028 unsigned MatchResult;
80728029
81358092 if (ErrorInfo >= Operands.size())
81368093 return Error(IDLoc, "too few operands for instruction");
81378094
8138 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8095 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
81398096 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
81408097 }
81418098
81438100 }
81448101 case Match_MnemonicFail:
81458102 return Error(IDLoc, "invalid instruction",
8146 ((ARMOperand*)Operands[0])->getLocRange());
8103 ((ARMOperand &)*Operands[0]).getLocRange());
81478104 case Match_RequiresNotITBlock:
81488105 return Error(IDLoc, "flag setting instruction only valid outside IT block");
81498106 case Match_RequiresITBlock:
81538110 case Match_RequiresThumb2:
81548111 return Error(IDLoc, "instruction variant requires Thumb2");
81558112 case Match_ImmRange0_15: {
8156 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8113 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
81578114 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
81588115 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
81598116 }
81608117 case Match_ImmRange0_239: {
8161 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8118 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
81628119 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
81638120 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
81648121 }
81748131 case Match_DupAlignedMemoryRequires64or128:
81758132 case Match_AlignedMemoryRequires64or128or256:
81768133 {
8177 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8134 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
81788135 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
81798136 switch (MatchResult) {
81808137 default:
89228879 }
89238880
89248881 // RAII object to make sure parsed operands are deleted.
8925 struct CleanupObject {
8926 SmallVector Operands;
8927 ~CleanupObject() {
8928 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8929 delete Operands[I];
8930 }
8931 } CO;
8882 SmallVector, 1> Operands;
89328883
89338884 // Parse the register list
8934 if (parseRegisterList(CO.Operands))
8935 return false;
8936 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8937 if (!IsVector && !Op->isRegList()) {
8885 if (parseRegisterList(Operands))
8886 return false;
8887 ARMOperand &Op = (ARMOperand &)*Operands[0];
8888 if (!IsVector && !Op.isRegList()) {
89388889 Error(L, ".save expects GPR registers");
89398890 return false;
89408891 }
8941 if (IsVector && !Op->isDPRRegList()) {
8892 if (IsVector && !Op.isDPRRegList()) {
89428893 Error(L, ".vsave expects DPR registers");
89438894 return false;
89448895 }
89458896
8946 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8897 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
89478898 return false;
89488899 }
89498900
94679418
94689419 // Define this matcher function after the auto-generated include so we
94699420 // have the match class enum definitions.
9470 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9421 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
94719422 unsigned Kind) {
9472 ARMOperand *Op = static_cast>(AsmOp);
9423 ARMOperand &Op = static_cast>(AsmOp);
94739424 // If the kind is a token for a literal immediate, check if our asm
94749425 // operand matches. This is for InstAliases which have a fixed-value
94759426 // immediate in the syntax.
94769427 switch (Kind) {
94779428 default: break;
94789429 case MCK__35_0:
9479 if (Op->isImm())
9480 if (const MCConstantExpr *CE = dyn_cast(Op->getImm()))
9430 if (Op.isImm())
9431 if (const MCConstantExpr *CE = dyn_cast(Op.getImm()))
94819432 if (CE->getValue() == 0)
94829433 return Match_Success;
94839434 break;
94849435 case MCK_ARMSOImm:
9485 if (Op->isImm()) {
9486 const MCExpr *SOExpr = Op->getImm();
9436 if (Op.isImm()) {
9437 const MCExpr *SOExpr = Op.getImm();
94879438 int64_t Value;
94889439 if (!SOExpr->EvaluateAsAbsolute(Value))
94899440 return Match_Success;
94929443 }
94939444 break;
94949445 case MCK_GPRPair:
9495 if (Op->isReg() &&
9496 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9446 if (Op.isReg() &&
9447 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
94979448 return Match_Success;
94989449 break;
94999450 }
7272 #include "MipsGenAsmMatcher.inc"
7373
7474 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
75 SmallVectorImpl &Operands,
76 MCStreamer &Out, unsigned &ErrorInfo,
75 OperandVector &Operands, MCStreamer &Out,
76 unsigned &ErrorInfo,
7777 bool MatchingInlineAsm) override;
7878
7979 /// Parse a register as used in CFI directives
8080 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
8181
82 bool ParseParenSuffix(StringRef Name,
83 SmallVectorImpl &Operands);
84
85 bool ParseBracketSuffix(StringRef Name,
86 SmallVectorImpl &Operands);
87
88 bool
89 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
90 SmallVectorImpl &Operands) override;
82 bool ParseParenSuffix(StringRef Name, OperandVector &Operands);
83
84 bool ParseBracketSuffix(StringRef Name, OperandVector &Operands);
85
86 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
87 SMLoc NameLoc, OperandVector &Operands) override;
9188
9289 bool ParseDirective(AsmToken DirectiveID) override;
9390
91 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
92
9493 MipsAsmParser::OperandMatchResultTy
95 parseMemOperand(SmallVectorImpl &Operands);
96
97 MipsAsmParser::OperandMatchResultTy MatchAnyRegisterNameWithoutDollar(
98 SmallVectorImpl &Operands, StringRef Identifier,
99 SMLoc S);
94 MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
95 StringRef Identifier, SMLoc S);
10096
10197 MipsAsmParser::OperandMatchResultTy
102 MatchAnyRegisterWithoutDollar(SmallVectorImpl &Operands,
103 SMLoc S);
104
105 MipsAsmParser::OperandMatchResultTy
106 ParseAnyRegister(SmallVectorImpl &Operands);
107
108 MipsAsmParser::OperandMatchResultTy
109 ParseImm(SmallVectorImpl &Operands);
110
111 MipsAsmParser::OperandMatchResultTy
112 ParseJumpTarget(SmallVectorImpl &Operands);
113
114 MipsAsmParser::OperandMatchResultTy
115 parseInvNum(SmallVectorImpl &Operands);
116
117 MipsAsmParser::OperandMatchResultTy
118 ParseLSAImm(SmallVectorImpl &Operands);
119
120 bool searchSymbolAlias(SmallVectorImpl &Operands);
121
122 bool ParseOperand(SmallVectorImpl &,
123 StringRef Mnemonic);
98 MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
99
100 MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands);
101
102 MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands);
103
104 MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands);
105
106 MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands);
107
108 MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands);
109
110 bool searchSymbolAlias(OperandVector &Operands);
111
112 bool ParseOperand(OperandVector &, StringRef Mnemonic);
124113
125114 bool needsExpansion(MCInst &Inst);
126115
288277 k_Token /// A simple token
289278 } Kind;
290279
280 public:
291281 MipsOperand(KindTy K, MipsAsmParser &Parser)
292282 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
293283
284 private:
294285 /// For diagnostics, and checking the assembler temporary
295286 MipsAsmParser &AsmParser;
296287
329320 SMLoc StartLoc, EndLoc;
330321
331322 /// Internal constructor for register kinds
332 static MipsOperand *CreateReg(unsigned Index, RegKind RegKind,
333 const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
334 MipsAsmParser &Parser) {
335 MipsOperand *Op = new MipsOperand(k_RegisterIndex, Parser);
323 static std::unique_ptr CreateReg(unsigned Index, RegKind RegKind,
324 const MCRegisterInfo *RegInfo,
325 SMLoc S, SMLoc E,
326 MipsAsmParser &Parser) {
327 auto Op = make_unique(k_RegisterIndex, Parser);
336328 Op->RegIdx.Index = Index;
337329 Op->RegIdx.RegInfo = RegInfo;
338330 Op->RegIdx.Kind = RegKind;
655647 return Mem.Off;
656648 }
657649
658 static MipsOperand *CreateToken(StringRef Str, SMLoc S,
659 MipsAsmParser &Parser) {
660 MipsOperand *Op = new MipsOperand(k_Token, Parser);
650 static std::unique_ptr CreateToken(StringRef Str, SMLoc S,
651 MipsAsmParser &Parser) {
652 auto Op = make_unique(k_Token, Parser);
661653 Op->Tok.Data = Str.data();
662654 Op->Tok.Length = Str.size();
663655 Op->StartLoc = S;
667659
668660 /// Create a numeric register (e.g. $1). The exact register remains
669661 /// unresolved until an instruction successfully matches
670 static MipsOperand *CreateNumericReg(unsigned Index,
671 const MCRegisterInfo *RegInfo, SMLoc S,
672 SMLoc E, MipsAsmParser &Parser) {
662 static std::unique_ptr
663 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
664 SMLoc E, MipsAsmParser &Parser) {
673665 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
674666 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
675667 }
676668
677669 /// Create a register that is definitely a GPR.
678670 /// This is typically only used for named registers such as $gp.
679 static MipsOperand *CreateGPRReg(unsigned Index,
680 const MCRegisterInfo *RegInfo, SMLoc S,
681 SMLoc E, MipsAsmParser &Parser) {
671 static std::unique_ptr
672 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
673 MipsAsmParser &Parser) {
682674 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
683675 }
684676
685677 /// Create a register that is definitely a FGR.
686678 /// This is typically only used for named registers such as $f0.
687 static MipsOperand *CreateFGRReg(unsigned Index,
688 const MCRegisterInfo *RegInfo, SMLoc S,
689 SMLoc E, MipsAsmParser &Parser) {
679 static std::unique_ptr
680 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
681 MipsAsmParser &Parser) {
690682 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
691683 }
692684
693685 /// Create a register that is definitely an FCC.
694686 /// This is typically only used for named registers such as $fcc0.
695 static MipsOperand *CreateFCCReg(unsigned Index,
696 const MCRegisterInfo *RegInfo, SMLoc S,
697 SMLoc E, MipsAsmParser &Parser) {
687 static std::unique_ptr
688 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
689 MipsAsmParser &Parser) {
698690 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
699691 }
700692
701693 /// Create a register that is definitely an ACC.
702694 /// This is typically only used for named registers such as $ac0.
703 static MipsOperand *CreateACCReg(unsigned Index,
704 const MCRegisterInfo *RegInfo, SMLoc S,
705 SMLoc E, MipsAsmParser &Parser) {
695 static std::unique_ptr
696 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
697 MipsAsmParser &Parser) {
706698 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
707699 }
708700
709701 /// Create a register that is definitely an MSA128.
710702 /// This is typically only used for named registers such as $w0.
711 static MipsOperand *CreateMSA128Reg(unsigned Index,
712 const MCRegisterInfo *RegInfo, SMLoc S,
713 SMLoc E, MipsAsmParser &Parser) {
703 static std::unique_ptr
704 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
705 SMLoc E, MipsAsmParser &Parser) {
714706 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
715707 }
716708
717709 /// Create a register that is definitely an MSACtrl.
718710 /// This is typically only used for named registers such as $msaaccess.
719 static MipsOperand *CreateMSACtrlReg(unsigned Index,
720 const MCRegisterInfo *RegInfo, SMLoc S,
721 SMLoc E, MipsAsmParser &Parser) {
711 static std::unique_ptr
712 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
713 SMLoc E, MipsAsmParser &Parser) {
722714 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
723715 }
724716
725 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
726 MipsAsmParser &Parser) {
727 MipsOperand *Op = new MipsOperand(k_Immediate, Parser);
717 static std::unique_ptr
718 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
719 auto Op = make_unique(k_Immediate, Parser);
728720 Op->Imm.Val = Val;
729721 Op->StartLoc = S;
730722 Op->EndLoc = E;
731723 return Op;
732724 }
733725
734 static MipsOperand *CreateMem(MipsOperand *Base, const MCExpr *Off, SMLoc S,
735 SMLoc E, MipsAsmParser &Parser) {
736 MipsOperand *Op = new MipsOperand(k_Memory, Parser);
737 Op->Mem.Base = Base;
726 static std::unique_ptr
727 CreateMem(std::unique_ptr Base, const MCExpr *Off, SMLoc S,
728 SMLoc E, MipsAsmParser &Parser) {
729 auto Op = make_unique(k_Memory, Parser);
730 Op->Mem.Base = Base.release();
738731 Op->Mem.Off = Off;
739732 Op->StartLoc = S;
740733 Op->EndLoc = E;
11631156 TempInst.clear();
11641157 }
11651158
1166 bool MipsAsmParser::MatchAndEmitInstruction(
1167 SMLoc IDLoc, unsigned &Opcode,
1168 SmallVectorImpl &Operands, MCStreamer &Out,
1169 unsigned &ErrorInfo, bool MatchingInlineAsm) {
1159 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1160 OperandVector &Operands,
1161 MCStreamer &Out,
1162 unsigned &ErrorInfo,
1163 bool MatchingInlineAsm) {
11701164 MCInst Inst;
11711165 SmallVector Instructions;
11721166 unsigned MatchResult =
11911185 if (ErrorInfo >= Operands.size())
11921186 return Error(IDLoc, "too few operands for instruction");
11931187
1194 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
1188 ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
11951189 if (ErrorLoc == SMLoc())
11961190 ErrorLoc = IDLoc;
11971191 }
13771371 return getReg(RegClass, RegNum);
13781372 }
13791373
1380 bool
1381 MipsAsmParser::ParseOperand(SmallVectorImpl &Operands,
1382 StringRef Mnemonic) {
1374 bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) {
13831375 DEBUG(dbgs() << "ParseOperand\n");
13841376
13851377 // Check if the current operand has a custom associated parser, if so, try to
15771569
15781570 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
15791571 SMLoc &EndLoc) {
1580 SmallVector<MCParsedAsmOperand *, 1> Operands;
1572 SmallVector<std::unique_ptr, 1> Operands;
15811573 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
15821574 if (ResTy == MatchOperand_Success) {
15831575 assert(Operands.size() == 1);
1584 MipsOperand &Operand = *static_cast(Operands.front());
1576 MipsOperand &Operand = static_cast(*Operands.front());
15851577 StartLoc = Operand.getStartLoc();
15861578 EndLoc = Operand.getEndLoc();
15871579
15931585 // Resolve to GPR32 or GPR64 appropriately.
15941586 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
15951587 }
1596
1597 delete &Operand;
15981588
15991589 return (RegNo == (unsigned)-1);
16001590 }
16311621 return Result;
16321622 }
16331623
1634 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1635 SmallVectorImpl &Operands) {
1624 MipsAsmParser::OperandMatchResultTy
1625 MipsAsmParser::parseMemOperand(OperandVector &Operands) {
16361626 DEBUG(dbgs() << "parseMemOperand\n");
16371627 const MCExpr *IdVal = nullptr;
16381628 SMLoc S;
16521642
16531643 const AsmToken &Tok = Parser.getTok(); // Get the next token.
16541644 if (Tok.isNot(AsmToken::LParen)) {
1655 MipsOperand *Mnemonic = static_cast(Operands[0]);
1656 if (Mnemonic->getToken() == "la") {
1645 MipsOperand &Mnemonic = static_cast(*Operands[0]);
1646 if (Mnemonic.getToken() == "la") {
16571647 SMLoc E =
16581648 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
16591649 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
16651655
16661656 // Zero register assumed, add a memory operand with ZERO as its base.
16671657 // "Base" will be managed by k_Memory.
1668 MipsOperand *Base = MipsOperand::CreateGPRReg(
1669 0, getContext().getRegisterInfo(), S, E, *this);
1670 Operands.push_back(MipsOperand::CreateMem(Base, IdVal, S, E, *this));
1658 auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(),
1659 S, E, *this);
1660 Operands.push_back(
1661 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
16711662 return MatchOperand_Success;
16721663 }
16731664 Error(Parser.getTok().getLoc(), "'(' expected");
16941685 IdVal = MCConstantExpr::Create(0, getContext());
16951686
16961687 // Replace the register operand with the memory operand.
1697 MipsOperand *op = static_cast(Operands.back());
1688 std::unique_ptr op(
1689 static_cast(Operands.back().release()));
16981690 // Remove the register from the operands.
16991691 // "op" will be managed by k_Memory.
17001692 Operands.pop_back();
17081700 getContext());
17091701 }
17101702
1711 Operands.push_back(MipsOperand::CreateMem(op, IdVal, S, E, *this));
1703 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
17121704 return MatchOperand_Success;
17131705 }
17141706
1715 bool MipsAsmParser::searchSymbolAlias(
1716 SmallVectorImpl &Operands) {
1707 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
17171708
17181709 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
17191710 if (Sym) {
17391730 } else if (Expr->getKind() == MCExpr::Constant) {
17401731 Parser.Lex();
17411732 const MCConstantExpr *Const = static_cast(Expr);
1742 MipsOperand *op =
1743 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this);
1744 Operands.push_back(op);
1733 Operands.push_back(
1734 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
17451735 return true;
17461736 }
17471737 }
17491739 }
17501740
17511741 MipsAsmParser::OperandMatchResultTy
1752 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(
1753 SmallVectorImpl &Operands, StringRef Identifier,
1754 SMLoc S) {
1742 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands,
1743 StringRef Identifier,
1744 SMLoc S) {
17551745 int Index = matchCPURegisterName(Identifier);
17561746 if (Index != -1) {
17571747 Operands.push_back(MipsOperand::CreateGPRReg(
17981788 }
17991789
18001790 MipsAsmParser::OperandMatchResultTy
1801 MipsAsmParser::MatchAnyRegisterWithoutDollar(
1802 SmallVectorImpl &Operands, SMLoc S) {
1791 MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
18031792 auto Token = Parser.getLexer().peekTok(false);
18041793
18051794 if (Token.is(AsmToken::Identifier)) {
18211810 return MatchOperand_NoMatch;
18221811 }
18231812
1824 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseAnyRegister(
1825 SmallVectorImpl &Operands) {
1813 MipsAsmParser::OperandMatchResultTy
1814 MipsAsmParser::ParseAnyRegister(OperandVector &Operands) {
18261815 DEBUG(dbgs() << "ParseAnyRegister\n");
18271816
18281817 auto Token = Parser.getTok();
18491838 }
18501839
18511840 MipsAsmParser::OperandMatchResultTy
1852 MipsAsmParser::ParseImm(SmallVectorImpl &Operands) {
1841 MipsAsmParser::ParseImm(OperandVector &Operands) {
18531842 switch (getLexer().getKind()) {
18541843 default:
18551844 return MatchOperand_NoMatch;
18711860 return MatchOperand_Success;
18721861 }
18731862
1874 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseJumpTarget(
1875 SmallVectorImpl &Operands) {
1863 MipsAsmParser::OperandMatchResultTy
1864 MipsAsmParser::ParseJumpTarget(OperandVector &Operands) {
18761865 DEBUG(dbgs() << "ParseJumpTarget\n");
18771866
18781867 SMLoc S = getLexer().getLoc();
18981887 }
18991888
19001889 MipsAsmParser::OperandMatchResultTy
1901 MipsAsmParser::parseInvNum(SmallVectorImpl &Operands) {
1890 MipsAsmParser::parseInvNum(OperandVector &Operands) {
19021891 const MCExpr *IdVal;
19031892 // If the first token is '$' we may have register operand.
19041893 if (Parser.getTok().is(AsmToken::Dollar))
19161905 }
19171906
19181907 MipsAsmParser::OperandMatchResultTy
1919 MipsAsmParser::ParseLSAImm(SmallVectorImpl &Operands) {
1908 MipsAsmParser::ParseLSAImm(OperandVector &Operands) {
19201909 switch (getLexer().getKind()) {
19211910 default:
19221911 return MatchOperand_NoMatch;
19951984 /// ::= '(', register, ')'
19961985 /// handle it before we iterate so we don't get tripped up by the lack of
19971986 /// a comma.
1998 bool MipsAsmParser::ParseParenSuffix(
1999 StringRef Name, SmallVectorImpl &Operands) {
1987 bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) {
20001988 if (getLexer().is(AsmToken::LParen)) {
20011989 Operands.push_back(
20021990 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
20242012 /// ::= '[', integer, ']'
20252013 /// handle it before we iterate so we don't get tripped up by the lack of
20262014 /// a comma.
2027 bool MipsAsmParser::ParseBracketSuffix(
2028 StringRef Name, SmallVectorImpl &Operands) {
2015 bool MipsAsmParser::ParseBracketSuffix(StringRef Name,
2016 OperandVector &Operands) {
20292017 if (getLexer().is(AsmToken::LBrac)) {
20302018 Operands.push_back(
20312019 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
20472035 return false;
20482036 }
20492037
2050 bool MipsAsmParser::ParseInstruction(
2051 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2052 SmallVectorImpl &Operands) {
2038 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2039 SMLoc NameLoc, OperandVector &Operands) {
20532040 DEBUG(dbgs() << "ParseInstruction\n");
20542041 // Check if we have valid mnemonic
20552042 if (!mnemonicIsValid(Name, 0)) {
23312318
23322319 // FIXME: Warn if cpload is used in Mips16 mode.
23332320
2334 SmallVector<MCParsedAsmOperand *, 1> Reg;
2321 SmallVector<std::unique_ptr, 1> Reg;
23352322 OperandMatchResultTy ResTy = ParseAnyRegister(Reg);
23362323 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
23372324 reportParseError("expected register containing function address");
23382325 return false;
23392326 }
23402327
2341 MipsOperand *RegOpnd = static_cast(Reg[0]);
2342 if (!RegOpnd->isGPRAsmReg()) {
2343 reportParseError(RegOpnd->getStartLoc(), "invalid register");
2344 return false;
2345 }
2346
2347 getTargetStreamer().emitDirectiveCpload(RegOpnd->getGPR32Reg());
2348 delete RegOpnd;
2328 MipsOperand &RegOpnd = static_cast(*Reg[0]);
2329 if (!RegOpnd.isGPRAsmReg()) {
2330 reportParseError(RegOpnd.getStartLoc(), "invalid register");
2331 return false;
2332 }
2333
2334 getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg());
23492335 return false;
23502336 }
23512337
237237 bool ParseExpression(const MCExpr *&EVal);
238238 bool ParseDarwinExpression(const MCExpr *&EVal);
239239
240 bool ParseOperand(SmallVectorImpl &Operands);
240 bool ParseOperand(OperandVector &Operands);
241241
242242 bool ParseDirectiveWord(unsigned Size, SMLoc L);
243243 bool ParseDirectiveTC(unsigned Size, SMLoc L);
245245 bool ParseDarwinDirectiveMachine(SMLoc L);
246246
247247 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
248 SmallVectorImpl &Operands,
249 MCStreamer &Out, unsigned &ErrorInfo,
248 OperandVector &Operands, MCStreamer &Out,
249 unsigned &ErrorInfo,
250250 bool MatchingInlineAsm) override;
251251
252 void ProcessInstruction(MCInst &Inst,
253 const SmallVectorImpl &Ops);
252 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
254253
255254 /// @name Auto-generated Match Functions
256255 /// {
275274 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276275 }
277276
278 bool ParseInstruction(ParseInstructionInfo &Info,
279 StringRef Name, SMLoc NameLoc,
280 SmallVectorImpl &Operands) override;
277 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
278 SMLoc NameLoc, OperandVector &Operands) override;
281279
282280 bool ParseDirective(AsmToken DirectiveID) override;
283281
284 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
282 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
285283 unsigned Kind) override;
286284
287285 const MCExpr *applyModifierToExpr(const MCExpr *E,
547545
548546 void print(raw_ostream &OS) const override;
549547
550 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
551 PPCOperand *Op = new PPCOperand(Token);
548 static std::unique_ptr CreateToken(StringRef Str, SMLoc S,
549 bool IsPPC64) {
550 auto Op = make_unique(Token);
552551 Op->Tok.Data = Str.data();
553552 Op->Tok.Length = Str.size();
554553 Op->StartLoc = S;
557556 return Op;
558557 }
559558
560 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
561 bool IsPPC64) {
559 static std::unique_ptr
560 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
562561 // Allocate extra memory for the string and copy it.
562 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
563 // deleter which will destroy them by simply using "delete", not correctly
564 // calling operator delete on this extra memory after calling the dtor
565 // explicitly.
563566 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
564 PPCOperand *Op = new (Mem) PPCOperand(Token);
565 Op->Tok.Data = (const char *)(Op + 1);
567 std::unique_ptr Op(new (Mem) PPCOperand(Token));
568 Op->Tok.Data = (const char *)(Op.get() + 1);
566569 Op->Tok.Length = Str.size();
567 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
570 std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
568571 Op->StartLoc = S;
569572 Op->EndLoc = S;
570573 Op->IsPPC64 = IsPPC64;
571574 return Op;
572575 }
573576
574 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
575 PPCOperand *Op = new PPCOperand(Immediate);
577 static std::unique_ptr CreateImm(int64_t Val, SMLoc S, SMLoc E,
578 bool IsPPC64) {
579 auto Op = make_unique(Immediate);
576580 Op->Imm.Val = Val;
577581 Op->StartLoc = S;
578582 Op->EndLoc = E;
580584 return Op;
581585 }
582586
583 static PPCOperand *CreateExpr(const MCExpr *Val,
584 SMLoc S, SMLoc E, bool IsPPC64) {
585 PPCOperand *Op = new PPCOperand(Expression);
587 static std::unique_ptr CreateExpr(const MCExpr *Val, SMLoc S,
588 SMLoc E, bool IsPPC64) {
589 auto Op = make_unique(Expression);
586590 Op->Expr.Val = Val;
587591 Op->Expr.CRVal = EvaluateCRExpr(Val);
588592 Op->StartLoc = S;
591595 return Op;
592596 }
593597
594 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
595 SMLoc S, SMLoc E, bool IsPPC64) {
596 PPCOperand *Op = new PPCOperand(TLSRegister);
598 static std::unique_ptr
599 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
600 auto Op = make_unique(TLSRegister);
597601 Op->TLSReg.Sym = Sym;
598602 Op->StartLoc = S;
599603 Op->EndLoc = E;
601605 return Op;
602606 }
603607
604 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
605 SMLoc S, SMLoc E, bool IsPPC64) {
608 static std::unique_ptr
609 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
606610 if (const MCConstantExpr *CE = dyn_cast(Val))
607611 return CreateImm(CE->getValue(), S, E, IsPPC64);
608612
633637 }
634638 }
635639
636
637 void PPCAsmParser::
638 ProcessInstruction(MCInst &Inst,
639 const SmallVectorImpl &Operands) {
640 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
641 const OperandVector &Operands) {
640642 int Opcode = Inst.getOpcode();
641643 switch (Opcode) {
642644 case PPC::LAx: {
916918 }
917919 }
918920
919 bool PPCAsmParser::
920 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
921 SmallVectorImpl &Operands,
922 MCStreamer &Out, unsigned &ErrorInfo,
923 bool MatchingInlineAsm) {
921 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
922 OperandVector &Operands,
923 MCStreamer &Out, unsigned &ErrorInfo,
924 bool MatchingInlineAsm) {
924925 MCInst Inst;
925926
926927 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
941942 if (ErrorInfo >= Operands.size())
942943 return Error(IDLoc, "too few operands for instruction");
943944
944 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
945 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
945946 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
946947 }
947948
12151216 /// ParseOperand
12161217 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
12171218 /// rNN for MachO.
1218 bool PPCAsmParser::
1219 ParseOperand(SmallVectorImpl &Operands) {
1219 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
12201220 SMLoc S = Parser.getTok().getLoc();
12211221 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
12221222 const MCExpr *EVal;
1223 PPCOperand *Op;
12241223
12251224 // Attempt to parse the next token as an immediate
12261225 switch (getLexer().getKind()) {
12321231 int64_t IntVal;
12331232 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
12341233 Parser.Lex(); // Eat the identifier token.
1235 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1236 Operands.push_back(Op);
1234 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
12371235 return false;
12381236 }
12391237 return Error(S, "invalid register name");
12481246 int64_t IntVal;
12491247 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
12501248 Parser.Lex(); // Eat the identifier token.
1251 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1252 Operands.push_back(Op);
1249 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
12531250 return false;
12541251 }
12551252 }
12711268 }
12721269
12731270 // Push the parsed operand into the list of operands
1274 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1275 Operands.push_back(Op);
1271 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
12761272
12771273 // Check whether this is a TLS call expression
12781274 bool TLSCall = false;
12911287 E = Parser.getTok().getLoc();
12921288 Parser.Lex(); // Eat the ')'.
12931289
1294 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1295 Operands.push_back(Op);
1290 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
12961291 }
12971292
12981293 // Otherwise, check for D-form memory operands
13391334 E = Parser.getTok().getLoc();
13401335 Parser.Lex(); // Eat the ')'.
13411336
1342 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1343 Operands.push_back(Op);
1337 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
13441338 }
13451339
13461340 return false;
13471341 }
13481342
13491343 /// Parse an instruction mnemonic followed by its operands.
1350 bool PPCAsmParser::
1351 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1352 SmallVectorImpl &Operands) {
1344 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1345 SMLoc NameLoc, OperandVector &Operands) {
13531346 // The first operand is the token for the instruction name.
13541347 // If the next character is a '+' or '-', we need to add it to the
13551348 // instruction name, to match what TableGen is doing.
15531546
15541547 // Define this matcher function after the auto-generated include so we
15551548 // have the match class enum definitions.
1556 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1549 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
15571550 unsigned Kind) {
15581551 // If the kind is a token for a literal immediate, check if our asm
15591552 // operand matches. This is for InstAliases which have a fixed-value
15671560 default: return Match_InvalidOperand;
15681561 }
15691562
1570 PPCOperand *Op = static_cast(AsmOp);
1571 if (Op->isImm() && Op->getImm() == ImmVal)
1563 PPCOperand &Op = static_cast(AsmOp);
1564 if (Op.isImm() && Op.getImm() == ImmVal)
15721565 return Match_Success;
15731566
15741567 return Match_InvalidOperand;
4646
4747 // public interface of the MCTargetAsmParser.
4848 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
49 SmallVectorImpl &Operands,
50 MCStreamer &Out, unsigned &ErrorInfo,
49 OperandVector &Operands, MCStreamer &Out,
50 unsigned &ErrorInfo,
5151 bool MatchingInlineAsm) override;
5252 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
5353 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
54 SMLoc NameLoc,
55 SmallVectorImpl &Operands) override;
54 SMLoc NameLoc, OperandVector &Operands) override;
5655 bool ParseDirective(AsmToken DirectiveID) override;
5756
58 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
57 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
5958 unsigned Kind) override;
6059
6160 // Custom parse functions for Sparc specific operands.
61 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
62
63 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
64
6265 OperandMatchResultTy
63 parseMEMOperand(SmallVectorImpl &Operands);
64
65 OperandMatchResultTy
66 parseOperand(SmallVectorImpl &Operands,
67 StringRef Name);
68
69 OperandMatchResultTy
70 parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
71
72 OperandMatchResultTy
73 parseBranchModifiers(SmallVectorImpl &Operands);
66 parseSparcAsmOperand(std::unique_ptr &Operand,
67 bool isCall = false);
68
69 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
7470
7571 // returns true if Tok is matched to a register and returns register in RegNo.
7672 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
152148
153149 SMLoc StartLoc, EndLoc;
154150
155 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
156
157151 struct Token {
158152 const char *Data;
159153 unsigned Length;
181175 struct MemOp Mem;
182176 };
183177 public:
178 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
179
184180 bool isToken() const override { return Kind == k_Token; }
185181 bool isReg() const override { return Kind == k_Register; }
186182 bool isImm() const override { return Kind == k_Immediate; }
290286 addExpr(Inst, Expr);
291287 }
292288
293 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
294 SparcOperand *Op = new SparcOperand(k_Token);
289 static std::unique_ptr CreateToken(StringRef Str, SMLoc S) {
290 auto Op = make_unique(k_Token);
295291 Op->Tok.Data = Str.data();
296292 Op->Tok.Length = Str.size();
297293 Op->StartLoc = S;
299295 return Op;
300296 }
301297
302 static SparcOperand *CreateReg(unsigned RegNum,
303 unsigned Kind,
304 SMLoc S, SMLoc E) {
305 SparcOperand *Op = new SparcOperand(k_Register);
298 static std::unique_ptr CreateReg(unsigned RegNum, unsigned Kind,
299 SMLoc S, SMLoc E) {
300 auto Op = make_unique(k_Register);
306301 Op->Reg.RegNum = RegNum;
307302 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
308303 Op->StartLoc = S;
310305 return Op;
311306 }
312307
313 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
314 SparcOperand *Op = new SparcOperand(k_Immediate);
308 static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S,
309 SMLoc E) {
310 auto Op = make_unique(k_Immediate);
315311 Op->Imm.Val = Val;
316312 Op->StartLoc = S;
317313 Op->EndLoc = E;
318314 return Op;
319315 }
320316
321 static SparcOperand *MorphToDoubleReg(SparcOperand *Op) {
322 unsigned Reg = Op->getReg();
323 assert(Op->Reg.Kind == rk_FloatReg);
317 static bool MorphToDoubleReg(SparcOperand &Op) {
318 unsigned Reg = Op.getReg();
319 assert(Op.Reg.Kind == rk_FloatReg);
324320 unsigned regIdx = Reg - Sparc::F0;
325321 if (regIdx % 2 || regIdx > 31)
326 return nullptr;
327 Op->Reg.RegNum = DoubleRegs[regIdx / 2];
328 Op->Reg.Kind = rk_DoubleReg;
329 return Op;
330 }
331
332 static SparcOperand *MorphToQuadReg(SparcOperand *Op) {
333 unsigned Reg = Op->getReg();
322 return false;
323 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
324 Op.Reg.Kind = rk_DoubleReg;
325 return true;
326 }
327
328 static bool MorphToQuadReg(SparcOperand &Op) {
329 unsigned Reg = Op.getReg();
334330 unsigned regIdx = 0;
335 switch (Op->Reg.Kind) {
331 switch (Op.Reg.Kind) {
336332 default: assert(0 && "Unexpected register kind!");
337333 case rk_FloatReg:
338334 regIdx = Reg - Sparc::F0;
339335 if (regIdx % 4 || regIdx > 31)
340 return nullptr;
336 return false;
341337 Reg = QuadFPRegs[regIdx / 4];
342338 break;
343339 case rk_DoubleReg:
344340 regIdx = Reg - Sparc::D0;
345341 if (regIdx % 2 || regIdx > 31)
346 return nullptr;
342 return false;
347343 Reg = QuadFPRegs[regIdx / 2];
348344 break;
349345 }
350 Op->Reg.RegNum = Reg;
351 Op->Reg.Kind = rk_QuadReg;
352 return Op;
353 }
354
355 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) {
346 Op.Reg.RegNum = Reg;
347 Op.Reg.Kind = rk_QuadReg;
348 return true;
349 }
350
351 static std::unique_ptr
352 MorphToMEMrr(unsigned Base, std::unique_ptr Op) {
356353 unsigned offsetReg = Op->getReg();
357354 Op->Kind = k_MemoryReg;
358355 Op->Mem.Base = Base;
361358 return Op;
362359 }
363360
364 static SparcOperand *CreateMEMri(unsigned Base,
365 const MCExpr *Off,
366 SMLoc S, SMLoc E) {
367 SparcOperand *Op = new SparcOperand(k_MemoryImm);
361 static std::unique_ptr
362 CreateMEMri(unsigned Base, const MCExpr *Off, SMLoc S, SMLoc E) {
363 auto Op = make_unique(k_MemoryImm);
368364 Op->Mem.Base = Base;
369365 Op->Mem.OffsetReg = 0;
370366 Op->Mem.Off = Off;
373369 return Op;
374370 }
375371
376 static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) {
372 static std::unique_ptr
373 MorphToMEMri(unsigned Base, std::unique_ptr Op) {
377374 const MCExpr *Imm = Op->getImm();
378375 Op->Kind = k_MemoryImm;
379376 Op->Mem.Base = Base;
385382
386383 } // end namespace
387384
388 bool SparcAsmParser::
389 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
390 SmallVectorImpl &Operands,
391 MCStreamer &Out, unsigned &ErrorInfo,
392 bool MatchingInlineAsm) {
385 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
386 OperandVector &Operands,
387 MCStreamer &Out,
388 unsigned &ErrorInfo,
389 bool MatchingInlineAsm) {
393390 MCInst Inst;
394391 SmallVector Instructions;
395392 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
414411 if (ErrorInfo >= Operands.size())
415412 return Error(IDLoc, "too few operands for instruction");
416413
417 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
414 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
418415 if (ErrorLoc == SMLoc())
419416 ErrorLoc = IDLoc;
420417 }
449446 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
450447 unsigned VariantID);
451448
452 bool SparcAsmParser::
453 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
454 SMLoc NameLoc,
455 SmallVectorImpl &Operands)
456 {
449 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
450 StringRef Name, SMLoc NameLoc,
451 OperandVector &Operands) {
457452
458453 // First operand in MCInst is instruction mnemonic.
459454 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
547542 return false;
548543 }
549544
550 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
551 parseMEMOperand(SmallVectorImpl &Operands)
552 {
545 SparcAsmParser::OperandMatchResultTy
546 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
553547
554548 SMLoc S, E;
555549 unsigned BaseReg = 0;
574568 break;
575569 }
576570
577 SparcOperand *Offset = nullptr;
571 std::unique_ptr Offset;
578572 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
579573 if (ResTy != MatchOperand_Success || !Offset)
580574 return MatchOperand_NoMatch;
581575
582 Offset = (Offset->isImm()
583 ? SparcOperand::MorphToMEMri(BaseReg, Offset)
584 : SparcOperand::MorphToMEMrr(BaseReg, Offset));
585
586 Operands.push_back(Offset);
576 Operands.push_back(
577 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
578 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
579
587580 return MatchOperand_Success;
588581 }
589582
590 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
591 parseOperand(SmallVectorImpl &Operands,
592 StringRef Mnemonic)
593 {
583 SparcAsmParser::OperandMatchResultTy
584 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
594585
595586 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
596587
636627 return MatchOperand_Success;
637628 }
638629
639 SparcOperand *Op = nullptr;
630 std::unique_ptr Op;
640631
641632 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
642633 if (ResTy != MatchOperand_Success || !Op)
643634 return MatchOperand_ParseFail;
644635
645636 // Push the parsed operand into the list of operands
646 Operands.push_back(Op);
637 Operands.push_back(std::move(Op));
647638
648639 return MatchOperand_Success;
649640