llvm.org GIT mirror llvm / c4a2469
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. Merged from r182600 Author: Tom Stellard <thomas.stellard@amd.com> Date: Thu May 23 18:26:42 2013 +0000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@185868 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 7 years ago
2 changed file(s) with 31 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
115115 const MachineOperand &MO = *I;
116116 if (!MO.isReg())
117117 continue;
118 if (MO.isDef())
119 DstMI = MO.getReg();
118 if (MO.isDef()) {
119 unsigned Reg = MO.getReg();
120 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
121 DstMI = Reg;
122 else
123 DstMI = TRI.getMatchingSuperReg(Reg,
124 TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
125 &AMDGPU::R600_Reg128RegClass);
126 }
120127 if (MO.isUse()) {
121128 unsigned Reg = MO.getReg();
122129 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; This test is for a scheduler bug where VTX_READ instructions that used
3 ; the result of another VTX_READ instruction were being grouped in the
4 ; same fetch clasue.
5
6 ; CHECK: @test
7 ; CHECK: Fetch clause
8 ; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40
9 ; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44
10 ; CHECK: Fetch clause
11 ; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
12 ; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
13 define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) {
14 entry:
15 %0 = load i32 addrspace(1)* %in0, align 4
16 %1 = load i32 addrspace(1)* %in1, align 4
17 %cmp.i = icmp slt i32 %0, %1
18 %cond.i = select i1 %cmp.i, i32 %0, i32 %1
19 store i32 %cond.i, i32 addrspace(1)* %out, align 4
20 ret void
21 }