llvm.org GIT mirror llvm / c476ed9
remove JIT support from the Alpha backend. The JIT will be moving to MC, and the Alpha backend isn't MCized yet. Approved by Andrew. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119051 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 8 years ago
11 changed file(s) with 5 addition(s) and 609 deletion(s). Raw diff Collapse all Expand all
387387 CXX.Flags += -fPIC
388388 CPP.BaseFlags += -fPIC
389389 endif
390 endif
391
392 ifeq ($(ARCH),Alpha)
390
393391 LD.Flags += -Wl,--no-relax
394392 endif
395393
479479 Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
480480 PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
481481 x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
482 Alpha) AC_SUBST(TARGET_HAS_JIT,1) ;;
482 Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
483483 ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
484484 Mips) AC_SUBST(TARGET_HAS_JIT,0) ;;
485485 XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
48494849 ;;
48504850 x86_64) TARGET_HAS_JIT=1
48514851 ;;
4852 Alpha) TARGET_HAS_JIT=1
4852 Alpha) TARGET_HAS_JIT=0
48534853 ;;
48544854 ARM) TARGET_HAS_JIT=1
48554855 ;;
+0
-222
lib/Target/Alpha/AlphaCodeEmitter.cpp less more
None //===-- Alpha/AlphaCodeEmitter.cpp - Convert Alpha code to machine code ---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the pass that transforms the Alpha machine instructions
10 // into relocatable machine code.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "alpha-emitter"
15 #include "AlphaTargetMachine.h"
16 #include "AlphaRelocations.h"
17 #include "Alpha.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/JITCodeEmitter.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 using namespace llvm;
28
29 namespace {
30 class AlphaCodeEmitter : public MachineFunctionPass {
31 JITCodeEmitter &MCE;
32 const AlphaInstrInfo *II;
33 public:
34 static char ID;
35
36 AlphaCodeEmitter(JITCodeEmitter &mce) : MachineFunctionPass(ID),
37 MCE(mce) {}
38
39 /// getBinaryCodeForInstr - This function, generated by the
40 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
41 /// machine instructions.
42
43 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
44
45 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
46
47 unsigned getMachineOpValue(const MachineInstr &MI,
48 const MachineOperand &MO) const;
49
50 bool runOnMachineFunction(MachineFunction &MF);
51
52 virtual const char *getPassName() const {
53 return "Alpha Machine Code Emitter";
54 }
55
56 private:
57 void emitBasicBlock(MachineBasicBlock &MBB);
58 };
59 }
60
61 char AlphaCodeEmitter::ID = 0;
62
63
64 /// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha
65 /// code to the specified MCE object.
66
67 FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM,
68 JITCodeEmitter &JCE) {
69 return new AlphaCodeEmitter(JCE);
70 }
71
72 bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
73 II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
74
75 do {
76 MCE.startFunction(MF);
77 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
78 emitBasicBlock(*I);
79 } while (MCE.finishFunction(MF));
80
81 return false;
82 }
83
84 void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
85 MCE.StartMachineBasicBlock(&MBB);
86 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
87 I != E; ++I) {
88 const MachineInstr &MI = *I;
89 MCE.processDebugLoc(MI.getDebugLoc(), true);
90 switch(MI.getOpcode()) {
91 default:
92 MCE.emitWordLE(getBinaryCodeForInstr(*I));
93 break;
94 case Alpha::ALTENT:
95 case Alpha::PCLABEL:
96 case Alpha::MEMLABEL:
97 case TargetOpcode::IMPLICIT_DEF:
98 case TargetOpcode::KILL:
99 break; //skip these
100 }
101 MCE.processDebugLoc(MI.getDebugLoc(), false);
102 }
103 }
104
105 static unsigned getAlphaRegNumber(unsigned Reg) {
106 switch (Reg) {
107 case Alpha::R0 : case Alpha::F0 : return 0;
108 case Alpha::R1 : case Alpha::F1 : return 1;
109 case Alpha::R2 : case Alpha::F2 : return 2;
110 case Alpha::R3 : case Alpha::F3 : return 3;
111 case Alpha::R4 : case Alpha::F4 : return 4;
112 case Alpha::R5 : case Alpha::F5 : return 5;
113 case Alpha::R6 : case Alpha::F6 : return 6;
114 case Alpha::R7 : case Alpha::F7 : return 7;
115 case Alpha::R8 : case Alpha::F8 : return 8;
116 case Alpha::R9 : case Alpha::F9 : return 9;
117 case Alpha::R10 : case Alpha::F10 : return 10;
118 case Alpha::R11 : case Alpha::F11 : return 11;
119 case Alpha::R12 : case Alpha::F12 : return 12;
120 case Alpha::R13 : case Alpha::F13 : return 13;
121 case Alpha::R14 : case Alpha::F14 : return 14;
122 case Alpha::R15 : case Alpha::F15 : return 15;
123 case Alpha::R16 : case Alpha::F16 : return 16;
124 case Alpha::R17 : case Alpha::F17 : return 17;
125 case Alpha::R18 : case Alpha::F18 : return 18;
126 case Alpha::R19 : case Alpha::F19 : return 19;
127 case Alpha::R20 : case Alpha::F20 : return 20;
128 case Alpha::R21 : case Alpha::F21 : return 21;
129 case Alpha::R22 : case Alpha::F22 : return 22;
130 case Alpha::R23 : case Alpha::F23 : return 23;
131 case Alpha::R24 : case Alpha::F24 : return 24;
132 case Alpha::R25 : case Alpha::F25 : return 25;
133 case Alpha::R26 : case Alpha::F26 : return 26;
134 case Alpha::R27 : case Alpha::F27 : return 27;
135 case Alpha::R28 : case Alpha::F28 : return 28;
136 case Alpha::R29 : case Alpha::F29 : return 29;
137 case Alpha::R30 : case Alpha::F30 : return 30;
138 case Alpha::R31 : case Alpha::F31 : return 31;
139 default:
140 llvm_unreachable("Unhandled reg");
141 }
142 }
143
144 unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
145 const MachineOperand &MO) const {
146
147 unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
148 // or things that get fixed up later by the JIT.
149
150 if (MO.isReg()) {
151 rv = getAlphaRegNumber(MO.getReg());
152 } else if (MO.isImm()) {
153 rv = MO.getImm();
154 } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
155 DEBUG(errs() << MO << " is a relocated op for " << MI << "\n");
156 unsigned Reloc = 0;
157 int Offset = 0;
158 bool useGOT = false;
159 switch (MI.getOpcode()) {
160 case Alpha::BSR:
161 Reloc = Alpha::reloc_bsr;
162 break;
163 case Alpha::LDLr:
164 case Alpha::LDQr:
165 case Alpha::LDBUr:
166 case Alpha::LDWUr:
167 case Alpha::LDSr:
168 case Alpha::LDTr:
169 case Alpha::LDAr:
170 case Alpha::STQr:
171 case Alpha::STLr:
172 case Alpha::STWr:
173 case Alpha::STBr:
174 case Alpha::STSr:
175 case Alpha::STTr:
176 Reloc = Alpha::reloc_gprellow;
177 break;
178 case Alpha::LDAHr:
179 Reloc = Alpha::reloc_gprelhigh;
180 break;
181 case Alpha::LDQl:
182 Reloc = Alpha::reloc_literal;
183 useGOT = true;
184 break;
185 case Alpha::LDAg:
186 case Alpha::LDAHg:
187 Reloc = Alpha::reloc_gpdist;
188 Offset = MI.getOperand(3).getImm();
189 break;
190 default:
191 llvm_unreachable("unknown relocatable instruction");
192 }
193 if (MO.isGlobal())
194 MCE.addRelocation(MachineRelocation::getGV(
195 MCE.getCurrentPCOffset(),
196 Reloc,
197 const_cast(MO.getGlobal()),
198 Offset,
199 isa(MO.getGlobal()),
200 useGOT));
201 else if (MO.isSymbol())
202 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
203 Reloc, MO.getSymbolName(),
204 Offset, true));
205 else
206 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
207 Reloc, MO.getIndex(), Offset));
208 } else if (MO.isMBB()) {
209 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
210 Alpha::reloc_bsr, MO.getMBB()));
211 } else {
212 #ifndef NDEBUG
213 errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
214 #endif
215 llvm_unreachable(0);
216 }
217
218 return rv;
219 }
220
221 #include "AlphaGenCodeEmitter.inc"
+0
-310
lib/Target/Alpha/AlphaJITInfo.cpp less more
None //===-- AlphaJITInfo.cpp - Implement the JIT interfaces for the Alpha ---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the JIT interfaces for the Alpha target.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "jit"
14 #include "AlphaJITInfo.h"
15 #include "AlphaRelocations.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/JITCodeEmitter.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include
22 using namespace llvm;
23
24 #define BUILD_OFormatI(Op, RA, LIT, FUN, RC) \
25 ((Op << 26) | (RA << 21) | (LIT << 13) | (1 << 12) | (FUN << 5) | (RC))
26 #define BUILD_OFormat(Op, RA, RB, FUN, RC) \
27 ((Op << 26) | (RA << 21) | (RB << 16) | (FUN << 5) | (RC))
28
29 #define BUILD_LDA(RD, RS, IMM16) \
30 ((0x08 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
31 #define BUILD_LDAH(RD, RS, IMM16) \
32 ((0x09 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
33
34 #define BUILD_LDQ(RD, RS, IMM16) \
35 ((0x29 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF))
36
37 #define BUILD_JMP(RD, RS, IMM16) \
38 ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x00 << 14) | ((IMM16) & 0x3FFF))
39 #define BUILD_JSR(RD, RS, IMM16) \
40 ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x01 << 14) | ((IMM16) & 0x3FFF))
41
42 #define BUILD_SLLi(RD, RS, IMM8) \
43 (BUILD_OFormatI(0x12, RS, IMM8, 0x39, RD))
44
45 #define BUILD_ORi(RD, RS, IMM8) \
46 (BUILD_OFormatI(0x11, RS, IMM8, 0x20, RD))
47
48 #define BUILD_OR(RD, RS, RT) \
49 (BUILD_OFormat(0x11, RS, RT, 0x20, RD))
50
51
52
53 static void EmitBranchToAt(void *At, void *To) {
54 unsigned long Fn = (unsigned long)To;
55
56 unsigned *AtI = (unsigned*)At;
57
58 AtI[0] = BUILD_OR(0, 27, 27);
59
60 DEBUG(errs() << "Stub targeting " << To << "\n");
61
62 for (int x = 1; x <= 8; ++x) {
63 AtI[2*x - 1] = BUILD_SLLi(27,27,8);
64 unsigned d = (Fn >> (64 - 8 * x)) & 0x00FF;
65 //DEBUG(errs() << "outputing " << hex << d << dec << "\n");
66 AtI[2*x] = BUILD_ORi(27, 27, d);
67 }
68 AtI[17] = BUILD_JMP(31,27,0); //jump, preserving ra, and setting pv
69 AtI[18] = 0x00FFFFFF; //mark this as a stub
70 }
71
72 void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
73 //FIXME
74 llvm_unreachable(0);
75 }
76
77 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
78 //static AlphaJITInfo* AlphaJTI;
79
80 extern "C" {
81 #ifdef __alpha
82
83 void AlphaCompilationCallbackC(long* oldpv, void* CameFromStub)
84 {
85 void* Target = JITCompilerFunction(CameFromStub);
86
87 //rewrite the stub to an unconditional branch
88 if (((unsigned*)CameFromStub)[18] == 0x00FFFFFF) {
89 DEBUG(errs() << "Came from a stub, rewriting\n");
90 EmitBranchToAt(CameFromStub, Target);
91 } else {
92 DEBUG(errs() << "confused, didn't come from stub at " << CameFromStub
93 << " old jump vector " << oldpv
94 << " new jump vector " << Target << "\n");
95 }
96
97 //Change pv to new Target
98 *oldpv = (long)Target;
99 }
100
101 void AlphaCompilationCallback(void);
102
103 asm(
104 ".text\n"
105 ".globl AlphaCompilationCallbackC\n"
106 ".align 4\n"
107 ".globl AlphaCompilationCallback\n"
108 ".ent AlphaCompilationCallback\n"
109 "AlphaCompilationCallback:\n"
110 // //get JIT's GOT
111 "ldgp $29, 0($27)\n"
112 //Save args, callee saved, and perhaps others?
113 //args: $16-$21 $f16-$f21 (12)
114 //callee: $9-$14 $f2-$f9 (14)
115 //others: fp:$15 ra:$26 pv:$27 (3)
116 "lda $30, -232($30)\n"
117 "stq $16, 0($30)\n"
118 "stq $17, 8($30)\n"
119 "stq $18, 16($30)\n"
120 "stq $19, 24($30)\n"
121 "stq $20, 32($30)\n"
122 "stq $21, 40($30)\n"
123 "stt $f16, 48($30)\n"
124 "stt $f17, 56($30)\n"
125 "stt $f18, 64($30)\n"
126 "stt $f19, 72($30)\n"
127 "stt $f20, 80($30)\n"
128 "stt $f21, 88($30)\n"
129 "stq $9, 96($30)\n"
130 "stq $10, 104($30)\n"
131 "stq $11, 112($30)\n"
132 "stq $12, 120($30)\n"
133 "stq $13, 128($30)\n"
134 "stq $14, 136($30)\n"
135 "stt $f2, 144($30)\n"
136 "stt $f3, 152($30)\n"
137 "stt $f4, 160($30)\n"
138 "stt $f5, 168($30)\n"
139 "stt $f6, 176($30)\n"
140 "stt $f7, 184($30)\n"
141 "stt $f8, 192($30)\n"
142 "stt $f9, 200($30)\n"
143 "stq $15, 208($30)\n"
144 "stq $26, 216($30)\n"
145 "stq $27, 224($30)\n"
146
147 "addq $30, 224, $16\n" //pass the addr of saved pv as the first arg
148 "bis $0, $0, $17\n" //pass the roughly stub addr in second arg
149 "jsr $26, AlphaCompilationCallbackC\n" //call without saving ra
150
151 "ldq $16, 0($30)\n"
152 "ldq $17, 8($30)\n"
153 "ldq $18, 16($30)\n"
154 "ldq $19, 24($30)\n"
155 "ldq $20, 32($30)\n"
156 "ldq $21, 40($30)\n"
157 "ldt $f16, 48($30)\n"
158 "ldt $f17, 56($30)\n"
159 "ldt $f18, 64($30)\n"
160 "ldt $f19, 72($30)\n"
161 "ldt $f20, 80($30)\n"
162 "ldt $f21, 88($30)\n"
163 "ldq $9, 96($30)\n"
164 "ldq $10, 104($30)\n"
165 "ldq $11, 112($30)\n"
166 "ldq $12, 120($30)\n"
167 "ldq $13, 128($30)\n"
168 "ldq $14, 136($30)\n"
169 "ldt $f2, 144($30)\n"
170 "ldt $f3, 152($30)\n"
171 "ldt $f4, 160($30)\n"
172 "ldt $f5, 168($30)\n"
173 "ldt $f6, 176($30)\n"
174 "ldt $f7, 184($30)\n"
175 "ldt $f8, 192($30)\n"
176 "ldt $f9, 200($30)\n"
177 "ldq $15, 208($30)\n"
178 "ldq $26, 216($30)\n"
179 "ldq $27, 224($30)\n" //this was updated in the callback with the target
180
181 "lda $30, 232($30)\n" //restore sp
182 "jmp $31, ($27)\n" //jump to the new function
183 ".end AlphaCompilationCallback\n"
184 );
185 #else
186 void AlphaCompilationCallback() {
187 llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
188 }
189 #endif
190 }
191
192 TargetJITInfo::StubLayout AlphaJITInfo::getStubLayout() {
193 // The stub contains 19 4-byte instructions, aligned at 4 bytes:
194 // R0 = R27
195 // 8 x "R27 <<= 8; R27 |= 8-bits-of-Target" == 16 instructions
196 // JMP R27
197 // Magic number so the compilation callback can recognize the stub.
198 StubLayout Result = {19 * 4, 4};
199 return Result;
200 }
201
202 void *AlphaJITInfo::emitFunctionStub(const Function* F, void *Fn,
203 JITCodeEmitter &JCE) {
204 //assert(Fn == AlphaCompilationCallback && "Where are you going?\n");
205 //Do things in a stupid slow way!
206 void* Addr = (void*)(intptr_t)JCE.getCurrentPCValue();
207 for (int x = 0; x < 19; ++ x)
208 JCE.emitWordLE(0);
209 EmitBranchToAt(Addr, Fn);
210 DEBUG(errs() << "Emitting Stub to " << Fn << " at [" << Addr << "]\n");
211 return Addr;
212 }
213
214 TargetJITInfo::LazyResolverFn
215 AlphaJITInfo::getLazyResolverFunction(JITCompilerFn F) {
216 JITCompilerFunction = F;
217 // setZerothGOTEntry((void*)AlphaCompilationCallback);
218 return AlphaCompilationCallback;
219 }
220
221 //These describe LDAx
222 static const int IMM_LOW = -32768;
223 static const int IMM_HIGH = 32767;
224 static const int IMM_MULT = 65536;
225
226 static long getUpper16(long l)
227 {
228 long y = l / IMM_MULT;
229 if (l % IMM_MULT > IMM_HIGH)
230 ++y;
231 if (l % IMM_MULT < IMM_LOW)
232 --y;
233 assert((short)y == y && "displacement out of range");
234 return y;
235 }
236
237 static long getLower16(long l)
238 {
239 long h = getUpper16(l);
240 long y = l - h * IMM_MULT;
241 assert(y == (short)y && "Displacement out of range");
242 return y;
243 }
244
245 void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
246 unsigned NumRelocs, unsigned char* GOTBase) {
247 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
248 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
249 long idx = 0;
250 bool doCommon = true;
251 switch ((Alpha::RelocationType)MR->getRelocationType()) {
252 default: llvm_unreachable("Unknown relocation type!");
253 case Alpha::reloc_literal:
254 //This is a LDQl
255 idx = MR->getGOTIndex();
256 DEBUG(errs() << "Literal relocation to slot " << idx);
257 idx = (idx - GOToffset) * 8;
258 DEBUG(errs() << " offset " << idx << "\n");
259 break;
260 case Alpha::reloc_gprellow:
261 idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
262 idx = getLower16(idx);
263 DEBUG(errs() << "gprellow relocation offset " << idx << "\n");
264 DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
265 << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
266 break;
267 case Alpha::reloc_gprelhigh:
268 idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
269 idx = getUpper16(idx);
270 DEBUG(errs() << "gprelhigh relocation offset " << idx << "\n");
271 DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
272 << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
273 break;
274 case Alpha::reloc_gpdist:
275 switch (*RelocPos >> 26) {
276 case 0x09: //LDAH
277 idx = &GOTBase[GOToffset * 8] - (unsigned char*)RelocPos;
278 idx = getUpper16(idx);
279 DEBUG(errs() << "LDAH: " << idx << "\n");
280 //add the relocation to the map
281 gpdistmap[std::make_pair(Function, MR->getConstantVal())] = RelocPos;
282 break;
283 case 0x08: //LDA
284 assert(gpdistmap[std::make_pair(Function, MR->getConstantVal())] &&
285 "LDAg without seeing LDAHg");
286 idx = &GOTBase[GOToffset * 8] -
287 (unsigned char*)gpdistmap[std::make_pair(Function, MR->getConstantVal())];
288 idx = getLower16(idx);
289 DEBUG(errs() << "LDA: " << idx << "\n");
290 break;
291 default:
292 llvm_unreachable("Cannot handle gpdist yet");
293 }
294 break;
295 case Alpha::reloc_bsr: {
296 idx = (((unsigned char*)MR->getResultPointer() -
297 (unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun
298 *RelocPos |= (idx & ((1 << 21)-1));
299 doCommon = false;
300 break;
301 }
302 }
303 if (doCommon) {
304 short x = (short)idx;
305 assert(x == idx);
306 *(short*)RelocPos = x;
307 }
308 }
309 }
+0
-53
lib/Target/Alpha/AlphaJITInfo.h less more
None //===- AlphaJITInfo.h - Alpha impl. of the JIT interface ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Alpha implementation of the TargetJITInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHA_JITINFO_H
14 #define ALPHA_JITINFO_H
15
16 #include "llvm/Target/TargetJITInfo.h"
17 #include
18
19 namespace llvm {
20 class TargetMachine;
21
22 class AlphaJITInfo : public TargetJITInfo {
23 protected:
24 TargetMachine &TM;
25
26 //because gpdist are paired and relative to the pc of the first inst,
27 //we need to have some state
28 std::map, void*> gpdistmap;
29 public:
30 explicit AlphaJITInfo(TargetMachine &tm) : TM(tm)
31 { useGOT = true; }
32
33 virtual StubLayout getStubLayout();
34 virtual void *emitFunctionStub(const Function* F, void *Fn,
35 JITCodeEmitter &JCE);
36 virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
37 virtual void relocate(void *Function, MachineRelocation *MR,
38 unsigned NumRelocs, unsigned char* GOTBase);
39
40 /// replaceMachineCodeForFunction - Make it so that calling the function
41 /// whose machine code is at OLD turns into a call to NEW, perhaps by
42 /// overwriting OLD with a branch to NEW. This is used for self-modifying
43 /// code.
44 ///
45 virtual void replaceMachineCodeForFunction(void *Old, void *New);
46 private:
47 static const unsigned GOToffset = 4096;
48
49 };
50 }
51
52 #endif
1010 //===----------------------------------------------------------------------===//
1111
1212 #include "Alpha.h"
13 #include "AlphaJITInfo.h"
1413 #include "AlphaMCAsmInfo.h"
1514 #include "AlphaTargetMachine.h"
1615 #include "llvm/PassManager.h"
2928 : LLVMTargetMachine(T, TT),
3029 DataLayout("e-f128:128:128-n64"),
3130 FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
32 JITInfo(*this),
3331 Subtarget(TT, FS),
3432 TLInfo(*this),
3533 TSInfo(*this) {
5351 PM.add(createAlphaLLRPPass(*this));
5452 return false;
5553 }
56 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
57 CodeGenOpt::Level OptLevel,
58 JITCodeEmitter &JCE) {
59 PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
60 return false;
61 }
1717 #include "llvm/Target/TargetData.h"
1818 #include "llvm/Target/TargetFrameInfo.h"
1919 #include "AlphaInstrInfo.h"
20 #include "AlphaJITInfo.h"
2120 #include "AlphaISelLowering.h"
2221 #include "AlphaSelectionDAGInfo.h"
2322 #include "AlphaSubtarget.h"
3029 const TargetData DataLayout; // Calculates type size & alignment
3130 AlphaInstrInfo InstrInfo;
3231 TargetFrameInfo FrameInfo;
33 AlphaJITInfo JITInfo;
3432 AlphaSubtarget Subtarget;
3533 AlphaTargetLowering TLInfo;
3634 AlphaSelectionDAGInfo TSInfo;
5250 return &TSInfo;
5351 }
5452 virtual const TargetData *getTargetData() const { return &DataLayout; }
55 virtual AlphaJITInfo* getJITInfo() {
56 return &JITInfo;
57 }
5853
5954 // Pass Pipeline Configuration
6055 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
6156 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
62 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
63 JITCodeEmitter &JCE);
6457 };
6558
6659 } // end namespace llvm
9090 return;
9191
9292 case MachineOperand::MO_Immediate:
93 llvm_unreachable("printOp() does not handle immediate values");
93 assert(0 && "printOp() does not handle immediate values");
9494 return;
9595
9696 case MachineOperand::MO_MachineBasicBlock:
44 tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
55 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
66 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
7 tablegen(AlphaGenCodeEmitter.inc -gen-emitter)
87 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
98 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
109 tablegen(AlphaGenCallingConv.inc -gen-callingconv)
1615 AlphaInstrInfo.cpp
1716 AlphaISelDAGToDAG.cpp
1817 AlphaISelLowering.cpp
19 AlphaJITInfo.cpp
2018 AlphaLLRP.cpp
2119 AlphaMCAsmInfo.cpp
2220 AlphaRegisterInfo.cpp
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
1515 AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
16 AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \
16 AlphaGenInstrInfo.inc \
1717 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1818 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
1919