llvm.org GIT mirror llvm / c44fff4
Keep the killed/dead sets sorted, so that "KillsRegister" can do a quick binary search to test for membership. This speeds up LLC a bit more on KC++, e.g. on itanium from 16.6974s to 14.8272s, PPC from 11.4926s to 10.7089s and X86 from 10.8128s to 9.7943s, with no difference in generated code (like all of the RA patches). With these changes, isel is the slowest pass for PPC/X86, but linscan+live intervals is still > 50% of the compile time for itanium. More work could be done, but this is the last for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22993 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 15 years ago
1 changed file(s) with 26 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
144144
145145 /// KillsRegister - Return true if the specified instruction kills the
146146 /// specified register.
147 bool KillsRegister(MachineInstr *MI, unsigned Reg) const {
148 std::map >::const_iterator I =
149 RegistersKilled.find(MI);
150 if (I != RegistersKilled.end())
151 for (std::vector::const_iterator CI = I->second.begin(),
152 E = I->second.end(); CI != E; ++CI)
153 if (*CI == Reg) return true;
154 return false;
155 }
156
147 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
148
157149 killed_iterator dead_begin(MachineInstr *MI) {
158150 return getDeadDefsVector(MI).begin();
159151 }
168160
169161 /// RegisterDefIsDead - Return true if the specified instruction defines the
170162 /// specified register, but that definition is dead.
171 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
172 std::map >::const_iterator I =
173 RegistersDead.find(MI);
174 if (I != RegistersDead.end())
175 for (std::vector::const_iterator CI = I->second.begin(),
176 E = I->second.end(); CI != E; ++CI)
177 if (*CI == Reg) return true;
178 return false;
179 }
180
163 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
164
181165 //===--------------------------------------------------------------------===//
182166 // API to update live variable information
183167
192176 /// instruction.
193177 ///
194178 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
195 RegistersKilled.insert(std::make_pair(MI, IncomingReg));
179 std::vector &V = RegistersKilled[MI];
180 // Insert in a sorted order.
181 if (V.empty() || IncomingReg > V.back()) {
182 V.push_back(IncomingReg);
183 } else {
184 std::vector::iterator I = V.begin();
185 for (; *I < IncomingReg; ++I)
186 /*empty*/;
187 if (*I != IncomingReg) // Don't insert duplicates.
188 V.insert(I, IncomingReg);
189 }
196190 getVarInfo(IncomingReg).Kills.push_back(MI);
197191 }
198192
225219 /// register is dead after being used by the specified instruction.
226220 ///
227221 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
228 RegistersDead.insert(std::make_pair(MI, IncomingReg));
222 std::vector &V = RegistersDead[MI];
223 // Insert in a sorted order.
224 if (V.empty() || IncomingReg > V.back()) {
225 V.push_back(IncomingReg);
226 } else {
227 std::vector::iterator I = V.begin();
228 for (; *I < IncomingReg; ++I)
229 /*empty*/;
230 if (*I != IncomingReg) // Don't insert duplicates.
231 V.insert(I, IncomingReg);
232 }
229233 getVarInfo(IncomingReg).Kills.push_back(MI);
230234 }
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