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Add 64-bit shift instructions. SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
4 changed file(s) with 100 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 //===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains instruction definitions and patterns needed for 64-bit
10 // code generation on SPARC v9.
11 //
12 // Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
13 // also be used in 32-bit code running on a SPARC v9 CPU.
14 //
15 //===----------------------------------------------------------------------===//
16
17 let Predicates = [Is64Bit] in {
18 // The same integer registers are used for i32 and i64 values.
19 // When registers hold i32 values, the high bits are don't care.
20 // This give us free trunc and anyext.
21 def : Pat<(i64 (anyext i32:$val)), (COPY $val)>;
22 def : Pat<(i32 (trunc i64:$val)), (COPY $val)>;
23
24 } // Predicates = [Is64Bit]
25
26
27 //===----------------------------------------------------------------------===//
28 // 64-bit Shift Instructions.
29 //===----------------------------------------------------------------------===//
30 //
31 // The 32-bit shift instructions are still available. The left shift srl
32 // instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
33 //
34 // The srl instructions only shift the low 32 bits and clear the high 32 bits.
35 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
36
37 let Predicates = [Is64Bit] in {
38
39 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
40 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
41
42 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
43 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
44 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
45
46 } // Predicates = [Is64Bit]
110110 let Inst{4-0} = rs2;
111111 }
112112
113 // Shift by register rs2.
114 class F3_Sr opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
115 string asmstr, list pattern> : F3 {
116 bit x = xVal; // 1 for 64-bit shifts.
117 bits<5> rs2;
113118
119 let op = opVal;
120 let op3 = op3val;
121
122 let Inst{13} = 0; // i field = 0
123 let Inst{12} = x; // extended registers.
124 let Inst{4-0} = rs2;
125 }
126
127 // Shift by immediate.
128 class F3_Si opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
129 string asmstr, list pattern> : F3 {
130 bit x = xVal; // 1 for 64-bit shifts.
131 bits<6> shcnt; // shcnt32 / shcnt64.
132
133 let op = opVal;
134 let op3 = op3val;
135
136 let Inst{13} = 1; // i field = 1
137 let Inst{12} = x; // extended registers.
138 let Inst{5-0} = shcnt;
139 }
140
141 // Define rr and ri shift instructions with patterns.
142 multiclass F3_S Op3Val, bit XVal, SDNode OpNode,
143 ValueType VT, RegisterClass RC> {
144 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, RC:$rs2),
145 !strconcat(OpcStr, " $rs, $rs2, $rd"),
146 [(set VT:$rd, (OpNode VT:$rs, VT:$rs2))]>;
147 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, unknown:$shcnt),
148 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
149 [(set VT:$rd, (OpNode VT:$rs, (VT imm:$shcnt)))]>;
150 }
815815 // zextload bool -> zextload byte
816816 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
817817 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
818
819 include "SparcInstr64Bit.td"
44 define i64 @ret2(i64 %a, i64 %b) {
55 ret i64 %b
66 }
7
8 ; CHECK: shl_imm
9 ; CHECK: sllx %i0, 7, %i0
10 define i64 @shl_imm(i64 %a) {
11 %x = shl i64 %a, 7
12 ret i64 %x
13 }
14
15 ; CHECK: sra_reg
16 ; CHECK: srax %i0, %i1, %i0
17 define i64 @sra_reg(i64 %a, i64 %b) {
18 %x = ashr i64 %a, %b
19 ret i64 %x
20 }