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[ARM] Add patterns for bitreverse intrinsic on MVE BITREVERSE can use the VBRSR which will reverse and right shift. Shifting right by 0 will just reverse the bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372001 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Cruickshank 1 year, 8 days ago
3 changed file(s) with 64 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
262262 setOperationAction(ISD::MSTORE, VT, Legal);
263263 setOperationAction(ISD::CTLZ, VT, Legal);
264264 setOperationAction(ISD::CTTZ, VT, Expand);
265 setOperationAction(ISD::BITREVERSE, VT, Legal);
265266
266267 // No native support for these.
267268 setOperationAction(ISD::UDIV, VT, Expand);
37703770 def MVE_VBRSR8 : MVE_VBRSR<"vbrsr", "8", 0b00>;
37713771 def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
37723772 def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
3773
3774 let Predicates = [HasMVEInt] in {
3775 def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
3776 (v16i8 ( MVE_VBRSR8 (v16i8 MQPR:$val1), (t2MOVi (i32 8)) ))>;
3777
3778 def : Pat<(v4i32 ( bitreverse (v4i32 MQPR:$val1))),
3779 (v4i32 ( MVE_VBRSR32 (v4i32 MQPR:$val1), (t2MOVi (i32 32)) ))>;
3780
3781 def : Pat<(v8i16 ( bitreverse (v8i16 MQPR:$val1))),
3782 (v8i16 ( MVE_VBRSR16 (v8i16 MQPR:$val1), (t2MOVi (i32 16)) ))>;
3783 }
37733784
37743785 class MVE_VMUL_qr_int
37753786 bits<2> size, list pattern=[]>
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
2
3 define arm_aapcs_vfpcc <2 x i64> @brv_2i64_t(<2 x i64> %src){
4 ; CHECK-LABEL: brv_2i64_t:
5 ; CHECK: @ %bb.0: @ %entry
6 ; CHECK-NEXT: vrev64.8 q1, q0
7 ; CHECK-NEXT: movs r0, #8
8 ; CHECK-NEXT: vbrsr.8 q0, q1, r0
9 ; CHECK-NEXT: bx lr
10 entry:
11 %0 = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %src)
12 ret <2 x i64> %0
13 }
14
15 define arm_aapcs_vfpcc <4 x i32> @brv_4i32_t(<4 x i32> %src){
16 ; CHECK-LABEL: brv_4i32_t:
17 ; CHECK: @ %bb.0: @ %entry
18 ; CHECK-NEXT: movs r0, #32
19 ; CHECK-NEXT: vbrsr.32 q0, q0, r0
20 ; CHECK-NEXT: bx lr
21 entry:
22 %0 = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %src)
23 ret <4 x i32> %0
24 }
25
26 define arm_aapcs_vfpcc <8 x i16> @brv_8i16_t(<8 x i16> %src){
27 ; CHECK-LABEL: brv_8i16_t:
28 ; CHECK: @ %bb.0: @ %entry
29 ; CHECK-NEXT: movs r0, #16
30 ; CHECK-NEXT: vbrsr.16 q0, q0, r0
31 ; CHECK-NEXT: bx lr
32 entry:
33 %0 = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %src)
34 ret <8 x i16> %0
35 }
36
37 define arm_aapcs_vfpcc <16 x i8> @brv_16i8_t(<16 x i8> %src){
38 ; CHECK-LABEL: brv_16i8_t:
39 ; CHECK: @ %bb.0: @ %entry
40 ; CHECK-NEXT: movs r0, #8
41 ; CHECK-NEXT: vbrsr.8 q0, q0, r0
42 ; CHECK-NEXT: bx lr
43 entry:
44 %0 = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %src)
45 ret <16 x i8> %0
46 }
47
48 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>)
49 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
50 declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>)
51 declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)