llvm.org GIT mirror llvm / c3b0540
Update this significantly, mention subtarget and isel generation support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23760 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 14 years ago
1 changed file(s) with 34 addition(s) and 35 deletion(s). Raw diff Collapse all Expand all
6767 implement the following:

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  • Describe the register set
  • 70
  • Describe the register set.
  • 7171
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  • Create a TableGen description of
  • 7373 the register set and register classes
    7474
  • Implement a subclass of
  • 7575 href="CodeGenerator.html#mregisterinfo">MRegisterInfo
    7676
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  • Describe the instruction set
  • 77
  • Describe the instruction set.
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  • Create a TableGen description of
  • 8080 the instruction set
    8181
  • Implement a subclass of
  • 8282 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo
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  • Describe the target machine
  • 84
  • Describe the target machine.
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  • Create a TableGen description of
  • 8787 the target that describes the pointer size and references the instruction
    103103 is the description of your target to appear in -help
    104104 listing.
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  • Implement the assembly printer for the architecture. Usually, if you have
  • 107 described the instruction set with the assembly printer generator in mind, that
    108 step can be almost automated.
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    You also need to write an instruction selector for your platform. The

    112 recommended method is the
    113 href="CodeGenerator.html#instselect">pattern-matching instruction selector,
    114 examples of which you can see in other targets:
    115 lib/Target/*/*ISelPattern.cpp. The former method for writing
    116 instruction selectors (not recommended for new targets) is evident in
    117 lib/Target/*/*ISelSimple.cpp, which are InstVisitor-based
    118 translators, generating code for an LLVM instruction at a time. Creating an
    119 instruction selector is perhaps the most time-consuming part of creating a
    120 back-end.

    121
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    To create a JIT for your platform:

    123
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  • Create a subclass of
  • 126 href="CodeGenerator.html#targetjitinfo">TargetJITInfo
    127
  • Create a machine code emitter that will be used to emit binary code
  • 128 directly into memory, given MachineInstrs
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    Note that lib/target/Skeleton is a clean skeleton for a new target,

    132 so you might want to start with that and adapt it for your target, and if you
    133 are wondering how things are done, peek in the X86 or PowerPC target.

    134
    135

    The Skeleton target is non-functional but provides the basic building blocks

    136 you will need for your endeavor.

    137
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  • Implement the assembly printer for the architecture.
  • 107
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  • Define all of the assembly strings for your target, adding them to the
  • 109 instructions in your *InstrInfo.td file.
    110
  • Implement the llvm::AsmPrinter interface.
  • 111
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  • Implement an instruction selector for the architecture.
  • 114
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  • The recommended method is the
  • 116 pattern-matching DAG-to-DAG instruction selector (for example, see
    117 the PowerPC backend in PPCISelDAGtoDAG.cpp). Parts of instruction
    118 selector creation can be performed by adding patterns to the instructions
    119 in your .td file.
    120
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  • Optionally, add subtarget support.
  • 123
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  • If your target has multiple subtargets (e.g. variants with different
  • 125 capabilities), implement the llvm::TargetSubtarget interface
    126 for your architecture. This allows you to add -mcpu= and
    127 -mattr= options.
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  • Optionally, add JIT support.
  • 130
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  • Create a subclass of
  • 132 href="CodeGenerator.html#targetjitinfo">TargetJITInfo
    133
  • Create a machine code emitter that will be used to emit binary code
  • 134 directly into memory, given MachineInstrs
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