llvm.org GIT mirror llvm / c347f0a
ARM: Remove implicit iterator conversions, NFC Remove remaining implicit conversions from MachineInstrBundleIterator to MachineInstr* from the ARM backend. In most cases, I made them less attractive by preferring MachineInstr& or using a ranged-based for loop. Once all the backends are fixed I'll make the operator explicit so that this doesn't bitrot back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274920 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan P. N. Exon Smith 4 years ago
8 changed file(s) with 125 addition(s) and 136 deletion(s). Raw diff Collapse all Expand all
692692
693693 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
694694 MI != ME;) {
695 Modified |= runOnInstruction(MI++);
695 Modified |= runOnInstruction(&*MI++);
696696 }
697697
698698 }
359359 if (AllowModify) {
360360 MachineBasicBlock::iterator DI = std::next(I);
361361 while (DI != MBB.end()) {
362 MachineInstr *InstToDelete = DI;
362 MachineInstr &InstToDelete = *DI;
363363 ++DI;
364 InstToDelete->eraseFromParent();
364 InstToDelete.eraseFromParent();
365365 }
366366 }
367367 }
12261226
12271227 /// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
12281228 /// depending on whether the result is used.
1229 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MBBI) const {
1229 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
12301230 bool isThumb1 = Subtarget.isThumb1Only();
12311231 bool isThumb2 = Subtarget.isThumb2();
12321232 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
12331233
1234 MachineInstr *MI = MBBI;
12351234 DebugLoc dl = MI->getDebugLoc();
12361235 MachineBasicBlock *BB = MI->getParent();
12371236
12741273 STM.addReg(Reg, RegState::Kill);
12751274 }
12761275
1277 BB->erase(MBBI);
1276 BB->erase(MI);
12781277 }
12791278
12801279
721721 /// information about the sizes of each block and the locations of all
722722 /// the jump tables.
723723 void ARMConstantIslands::scanFunctionJumpTables() {
724 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
725 MBBI != E; ++MBBI) {
726 MachineBasicBlock &MBB = *MBBI;
727
728 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
729 I != E; ++I)
730 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
731 T2JumpTables.push_back(I);
724 for (MachineBasicBlock &MBB : *MF) {
725 for (MachineInstr &I : MBB)
726 if (I.isBranch() && I.getOpcode() == ARM::t2BR_JT)
727 T2JumpTables.push_back(&I);
732728 }
733729 }
734730
755751 adjustBBOffsetsAfter(&MF->front());
756752
757753 // Now go back through the instructions and build up our data structures.
758 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
759 MBBI != E; ++MBBI) {
760 MachineBasicBlock &MBB = *MBBI;
761
754 for (MachineBasicBlock &MBB : *MF) {
762755 // If this block doesn't fall through into the next MBB, then this is
763756 // 'water' that a constant pool island could be placed.
764757 if (!BBHasFallthrough(&MBB))
765758 WaterList.push_back(&MBB);
766759
767 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
768 I != E; ++I) {
769 if (I->isDebugValue())
760 for (MachineInstr &I : MBB) {
761 if (I.isDebugValue())
770762 continue;
771763
772 unsigned Opc = I->getOpcode();
773 if (I->isBranch()) {
764 unsigned Opc = I.getOpcode();
765 if (I.isBranch()) {
774766 bool isCond = false;
775767 unsigned Bits = 0;
776768 unsigned Scale = 1;
779771 default:
780772 continue; // Ignore other JT branches
781773 case ARM::t2BR_JT:
782 T2JumpTables.push_back(I);
774 T2JumpTables.push_back(&I);
783775 continue; // Does not get an entry in ImmBranches
784776 case ARM::Bcc:
785777 isCond = true;
813805
814806 // Record this immediate branch.
815807 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
816 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
808 ImmBranches.push_back(ImmBranch(&I, MaxOffs, isCond, UOpc));
817809 }
818810
819811 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
820 PushPopMIs.push_back(I);
812 PushPopMIs.push_back(&I);
821813
822814 if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
823815 Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
825817 continue;
826818
827819 // Scan the instructions for constant pool operands.
828 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
829 if (I->getOperand(op).isCPI() || I->getOperand(op).isJTI()) {
820 for (unsigned op = 0, e = I.getNumOperands(); op != e; ++op)
821 if (I.getOperand(op).isCPI() || I.getOperand(op).isJTI()) {
830822 // We found one. The addressing mode tells us the max displacement
831823 // from the PC that this instruction permits.
832824
885877 }
886878
887879 // Remember that this is a user of a CP entry.
888 unsigned CPI = I->getOperand(op).getIndex();
889 if (I->getOperand(op).isJTI()) {
880 unsigned CPI = I.getOperand(op).getIndex();
881 if (I.getOperand(op).isJTI()) {
890882 JumpTableUserIndices.insert(std::make_pair(CPI, CPUsers.size()));
891883 CPI = JumpTableEntryIndices[CPI];
892884 }
893885
894886 MachineInstr *CPEMI = CPEMIs[CPI];
895887 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
896 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
888 CPUsers.push_back(CPUser(&I, CPEMI, MaxOffs, NegOk, IsSoImm));
897889
898890 // Increment corresponding CPEntry reference count.
899891 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
916908 BBI.Unalign = 0;
917909 BBI.PostAlign = 0;
918910
919 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
920 ++I) {
921 BBI.Size += TII->GetInstSizeInBytes(*I);
911 for (MachineInstr &I : *MBB) {
912 BBI.Size += TII->GetInstSizeInBytes(I);
922913 // For inline asm, GetInstSizeInBytes returns a conservative estimate.
923914 // The actual size may be smaller, but still a multiple of the instr size.
924 if (I->isInlineAsm())
915 if (I.isInlineAsm())
925916 BBI.Unalign = isThumb ? 1 : 2;
926917 // Also consider instructions that may be shrunk later.
927 else if (isThumb && mayOptimizeThumb2Instruction(I))
918 else if (isThumb && mayOptimizeThumb2Instruction(&I))
928919 BBI.Unalign = 1;
929920 }
930921
14711462 Offset < BaseInsertOffset;
14721463 Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
14731464 assert(MI != UserMBB->end() && "Fell off end of block");
1474 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
1465 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
14751466 CPUser &U = CPUsers[CPUIndex];
14761467 if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
14771468 // Shift intertion point by one unit of alignment so it is within reach.
14881479
14891480 // Remember the last IT instruction.
14901481 if (MI->getOpcode() == ARM::t2IT)
1491 LastIT = MI;
1482 LastIT = &*MI;
14921483 }
14931484
14941485 --MI;
15051496 DEBUG(unsigned PredReg;
15061497 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
15071498
1508 NewMBB = splitBlockBeforeInstr(MI);
1499 NewMBB = splitBlockBeforeInstr(&*MI);
15091500 }
15101501
15111502 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
16261617 CPEBB->setAlignment(0);
16271618 } else
16281619 // Entries are sorted by descending alignment, so realign from the front.
1629 CPEBB->setAlignment(getCPELogAlign(CPEBB->begin()));
1620 CPEBB->setAlignment(getCPELogAlign(&*CPEBB->begin()));
16301621
16311622 adjustBBOffsetsAfter(CPEBB);
16321623 // An island has only one predecessor BB and one successor BB. Check if
10321032 .addReg(JumpTarget.getReg(), RegState::Kill);
10331033 }
10341034
1035 MachineInstr *NewMI = std::prev(MBBI);
1035 auto NewMI = std::prev(MBBI);
10361036 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
10371037 NewMI->addOperand(MBBI->getOperand(i));
10381038
9797 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
9898 }
9999
100 static bool isCSRestore(MachineInstr *MI,
101 const ARMBaseInstrInfo &TII,
100 static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
102101 const MCPhysReg *CSRegs) {
103102 // Integer spill area is handled with "pop".
104 if (isPopOpcode(MI->getOpcode())) {
103 if (isPopOpcode(MI.getOpcode())) {
105104 // The first two operands are predicates. The last two are
106105 // imp-def and imp-use of SP. Check everything in between.
107 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
108 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
106 for (int i = 5, e = MI.getNumOperands(); i != e; ++i)
107 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
109108 return false;
110109 return true;
111110 }
112 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
113 MI->getOpcode() == ARM::LDR_POST_REG ||
114 MI->getOpcode() == ARM::t2LDR_POST) &&
115 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
116 MI->getOperand(1).getReg() == ARM::SP)
111 if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
112 MI.getOpcode() == ARM::LDR_POST_REG ||
113 MI.getOpcode() == ARM::t2LDR_POST) &&
114 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
115 MI.getOperand(1).getReg() == ARM::SP)
117116 return true;
118117
119118 return false;
142141 MIFlags, Pred, PredReg);
143142 }
144143
145 static int sizeOfSPAdjustment(const MachineInstr *MI) {
144 static int sizeOfSPAdjustment(const MachineInstr &MI) {
146145 int RegSize;
147 switch (MI->getOpcode()) {
146 switch (MI.getOpcode()) {
148147 case ARM::VSTMDDB_UPD:
149148 RegSize = 8;
150149 break;
162161 int count = 0;
163162 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
164163 // pred) so the list starts at 4.
165 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
164 for (int i = MI.getNumOperands() - 1; i >= 4; --i)
166165 count += RegSize;
167166 return count;
168167 }
414413 // .cfi_offset operations will reflect that.
415414 if (DPRGapSize) {
416415 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
417 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize))
416 if (tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))
418417 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
419418 else {
420419 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
428427 // Since vpush register list cannot have gaps, there may be multiple vpush
429428 // instructions in the prologue.
430429 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
431 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI));
430 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
432431 LastPush = MBBI++;
433432 }
434433 }
492491 if (NumBytes) {
493492 // Adjust SP after all the callee-save spills.
494493 if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
495 tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes))
494 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
496495 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
497496 else {
498497 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
520519 // that push.
521520 if (HasFP) {
522521 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
523 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push);
522 unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
524523 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
525524 dl, TII, FramePtr, ARM::SP,
526525 PushSize + FramePtrOffsetInPush,
725724 if (MBBI != MBB.begin()) {
726725 do {
727726 --MBBI;
728 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
729 if (!isCSRestore(MBBI, TII, CSRegs))
727 } while (MBBI != MBB.begin() && isCSRestore(*MBBI, TII, CSRegs));
728 if (!isCSRestore(*MBBI, TII, CSRegs))
730729 ++MBBI;
731730 }
732731
772771 .addReg(FramePtr));
773772 }
774773 } else if (NumBytes &&
775 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
776 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
774 !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
775 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
777776
778777 // Increment past our save areas.
779778 if (AFI->getDPRCalleeSavedAreaSize()) {
17471746 // If we have alloca, convert as follows:
17481747 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
17491748 // ADJCALLSTACKUP -> add, sp, sp, amount
1750 MachineInstr *Old = I;
1751 DebugLoc dl = Old->getDebugLoc();
1752 unsigned Amount = Old->getOperand(0).getImm();
1749 MachineInstr &Old = *I;
1750 DebugLoc dl = Old.getDebugLoc();
1751 unsigned Amount = Old.getOperand(0).getImm();
17531752 if (Amount != 0) {
17541753 // We need to keep the stack aligned properly. To do this, we round the
17551754 // amount of space needed for the outgoing arguments up to the next
17621761 bool isARM = !AFI->isThumbFunction();
17631762
17641763 // Replace the pseudo instruction with a new instruction...
1765 unsigned Opc = Old->getOpcode();
1766 int PIdx = Old->findFirstPredOperandIdx();
1767 ARMCC::CondCodes Pred = (PIdx == -1)
1768 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1764 unsigned Opc = Old.getOpcode();
1765 int PIdx = Old.findFirstPredOperandIdx();
1766 ARMCC::CondCodes Pred =
1767 (PIdx == -1) ? ARMCC::AL
1768 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
17691769 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
17701770 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1771 unsigned PredReg = Old->getOperand(2).getReg();
1771 unsigned PredReg = Old.getOperand(2).getReg();
17721772 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
17731773 Pred, PredReg);
17741774 } else {
17751775 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1776 unsigned PredReg = Old->getOperand(3).getReg();
1776 unsigned PredReg = Old.getOperand(3).getReg();
17771777 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
17781778 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
17791779 Pred, PredReg);
80988098
80998099 // Add epilogue to handle BytesLeft.
81008100 BB = exitMBB;
8101 MachineInstr *StartOfExit = exitMBB->begin();
8101 auto StartOfExit = exitMBB->begin();
81028102
81038103 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
81048104 // [destOut] = STRB_POST(scratch, destLoop, 1)
114114 MachineInstr *MI;
115115 int Offset; ///< Load/Store offset.
116116 unsigned Position; ///< Position as counted from end of basic block.
117 MemOpQueueEntry(MachineInstr *MI, int Offset, unsigned Position)
118 : MI(MI), Offset(Offset), Position(Position) {}
117 MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
118 : MI(&MI), Offset(Offset), Position(Position) {}
119119 };
120120 typedef SmallVector MemOpQueue;
121121
173173
174174 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-load-store-opt", ARM_LOAD_STORE_OPT_NAME, false, false)
175175
176 static bool definesCPSR(const MachineInstr *MI) {
177 for (const auto &MO : MI->operands()) {
176 static bool definesCPSR(const MachineInstr &MI) {
177 for (const auto &MO : MI.operands()) {
178178 if (!MO.isReg())
179179 continue;
180180 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
186186 return false;
187187 }
188188
189 static int getMemoryOpOffset(const MachineInstr *MI) {
190 unsigned Opcode = MI->getOpcode();
189 static int getMemoryOpOffset(const MachineInstr &MI) {
190 unsigned Opcode = MI.getOpcode();
191191 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
192 unsigned NumOperands = MI->getDesc().getNumOperands();
193 unsigned OffField = MI->getOperand(NumOperands-3).getImm();
192 unsigned NumOperands = MI.getDesc().getNumOperands();
193 unsigned OffField = MI.getOperand(NumOperands - 3).getImm();
194194
195195 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
196196 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
490490 InsertSub = true;
491491
492492 } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) &&
493 !definesCPSR(MBBI)) {
493 !definesCPSR(*MBBI)) {
494494 // SUBS/ADDS using this register, with a dead def of the CPSR.
495495 // Merge it with the update; if the merged offset is too large,
496496 // insert a new sub instead.
514514 InsertSub = true;
515515 }
516516
517 } else if (definesCPSR(MBBI) || MBBI->isCall() || MBBI->isBranch()) {
517 } else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
518518 // Since SUBS sets the condition flags, we can't place the base reset
519519 // after an instruction that has a live CPSR def.
520520 // The base register might also contain an argument for a function call.
853853 MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
854854 iterator InsertBefore = std::next(iterator(LatestMI));
855855 MachineBasicBlock &MBB = *LatestMI->getParent();
856 unsigned Offset = getMemoryOpOffset(First);
856 unsigned Offset = getMemoryOpOffset(*First);
857857 unsigned Base = getLoadStoreBaseOp(*First).getReg();
858858 bool BaseKill = LatestMI->killsRegister(Base);
859859 unsigned PredReg = 0;
11451145 MIPredReg != PredReg)
11461146 return 0;
11471147
1148 if (CheckCPSRDef && definesCPSR(&MI))
1148 if (CheckCPSRDef && definesCPSR(MI))
11491149 return 0;
11501150 return MI.getOperand(2).getImm() * Scale;
11511151 }
16051605 bool BaseUndef = BaseOp.isUndef();
16061606 bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
16071607 bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
1608 int OffImm = getMemoryOpOffset(MI);
1608 int OffImm = getMemoryOpOffset(*MI);
16091609 unsigned PredReg = 0;
16101610 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
16111611
17141714 unsigned Base = getLoadStoreBaseOp(*MBBI).getReg();
17151715 unsigned PredReg = 0;
17161716 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1717 int Offset = getMemoryOpOffset(MBBI);
1717 int Offset = getMemoryOpOffset(*MBBI);
17181718 if (CurrBase == 0) {
17191719 // Start of a new chain.
17201720 CurrBase = Base;
17211721 CurrOpc = Opcode;
17221722 CurrPred = Pred;
1723 MemOps.push_back(MemOpQueueEntry(MBBI, Offset, Position));
1723 MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
17241724 continue;
17251725 }
17261726 // Note: No need to match PredReg in the next if.
17481748 if (!Overlap) {
17491749 // Check offset and sort memory operation into the current chain.
17501750 if (Offset > MemOps.back().Offset) {
1751 MemOps.push_back(MemOpQueueEntry(MBBI, Offset, Position));
1751 MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
17521752 continue;
17531753 } else {
17541754 MemOpQueue::iterator MI, ME;
17641764 }
17651765 }
17661766 if (MI != MemOps.end()) {
1767 MemOps.insert(MI, MemOpQueueEntry(MBBI, Offset, Position));
1767 MemOps.insert(MI, MemOpQueueEntry(*MBBI, Offset, Position));
17681768 continue;
17691769 }
17701770 }
17811781 MBBI->getOpcode() == ARM::t2STRDi8) {
17821782 // ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions
17831783 // remember them because we may still be able to merge add/sub into them.
1784 MergeBaseCandidates.push_back(MBBI);
1784 MergeBaseCandidates.push_back(&*MBBI);
17851785 }
17861786
17871787
18631863 // Ignore any DBG_VALUE instructions.
18641864 while (PrevI->isDebugValue() && PrevI != MBB.begin())
18651865 --PrevI;
1866 MachineInstr *PrevMI = PrevI;
1867 unsigned Opcode = PrevMI->getOpcode();
1866 MachineInstr &PrevMI = *PrevI;
1867 unsigned Opcode = PrevMI.getOpcode();
18681868 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
18691869 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
18701870 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
1871 MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
1871 MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
18721872 if (MO.getReg() != ARM::LR)
18731873 return false;
18741874 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
18751875 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
18761876 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
1877 PrevMI->setDesc(TII->get(NewOpc));
1877 PrevMI.setDesc(TII->get(NewOpc));
18781878 MO.setReg(ARM::PC);
1879 PrevMI->copyImplicitOps(*MBB.getParent(), *MBBI);
1879 PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
18801880 MBB.erase(MBBI);
18811881 return true;
18821882 }
20982098 return false;
20992099
21002100 // Then make sure the immediate offset fits.
2101 int OffImm = getMemoryOpOffset(Op0);
2101 int OffImm = getMemoryOpOffset(*Op0);
21022102 if (isT2) {
21032103 int Limit = (1 << 8) * Scale;
21042104 if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))
21342134 // Sort by offset (in reverse order).
21352135 std::sort(Ops.begin(), Ops.end(),
21362136 [](const MachineInstr *LHS, const MachineInstr *RHS) {
2137 int LOffset = getMemoryOpOffset(LHS);
2138 int ROffset = getMemoryOpOffset(RHS);
2139 assert(LHS == RHS || LOffset != ROffset);
2140 return LOffset > ROffset;
2141 });
2137 int LOffset = getMemoryOpOffset(*LHS);
2138 int ROffset = getMemoryOpOffset(*RHS);
2139 assert(LHS == RHS || LOffset != ROffset);
2140 return LOffset > ROffset;
2141 });
21422142
21432143 // The loads / stores of the same base are in order. Scan them from first to
21442144 // last and check for the following:
21702170 if (LastOpcode && LSMOpcode != LastOpcode)
21712171 break;
21722172
2173 int Offset = getMemoryOpOffset(Op);
2173 int Offset = getMemoryOpOffset(*Op);
21742174 unsigned Bytes = getLSMultipleTransferSize(Op);
21752175 if (LastBytes) {
21762176 if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
22052205 } else {
22062206 // This is the new location for the loads / stores.
22072207 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
2208 while (InsertPos != MBB->end()
2209 && (MemOps.count(InsertPos) || InsertPos->isDebugValue()))
2208 while (InsertPos != MBB->end() &&
2209 (MemOps.count(&*InsertPos) || InsertPos->isDebugValue()))
22102210 ++InsertPos;
22112211
22122212 // If we are moving a pair of loads / stores, see if it makes sense
23012301 MachineBasicBlock::iterator E = MBB->end();
23022302 while (MBBI != E) {
23032303 for (; MBBI != E; ++MBBI) {
2304 MachineInstr *MI = MBBI;
2305 if (MI->isCall() || MI->isTerminator()) {
2304 MachineInstr &MI = *MBBI;
2305 if (MI.isCall() || MI.isTerminator()) {
23062306 // Stop at barriers.
23072307 ++MBBI;
23082308 break;
23092309 }
23102310
2311 if (!MI->isDebugValue())
2312 MI2LocMap[MI] = ++Loc;
2313
2314 if (!isMemoryOp(*MI))
2311 if (!MI.isDebugValue())
2312 MI2LocMap[&MI] = ++Loc;
2313
2314 if (!isMemoryOp(MI))
23152315 continue;
23162316 unsigned PredReg = 0;
2317 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL)
2317 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
23182318 continue;
23192319
2320 int Opc = MI->getOpcode();
2320 int Opc = MI.getOpcode();
23212321 bool isLd = isLoadSingle(Opc);
2322 unsigned Base = MI->getOperand(1).getReg();
2322 unsigned Base = MI.getOperand(1).getReg();
23232323 int Offset = getMemoryOpOffset(MI);
23242324
23252325 bool StopHere = false;
23282328 Base2LdsMap.find(Base);
23292329 if (BI != Base2LdsMap.end()) {
23302330 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
2331 if (Offset == getMemoryOpOffset(BI->second[i])) {
2331 if (Offset == getMemoryOpOffset(*BI->second[i])) {
23322332 StopHere = true;
23332333 break;
23342334 }
23352335 }
23362336 if (!StopHere)
2337 BI->second.push_back(MI);
2337 BI->second.push_back(&MI);
23382338 } else {
2339 Base2LdsMap[Base].push_back(MI);
2339 Base2LdsMap[Base].push_back(&MI);
23402340 LdBases.push_back(Base);
23412341 }
23422342 } else {
23442344 Base2StsMap.find(Base);
23452345 if (BI != Base2StsMap.end()) {
23462346 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
2347 if (Offset == getMemoryOpOffset(BI->second[i])) {
2347 if (Offset == getMemoryOpOffset(*BI->second[i])) {
23482348 StopHere = true;
23492349 break;
23502350 }
23512351 }
23522352 if (!StopHere)
2353 BI->second.push_back(MI);
2353 BI->second.push_back(&MI);
23542354 } else {
2355 Base2StsMap[Base].push_back(MI);
2355 Base2StsMap[Base].push_back(&MI);
23562356 StBases.push_back(Base);
23572357 }
23582358 }
5858 // If we have alloca, convert as follows:
5959 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
6060 // ADJCALLSTACKUP -> add, sp, sp, amount
61 MachineInstr *Old = I;
62 DebugLoc dl = Old->getDebugLoc();
63 unsigned Amount = Old->getOperand(0).getImm();
61 MachineInstr &Old = *I;
62 DebugLoc dl = Old.getDebugLoc();
63 unsigned Amount = Old.getOperand(0).getImm();
6464 if (Amount != 0) {
6565 // We need to keep the stack aligned properly. To do this, we round the
6666 // amount of space needed for the outgoing arguments up to the next
6969 Amount = (Amount+Align-1)/Align*Align;
7070
7171 // Replace the pseudo instruction with a new instruction...
72 unsigned Opc = Old->getOpcode();
72 unsigned Opc = Old.getOpcode();
7373 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
7474 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
7575 } else {
187187
188188 int FramePtrOffsetInBlock = 0;
189189 unsigned adjustedGPRCS1Size = GPRCS1Size;
190 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
190 if (tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
191191 FramePtrOffsetInBlock = NumBytes;
192192 adjustedGPRCS1Size += NumBytes;
193193 NumBytes = 0;
302302 AFI->setShouldRestoreSPFromFP(true);
303303 }
304304
305 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
306 if (MI->getOpcode() == ARM::tLDRspi &&
307 MI->getOperand(1).isFI() &&
308 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
305 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
306 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
307 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
309308 return true;
310 else if (MI->getOpcode() == ARM::tPOP) {
309 else if (MI.getOpcode() == ARM::tPOP) {
311310 // The first two operands are predicates. The last two are
312311 // imp-def and imp-use of SP. Check everything in between.
313 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
314 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
312 for (int i = 2, e = MI.getNumOperands() - 2; i != e; ++i)
313 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
315314 return false;
316315 return true;
317316 }
344343 if (MBBI != MBB.begin()) {
345344 do
346345 --MBBI;
347 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
348 if (!isCSRestore(MBBI, CSRegs))
346 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
347 if (!isCSRestore(*MBBI, CSRegs))
349348 ++MBBI;
350349 }
351350
374373 .addReg(FramePtr));
375374 } else {
376375 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
377 &MBB.front() != MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
376 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
378377 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
379 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
378 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
380379 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
381 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
380 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
382381 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
383382 }
384383 }