llvm.org GIT mirror llvm / c3384c9
ARM Refactor VLD/VST spaced pair instructions. Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
6 changed file(s) with 92 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
115115 let ParserMatchClass = VecListFourDAsmOperand;
116116 }
117117 // Register list of two D registers spaced by 2 (two sequential Q registers).
118 def VecListTwoQAsmOperand : AsmOperandClass {
119 let Name = "VecListTwoQ";
118 def VecListDPairSpacedAsmOperand : AsmOperandClass {
119 let Name = "VecListDPairSpaced";
120120 let ParserMethod = "parseVectorList";
121121 let RenderMethod = "addVecListOperands";
122122 }
123 def VecListTwoQ : RegisterOperand {
124 let ParserMatchClass = VecListTwoQAsmOperand;
123 def VecListDPairSpaced : RegisterOperand {
124 let ParserMatchClass = VecListDPairSpacedAsmOperand;
125125 }
126126 // Register list of three D registers spaced by 2 (three Q registers).
127127 def VecListThreeQAsmOperand : AsmOperandClass {
802802 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo;
803803
804804 // ...with double-spaced registers
805 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
806 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
807 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
808 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
809 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
810 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
805 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
806 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
807 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
808 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
809 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
810 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
811811
812812 // VLD3 : Vector Load (multiple 3-element structures)
813813 class VLD3D op11_8, bits<4> op7_4, string Dt>
18091809 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo;
18101810
18111811 // ...with double-spaced registers
1812 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
1813 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
1814 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
1815 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
1816 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
1817 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
1812 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1813 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1814 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1815 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1816 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1817 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
18181818
18191819 // VST3 : Vector Store (multiple 3-element structures)
18201820 class VST3D op11_8, bits<4> op7_4, string Dt>
11051105 return VectorList.Count == 2;
11061106 }
11071107
1108 bool isVecListDPairSpaced() const {
1109 if (!isSingleSpacedVectorList()) return false;
1110 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1111 .contains(VectorList.RegNum));
1112 }
1113
11081114 bool isVecListThreeQ() const {
11091115 if (!isDoubleSpacedVectorList()) return false;
11101116 return VectorList.Count == 3;
29732979 switch (LaneKind) {
29742980 case NoLanes:
29752981 E = Parser.getTok().getLoc();
2976 // VLD1 wants a DPair register.
2977 // FIXME: Make the rest of the two-reg instructions want the same
2978 // thing.
29792982 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
29802983 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
29812984
31483151
31493152 switch (LaneKind) {
31503153 case NoLanes:
3151 if (Count == 2 && Spacing == 1)
3152 // VLD1 wants a DPair register.
3153 // FIXME: Make the rest of the two-reg instructions want the same
3154 // thing.
3155 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0,
3156 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3157
3154 // Non-lane two-register operands have been converted to the
3155 // composite register classes.
3156 if (Count == 2) {
3157 const MCRegisterClass *RC = (Spacing == 1) ?
3158 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3159 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3160 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3161 }
31583162
31593163 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
31603164 (Spacing == 2), S, E));
127127 uint64_t Address, const void *Decoder);
128128 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
129129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
131 unsigned RegNo, uint64_t Address,
132 const void *Decoder);
130133
131134 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
132135 uint64_t Address, const void *Decoder);
10031006 return MCDisassembler::Fail;
10041007
10051008 unsigned Register = DPairDecoderTable[RegNo];
1009 Inst.addOperand(MCOperand::CreateReg(Register));
1010 return MCDisassembler::Success;
1011 }
1012
1013 static const unsigned DPairSpacedDecoderTable[] = {
1014 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1015 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1016 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1017 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1018 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1019 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1020 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1021 ARM::D28_D30, ARM::D29_D31
1022 };
1023
1024 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
1025 unsigned RegNo,
1026 uint64_t Address,
1027 const void *Decoder) {
1028 if (RegNo > 29)
1029 return MCDisassembler::Fail;
1030
1031 unsigned Register = DPairSpacedDecoderTable[RegNo];
10061032 Inst.addOperand(MCOperand::CreateReg(Register));
10071033 return MCDisassembler::Success;
10081034 }
19962022 case ARM::VLD2d8wb_fixed:
19972023 case ARM::VLD2d8wb_register:
19982024 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2025 return MCDisassembler::Fail;
2026 break;
2027 case ARM::VLD2b16:
2028 case ARM::VLD2b32:
2029 case ARM::VLD2b8:
2030 case ARM::VLD2b16wb_fixed:
2031 case ARM::VLD2b16wb_register:
2032 case ARM::VLD2b32wb_fixed:
2033 case ARM::VLD2b32wb_register:
2034 case ARM::VLD2b8wb_fixed:
2035 case ARM::VLD2b8wb_register:
2036 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
19992037 return MCDisassembler::Fail;
20002038 break;
20012039 default:
23572395 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
23582396 return MCDisassembler::Fail;
23592397 break;
2398 case ARM::VST2b16:
2399 case ARM::VST2b32:
2400 case ARM::VST2b8:
2401 case ARM::VST2b16wb_fixed:
2402 case ARM::VST2b16wb_register:
2403 case ARM::VST2b32wb_fixed:
2404 case ARM::VST2b32wb_register:
2405 case ARM::VST2b8wb_fixed:
2406 case ARM::VST2b8wb_register:
2407 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2408 return MCDisassembler::Fail;
2409 break;
23602410 default:
23612411 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
23622412 return MCDisassembler::Fail;
10411041 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
10421042 }
10431043
1044 void ARMInstPrinter::printVectorListDPairSpaced(const MCInst *MI,
1045 unsigned OpNum,
1046 raw_ostream &O) {
1047 unsigned Reg = MI->getOperand(OpNum).getReg();
1048 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1049 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1050 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1051 }
1052
10441053 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
10451054 raw_ostream &O) {
10461055 // Normally, it's not safe to use register enum values directly with
134134 void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
135135 void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136136 void printVectorListDPair(const MCInst *MI, unsigned OpNum, raw_ostream &O);
137 void printVectorListDPairSpaced(const MCInst *MI, unsigned OpNum,
138 raw_ostream &O);
137139 void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
138140 void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
139141 void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
573573 REG("QQPR");
574574 REG("QQQQPR");
575575 REG("VecListOneD");
576 REG("VecListTwoD");
577576 REG("VecListDPair");
577 REG("VecListDPairSpaced");
578578 REG("VecListThreeD");
579579 REG("VecListFourD");
580 REG("VecListTwoQ");
581580 REG("VecListOneDAllLanes");
582581 REG("VecListTwoDAllLanes");
583582 REG("VecListTwoQAllLanes");