llvm.org GIT mirror llvm / c308148
[ARM/AArch64] Support FP16 +fp16fml instructions Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340013 91177308-0d34-0410-b5e6-96231b3b80d8 Bernard Ogden 1 year, 3 months ago
24 changed file(s) with 821 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
5959 AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
6060 AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
6161 AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")
62 AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml")
6263 AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
6364 AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
6465 AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
151151 ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr)
152152 ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
153153 ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
154 ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
154155 #undef ARM_ARCH_EXT_NAME
155156
156157 #ifndef ARM_HW_DIV_NAME
8787 AEK_DOTPROD = 1 << 14,
8888 AEK_SHA2 = 1 << 15,
8989 AEK_AES = 1 << 16,
90 AEK_FP16FML = 1 << 17,
9091 // Unsupported extensions.
9192 AEK_OS = 0x8000000,
9293 AEK_IWMMXT = 0x10000000,
177178 AEK_SHA3 = 1 << 14,
178179 AEK_SHA2 = 1 << 15,
179180 AEK_AES = 1 << 16,
181 AEK_FP16FML = 1 << 17,
180182 };
181183
182184 StringRef getCanonicalArchName(StringRef Arch);
233233 else
234234 Features.push_back("-dsp");
235235
236 if (Extensions & ARM::AEK_FP16FML)
237 Features.push_back("+fp16fml");
238 else
239 Features.push_back("-fp16fml");
240
236241 if (Extensions & ARM::AEK_RAS)
237242 Features.push_back("+ras");
238243 else
459464 Features.push_back("+crypto");
460465 if (Extensions & AArch64::AEK_DOTPROD)
461466 Features.push_back("+dotprod");
467 if (Extensions & AArch64::AEK_FP16FML)
468 Features.push_back("+fp16fml");
462469 if (Extensions & AArch64::AEK_FP16)
463470 Features.push_back("+fullfp16");
464471 if (Extensions & AArch64::AEK_PROFILE)
6969
7070 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
7171 "Full FP16", [FeatureFPARMv8]>;
72
73 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
74 "Enable FP16 FML instructions", [FeatureFullFP16]>;
7275
7376 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
7477 "Enable Statistical Profiling extension">;
47874787 let Inst{10} = 1;
47884788 let Inst{9-5} = Rn;
47894789 let Inst{4-0} = Rd;
4790 }
4791
4792 let Predicates = [HasNEON, HasFP16FML] in
4793 class BaseSIMDThreeSameMult size, string asm, string kind1,
4794 string kind2> :
4795 BaseSIMDThreeSameVector {
4796 let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
4797 let Inst{13} = b13;
47904798 }
47914799
47924800 class BaseSIMDThreeSameVectorDot
72547262 let Inst{11} = idx{1}; // H
72557263 }
72567264
7265 let Predicates = [HasNEON, HasFP16FML] in
7266 class BaseSIMDThreeSameMultIndex opc, string asm,
7267 string dst_kind, string lhs_kind,
7268 string rhs_kind> :
7269 BaseSIMDIndexedTied
7270 VectorIndexH, asm, "", dst_kind, lhs_kind,
7271 rhs_kind, []> {
7272 //idx = H:L:M
7273 bits<3> idx;
7274 let Inst{11} = idx{2}; // H
7275 let Inst{21} = idx{1}; // L
7276 let Inst{20} = idx{0}; // M
7277 }
7278
72577279 multiclass SIMDThreeSameVectorDotIndex
72587280 SDPatternOperator OpNode> {
72597281 def v8i8 : BaseSIMDThreeSameVectorDotIndex<0, U, asm, ".2s", ".8b", ".4b", V64,
4848 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
4949 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
5050 AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
51 def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">,
52 AssemblerPredicate<"FeatureFP16FML", "fp16fml">;
5153 def HasSPE : Predicate<"Subtarget->hasSPE()">,
5254 AssemblerPredicate<"FeatureSPE", "spe">;
5355 def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">,
32983300 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
32993301 int_aarch64_neon_sqsub>;
33003302
3303 // FP16FML
3304 def FMLAL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b001, "fmlal", ".2s", ".2h">;
3305 def FMLSL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b101, "fmlsl", ".2s", ".2h">;
3306 def FMLAL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b001, "fmlal", ".4s", ".4h">;
3307 def FMLSL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b101, "fmlsl", ".4s", ".4h">;
3308 def FMLAL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b001, "fmlal2", ".2s", ".2h">;
3309 def FMLSL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b101, "fmlsl2", ".2s", ".2h">;
3310 def FMLAL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b001, "fmlal2", ".4s", ".4h">;
3311 def FMLSL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b101, "fmlsl2", ".4s", ".4h">;
3312 def FMLALI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0000, "fmlal", ".2s", ".2h", ".h">;
3313 def FMLSLI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0100, "fmlsl", ".2s", ".2h", ".h">;
3314 def FMLALI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0000, "fmlal", ".4s", ".4h", ".h">;
3315 def FMLSLI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0100, "fmlsl", ".4s", ".4h", ".h">;
3316 def FMLALI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1000, "fmlal2", ".2s", ".2h", ".h">;
3317 def FMLSLI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1100, "fmlsl2", ".2s", ".2h", ".h">;
3318 def FMLALI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1000, "fmlal2", ".4s", ".4h", ".h">;
3319 def FMLSLI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1100, "fmlsl2", ".4s", ".4h", ".h">;
3320
33013321 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
33023322 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
33033323 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
7777 bool HasRDM = false;
7878 bool HasPerfMon = false;
7979 bool HasFullFP16 = false;
80 bool HasFP16FML = false;
8081 bool HasSPE = false;
8182
8283 // ARMv8.4 Crypto extensions
290291
291292 bool hasPerfMon() const { return HasPerfMon; }
292293 bool hasFullFP16() const { return HasFullFP16; }
294 bool hasFP16FML() const { return HasFP16FML; }
293295 bool hasSPE() const { return HasSPE; }
294296 bool hasLSLFast() const { return HasLSLFast; }
295297 bool hasSVE() const { return HasSVE; }
5959 "Enable full half-precision "
6060 "floating point",
6161 [FeatureFPARMv8]>;
62
63 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
64 "Enable full half-precision "
65 "floating point fml instructions",
66 [FeatureFullFP16]>;
6267
6368 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
6469 "Floating point unit supports "
25782578 let Inst{3-0} = Vm{3-0};
25792579 }
25802580
2581 // In Armv8.2-A, some NEON instructions are added that encode Vn and Vm
2582 // differently:
2583 // if Q == ‘1’ then UInt(N:Vn) else UInt(Vn:N);
2584 // if Q == ‘1’ then UInt(M:Vm) else UInt(Vm:M);
2585 // Class N3VCP8 above describes the Q=1 case, and this class the Q=0 case.
2586 class N3VCP8Q0 op24_23, bits<2> op21_20, bit op6, bit op4,
2587 dag oops, dag iops, InstrItinClass itin,
2588 string opc, string dt, string asm, string cstr, list pattern>
2589 : NeonInp {
2590 bits<5> Vd;
2591 bits<5> Vn;
2592 bits<5> Vm;
2593
2594 let DecoderNamespace = "VFPV8";
2595 // These have the same encodings in ARM and Thumb2
2596 let PostEncoderMethod = "";
2597
2598 let Inst{31-25} = 0b1111110;
2599 let Inst{24-23} = op24_23;
2600 let Inst{22} = Vd{4};
2601 let Inst{21-20} = op21_20;
2602 let Inst{19-16} = Vn{4-1};
2603 let Inst{15-12} = Vd{3-0};
2604 let Inst{11-8} = 0b1000;
2605 let Inst{7} = Vn{0};
2606 let Inst{6} = op6;
2607 let Inst{5} = Vm{0};
2608 let Inst{4} = op4;
2609 let Inst{3-0} = Vm{4-1};
2610 }
2611
25812612 // Operand types for complex instructions
25822613 class ComplexRotationOperand
25832614 : AsmOperandClass {
284284 AssemblerPredicate<"FeatureFP16","half-float conversions">;
285285 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
286286 AssemblerPredicate<"FeatureFullFP16","full half-float">;
287 def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">,
288 AssemblerPredicate<"FeatureFP16FML","full half-float fml">;
287289 def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">,
288290 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">;
289291 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
51075107 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
51085108 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
51095109 }
5110
5111 // +fp16fml Floating Point Multiplication Variants
5112 let Predicates = [HasNEON, HasFP16FML], DecoderNamespace= "VFPV8" in {
5113
5114 class N3VCP8F16Q1
5115 RegisterClass Tm, bits<2> op1, bits<2> op2, bit op3>
5116 : N3VCP8
5117 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5118
5119 class N3VCP8F16Q0
5120 RegisterClass Tm, bits<2> op1, bits<2> op2, bit op3>
5121 : N3VCP8Q0
5122 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5123
5124 class VFMQ0 S>
5125 : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
5126 (ins SPR:$Vn, SPR:$Vm, VectorIndex32:$idx),
5127 IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
5128 bit idx;
5129 let Inst{3} = idx;
5130 let Inst{19-16} = Vn{4-1};
5131 let Inst{7} = Vn{0};
5132 let Inst{5} = Vm{0};
5133 let Inst{2-0} = Vm{3-1};
5134 }
5135
5136 class VFMQ1 S>
5137 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5138 (ins DPR:$Vn, DPR:$Vm, VectorIndex16:$idx),
5139 IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
5140 bits<2> idx;
5141 let Inst{5} = idx{1};
5142 let Inst{3} = idx{0};
5143 }
5144
5145 let hasNoSchedulingInfo = 1 in {
5146 // op1 op2 op3
5147 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
5148 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
5149 def VFMALQ : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>;
5150 def VFMSLQ : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
5151 def VFMALDI : VFMQ0<"vfmal", 0b00>;
5152 def VFMSLDI : VFMQ0<"vfmsl", 0b01>;
5153 def VFMALQI : VFMQ1<"vfmal", 0b00>;
5154 def VFMSLQI : VFMQ1<"vfmsl", 0b01>;
5155 }
5156 } // HasNEON, HasFP16FML
5157
51105158
51115159 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
51125160 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
225225
226226 /// HasFullFP16 - True if subtarget supports half-precision FP operations
227227 bool HasFullFP16 = false;
228
229 /// HasFP16FML - True if subtarget supports half-precision FP fml operations
230 bool HasFP16FML = false;
228231
229232 /// HasD16 - True if subtarget is limited to 16 double precision
230233 /// FP registers for VFPv3.
621624 bool hasFP16() const { return HasFP16; }
622625 bool hasD16() const { return HasD16; }
623626 bool hasFullFP16() const { return HasFullFP16; }
627 bool hasFP16FML() const { return HasFP16FML; }
624628
625629 bool hasFuseAES() const { return HasFuseAES; }
626630 bool hasFuseLiterals() const { return HasFuseLiterals; }
5656 const FeatureBitset InlineFeatureWhitelist = {
5757 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
5858 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
59 ARM::FeatureFullFP16, ARM::FeatureHWDivThumb,
59 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
6060 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
6161 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
6262 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
56255625 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
56265626 Mnemonic == "bxns" || Mnemonic == "blxns" ||
56275627 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5628 Mnemonic == "vcmla" || Mnemonic == "vcadd")
5628 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5629 Mnemonic == "vfmal" || Mnemonic == "vfmsl")
56295630 return Mnemonic;
56305631
56315632 // First, split out any predication code. Ignore mnemonics we know aren't
57155716 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
57165717 Mnemonic == "vmovx" || Mnemonic == "vins" ||
57175718 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5718 Mnemonic == "vcmla" || Mnemonic == "vcadd") {
5719 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5720 Mnemonic == "vfmal" || Mnemonic == "vfmsl") {
57195721 // These mnemonics are never predicable
57205722 CanAcceptPredicationCode = false;
57215723 } else if (!isThumb()) {
0 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp16fml,+neon < %s 2>&1 | FileCheck %s --check-prefix=CHECK
1
2 //------------------------------------------------------------------------------
3 // ARMV8.2-A Floating Point Multiplication
4 //------------------------------------------------------------------------------
5
6 fmlal V0.2s, v1.2h, v2.h[8]
7 fmlsl V0.2s, v1.2h, v2.h[8]
8 fmlal V0.4s, v1.4h, v2.h[8]
9 fmlsl V0.4s, v1.4h, v2.h[8]
10
11 fmlal2 V0.2s, v1.2h, v2.h[8]
12 fmlsl2 V0.2s, v1.2h, v2.h[8]
13 fmlal2 V0.4s, v1.4h, v2.h[8]
14 fmlsl2 V0.4s, v1.4h, v2.h[8]
15
16 fmlal V0.2s, v1.2h, v2.h[-1]
17 fmlsl2 V0.2s, v1.2h, v2.h[-1]
18
19 //CHECK: error: vector lane must be an integer in range [0, 7].
20 //CHECK-NEXT: fmlal V0.2s, v1.2h, v2.h[8]
21 //CHECK-NEXT: ^
22 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
23 //CHECK-NEXT: fmlsl V0.2s, v1.2h, v2.h[8]
24 //CHECK-NEXT: ^
25 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
26 //CHECK-NEXT: fmlal V0.4s, v1.4h, v2.h[8]
27 //CHECK-NEXT: ^
28 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
29 //CHECK-NEXT: fmlsl V0.4s, v1.4h, v2.h[8]
30 //CHECK-NEXT: ^
31
32 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
33 //CHECK-NEXT: fmlal2 V0.2s, v1.2h, v2.h[8]
34 //CHECK-NEXT: ^
35 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
36 //CHECK-NEXT: fmlsl2 V0.2s, v1.2h, v2.h[8]
37 //CHECK-NEXT: ^
38 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
39 //CHECK-NEXT: fmlal2 V0.4s, v1.4h, v2.h[8]
40 //CHECK-NEXT: ^
41 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
42 //CHECK-NEXT: fmlsl2 V0.4s, v1.4h, v2.h[8]
43 //CHECK-NEXT: ^
44
45 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
46 //CHECK-NEXT: fmlal V0.2s, v1.2h, v2.h[-1]
47 //CHECK-NEXT: ^
48 //CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
49 //CHECK-NEXT: fmlsl2 V0.2s, v1.2h, v2.h[-1]
50 //CHECK-NEXT: ^
0 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp16fml < %s | FileCheck %s --check-prefix=CHECK
1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-fullfp16,+fp16fml < %s | FileCheck %s --check-prefix=CHECK
2 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOFP16FML
3 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOFP16FML
4 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fp16fml,-fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOFP16FML
5 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-neon,+fp16fml < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEON
6 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-neon < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-FP16FML-NOR-NEON
7
8 //------------------------------------------------------------------------------
9 // ARMV8.2-A Floating Point Multiplication
10 //------------------------------------------------------------------------------
11
12 FMLAL V0.2S, V1.2H, V2.2H
13 FMLSL V0.2S, V1.2H, V2.2H
14 FMLAL V0.4S, V1.4H, V2.4H
15 FMLSL V0.4S, V1.4H, V2.4H
16 FMLAL2 V0.2S, V1.2H, V2.2H
17 FMLSL2 V0.2S, V1.2H, V2.2H
18 FMLAL2 V0.4S, V1.4H, V2.4H
19 FMLSL2 V0.4S, V1.4H, V2.4H
20
21 //CHECK: fmlal v0.2s, v1.2h, v2.2h // encoding: [0x20,0xec,0x22,0x0e]
22 //CHECK: fmlsl v0.2s, v1.2h, v2.2h // encoding: [0x20,0xec,0xa2,0x0e]
23 //CHECK: fmlal v0.4s, v1.4h, v2.4h // encoding: [0x20,0xec,0x22,0x4e]
24 //CHECK: fmlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xec,0xa2,0x4e]
25 //CHECK: fmlal2 v0.2s, v1.2h, v2.2h // encoding: [0x20,0xcc,0x22,0x2e]
26 //CHECK: fmlsl2 v0.2s, v1.2h, v2.2h // encoding: [0x20,0xcc,0xa2,0x2e]
27 //CHECK: fmlal2 v0.4s, v1.4h, v2.4h // encoding: [0x20,0xcc,0x22,0x6e]
28 //CHECK: fmlsl2 v0.4s, v1.4h, v2.4h // encoding: [0x20,0xcc,0xa2,0x6e]
29
30 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
31 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
32 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
33 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
34 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
35 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
36 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
37 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
38
39 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
40 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
41 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
42 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
43 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
44 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
45 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
46 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
47
48 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
49 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
50 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
51 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
52 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
53 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
54 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
55 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
56
57 # Checks with the maximum index value 7:
58 fmlal V0.2s, v1.2h, v2.h[7]
59 fmlsl V0.2s, v1.2h, v2.h[7]
60 fmlal V0.4s, v1.4h, v2.h[7]
61 fmlsl V0.4s, v1.4h, v2.h[7]
62 fmlal2 V0.2s, v1.2h, v2.h[7]
63 fmlsl2 V0.2s, v1.2h, v2.h[7]
64 fmlal2 V0.4s, v1.4h, v2.h[7]
65 fmlsl2 V0.4s, v1.4h, v2.h[7]
66
67 # Some more checks with a different index bit pattern to catch
68 # incorrect permutations of the index (decimal 7 is 0b111):
69 fmlal V0.2s, v1.2h, v2.h[5]
70 fmlsl V0.2s, v1.2h, v2.h[5]
71 fmlal V0.4s, v1.4h, v2.h[5]
72 fmlsl V0.4s, v1.4h, v2.h[5]
73 fmlal2 V0.2s, v1.2h, v2.h[5]
74 fmlsl2 V0.2s, v1.2h, v2.h[5]
75 fmlal2 V0.4s, v1.4h, v2.h[5]
76 fmlsl2 V0.4s, v1.4h, v2.h[5]
77
78 //CHECK: fmlal v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x08,0xb2,0x0f]
79 //CHECK: fmlsl v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x48,0xb2,0x0f]
80 //CHECK: fmlal v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x08,0xb2,0x4f]
81 //CHECK: fmlsl v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x48,0xb2,0x4f]
82 //CHECK: fmlal2 v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x88,0xb2,0x2f]
83 //CHECK: fmlsl2 v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0xc8,0xb2,0x2f]
84 //CHECK: fmlal2 v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x88,0xb2,0x6f]
85 //CHECK: fmlsl2 v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0xc8,0xb2,0x6f]
86
87 //CHECK: fmlal v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x08,0x92,0x0f]
88 //CHECK: fmlsl v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x48,0x92,0x0f]
89 //CHECK: fmlal v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x08,0x92,0x4f]
90 //CHECK: fmlsl v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x48,0x92,0x4f]
91 //CHECK: fmlal2 v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x88,0x92,0x2f]
92 //CHECK: fmlsl2 v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0xc8,0x92,0x2f]
93 //CHECK: fmlal2 v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x88,0x92,0x6f]
94 //CHECK: fmlsl2 v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0xc8,0x92,0x6f]
95
96 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
97 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
98 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
99 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
100 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
101 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
102 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
103 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
104 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
105 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
106 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
107 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
108 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
109 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
110 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
111 //CHECK-NOFP16FML: error: instruction requires: fp16fml{{$}}
112
113 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
114 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
115 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
116 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
117 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
118 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
119 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
120 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
121 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
122 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
123 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
124 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
125 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
126 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
127 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
128 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
129
130 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
131 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
132 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
133 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
134 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
135 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
136 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
137 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
138 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
139 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
140 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
141 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
142 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
143 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
144 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
145 //CHECK-NO-FP16FML-NOR-NEON: error: instruction requires: fp16fml neon{{$}}
146
0 // RUN: not llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
1
2 VFMAL.F16 D0, S1, S2[2]
3 vfmsl.f16 d0, s1, s2[2]
4 vfmsl.f16 d0, s1, s2[-1]
5 vfmal.f16 q0, d1, d2[4]
6 VFMSL.F16 Q0, D1, D2[4]
7 vfmal.f16 q0, d1, d2[-1]
8
9 //CHECK-ERROR: error: invalid operand for instruction
10 //CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
11 //CHECK-ERROR-NEXT: ^
12 //CHECK-ERROR-NEXT: error: invalid operand for instruction
13 //CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2]
14 //CHECK-ERROR-NEXT: ^
15 //CHECK-ERROR-NEXT: error: invalid operand for instruction
16 //CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1]
17 //CHECK-ERROR-NEXT: ^
18 //CHECK-ERROR-NEXT: error: invalid operand for instruction
19 //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4]
20 //CHECK-ERROR-NEXT: ^
21 //CHECK-ERROR-NEXT: error: invalid operand for instruction
22 //CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4]
23 //CHECK-ERROR-NEXT: ^
24 //CHECK-ERROR-NEXT: error: invalid operand for instruction
25 //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
26 //CHECK-ERROR-NEXT: ^
0 // RUN: llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK
1 // RUN: llvm-mc -triple thumb -mattr=+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK-T32
2 // RUN: llvm-mc -triple arm -mattr=-fullfp16,+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK
3 // RUN: llvm-mc -triple thumb -mattr=-fullfp16,+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK-T32
4
5 // RUN: not llvm-mc -triple arm -mattr=+v8.2a -show-encoding < %s 2> %t
6 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML-NOR-NEON < %t %s
7 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a -show-encoding < %s 2> %t
8 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML-NOR-NEON < %t %s
9
10 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon -show-encoding < %s 2> %t
11 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
12 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon -show-encoding < %s 2> %t
13 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
14
15 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon,+fp16fml,-fp16fml -show-encoding < %s 2> %t
16 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
17 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fp16fml,-fp16fml -show-encoding < %s 2> %t
18 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
19
20 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon,+fullfp16 -show-encoding < %s 2> %t
21 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
22 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fullfp16 -show-encoding < %s 2> %t
23 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
24
25 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon,+fp16fml,-fullfp16 -show-encoding < %s 2> %t
26 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
27 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fp16fml,-fullfp16 -show-encoding < %s 2> %t
28 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML < %t %s
29
30 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+fp16fml -show-encoding < %s 2> %t
31 // RUN: FileCheck --check-prefix=CHECK-NO-NEON < %t %s
32 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fp16fml -show-encoding < %s 2> %t
33 // RUN: FileCheck --check-prefix=CHECK-NO-NEON < %t %s
34
35 VFMAL.F16 D0, S1, S2
36 vfmsl.f16 d0, s1, s2
37 vfmal.f16 q0, d1, d2
38 VFMSL.F16 Q0, D1, D2
39
40 VFMAL.F16 D0, S1, S2[1]
41 vfmsl.f16 d0, s1, s2[1]
42 vfmal.f16 q0, d1, d2[3]
43 VFMSL.F16 Q0, D1, D2[3]
44
45 //CHECK: vfmal.f16 d0, s1, s2 @ encoding: [0x91,0x08,0x20,0xfc]
46 //CHECK: vfmsl.f16 d0, s1, s2 @ encoding: [0x91,0x08,0xa0,0xfc]
47 //CHECK: vfmal.f16 q0, d1, d2 @ encoding: [0x52,0x08,0x21,0xfc]
48 //CHECK: vfmsl.f16 q0, d1, d2 @ encoding: [0x52,0x08,0xa1,0xfc]
49
50 //CHECK: vfmal.f16 d0, s1, s2[1] @ encoding: [0x99,0x08,0x00,0xfe]
51 //CHECK: vfmsl.f16 d0, s1, s2[1] @ encoding: [0x99,0x08,0x10,0xfe]
52 //CHECK: vfmal.f16 q0, d1, d2[3] @ encoding: [0x7a,0x08,0x01,0xfe]
53 //CHECK: vfmsl.f16 q0, d1, d2[3] @ encoding: [0x7a,0x08,0x11,0xfe]
54
55 //CHECK-T32: vfmal.f16 d0, s1, s2 @ encoding: [0x20,0xfc,0x91,0x08]
56 //CHECK-T32: vfmsl.f16 d0, s1, s2 @ encoding: [0xa0,0xfc,0x91,0x08]
57 //CHECK-T32: vfmal.f16 q0, d1, d2 @ encoding: [0x21,0xfc,0x52,0x08]
58 //CHECK-T32: vfmsl.f16 q0, d1, d2 @ encoding: [0xa1,0xfc,0x52,0x08]
59
60 //CHECK-T32: vfmal.f16 d0, s1, s2[1] @ encoding: [0x00,0xfe,0x99,0x08]
61 //CHECK-T32: vfmsl.f16 d0, s1, s2[1] @ encoding: [0x10,0xfe,0x99,0x08]
62 //CHECK-T32: vfmal.f16 q0, d1, d2[3] @ encoding: [0x01,0xfe,0x7a,0x08]
63 //CHECK-T32: vfmsl.f16 q0, d1, d2[3] @ encoding: [0x11,0xfe,0x7a,0x08]
64
65 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
66 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
67 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
68 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
69 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
70 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
71 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
72 //CHECK-NO-FP16FML: instruction requires: full half-float fml{{$}}
73
74 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
75 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
76 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
77 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
78 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
79 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
80 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
81 //CHECK-NO-FP16FML-NOR-NEON: instruction requires: full half-float fml NEON{{$}}
82
83 //CHECK-NO-NEON: instruction requires: NEON{{$}}
84 //CHECK-NO-NEON: instruction requires: NEON{{$}}
85 //CHECK-NO-NEON: instruction requires: NEON{{$}}
86 //CHECK-NO-NEON: instruction requires: NEON{{$}}
87 //CHECK-NO-NEON: instruction requires: NEON{{$}}
88 //CHECK-NO-NEON: instruction requires: NEON{{$}}
89 //CHECK-NO-NEON: instruction requires: NEON{{$}}
90 //CHECK-NO-NEON: instruction requires: NEON{{$}}
91
0 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-ERROR,FP16-ERROR
1 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=FP16,CHECK-ERROR
2 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16,-fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=FP16,CHECK-ERROR
3 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,-fp16fml,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=FP16,CHECK-ERROR
4 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fp16fml,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-ERROR,FP16-ERROR
5 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fp16fml,-neon --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=FP16,CHECK-ERROR
6
7 [0x20,0xec,0x22,0x0e]
8 [0x20,0xec,0xa2,0x0e]
9 [0x20,0xec,0x22,0x4e]
10 [0x20,0xec,0xa2,0x4e]
11 [0x20,0xcc,0x22,0x2e]
12 [0x20,0xcc,0xa2,0x2e]
13 [0x20,0xcc,0x22,0x6e]
14 [0x20,0xcc,0xa2,0x6e]
15
16 #indexed variants:
17
18 [0x20,0x08,0xb2,0x0f]
19 [0x20,0x48,0xb2,0x0f]
20 [0x20,0x08,0xb2,0x4f]
21 [0x20,0x48,0xb2,0x4f]
22 [0x20,0x88,0xb2,0x2f]
23 [0x20,0xc8,0xb2,0x2f]
24 [0x20,0x88,0xb2,0x6f]
25 [0x20,0xc8,0xb2,0x6f]
26
27 [0x20,0x08,0x92,0x0f]
28 [0x20,0x48,0x92,0x0f]
29 [0x20,0x08,0x92,0x4f]
30 [0x20,0x48,0x92,0x4f]
31 [0x20,0x88,0x92,0x2f]
32 [0x20,0xc8,0x92,0x2f]
33 [0x20,0x88,0x92,0x6f]
34 [0x20,0xc8,0x92,0x6f]
35
36 #A fullfp16 instruction, for testing the interaction of the features
37 [0x41,0x08,0xe3,0x1e]
38
39 #CHECK-ERROR: warning: invalid instruction encoding
40 #CHECK-ERROR: [0x20,0xec,0x22,0x0e]
41 #CHECK-ERROR: ^
42 #CHECK-ERROR: warning: invalid instruction encoding
43 #CHECK-ERROR: [0x20,0xec,0xa2,0x0e]
44 #CHECK-ERROR: ^
45 #CHECK-ERROR: warning: invalid instruction encoding
46 #CHECK-ERROR: [0x20,0xec,0x22,0x4e]
47 #CHECK-ERROR: ^
48 #CHECK-ERROR: warning: invalid instruction encoding
49 #CHECK-ERROR: [0x20,0xec,0xa2,0x4e]
50 #CHECK-ERROR: ^
51 #CHECK-ERROR: warning: invalid instruction encoding
52 #CHECK-ERROR: [0x20,0xcc,0x22,0x2e]
53 #CHECK-ERROR: ^
54 #CHECK-ERROR: warning: invalid instruction encoding
55 #CHECK-ERROR: [0x20,0xcc,0xa2,0x2e]
56 #CHECK-ERROR: ^
57 #CHECK-ERROR: warning: invalid instruction encoding
58 #CHECK-ERROR: [0x20,0xcc,0x22,0x6e]
59 #CHECK-ERROR: ^
60 #CHECK-ERROR: warning: invalid instruction encoding
61 #CHECK-ERROR: [0x20,0xcc,0xa2,0x6e]
62 #CHECK-ERROR: ^
63 #CHECK-ERROR: warning: invalid instruction encoding
64 #CHECK-ERROR: [0x20,0x08,0xb2,0x0f]
65 #CHECK-ERROR: ^
66 #CHECK-ERROR: warning: invalid instruction encoding
67 #CHECK-ERROR: [0x20,0x48,0xb2,0x0f]
68 #CHECK-ERROR: ^
69 #CHECK-ERROR: warning: invalid instruction encoding
70 #CHECK-ERROR: [0x20,0x08,0xb2,0x4f]
71 #CHECK-ERROR: ^
72 #CHECK-ERROR: warning: invalid instruction encoding
73 #CHECK-ERROR: [0x20,0x48,0xb2,0x4f]
74 #CHECK-ERROR: ^
75 #CHECK-ERROR: warning: invalid instruction encoding
76 #CHECK-ERROR: [0x20,0x88,0xb2,0x2f]
77 #CHECK-ERROR: ^
78 #CHECK-ERROR: warning: invalid instruction encoding
79 #CHECK-ERROR: [0x20,0xc8,0xb2,0x2f]
80 #CHECK-ERROR: ^
81 #CHECK-ERROR: warning: invalid instruction encoding
82 #CHECK-ERROR: [0x20,0x88,0xb2,0x6f]
83 #CHECK-ERROR: ^
84 #CHECK-ERROR: warning: invalid instruction encoding
85 #CHECK-ERROR: [0x20,0xc8,0xb2,0x6f]
86 #CHECK-ERROR: ^
87 #CHECK-ERROR: warning: invalid instruction encoding
88 #CHECK-ERROR: [0x20,0x08,0x92,0x0f]
89 #CHECK-ERROR: ^
90 #CHECK-ERROR: warning: invalid instruction encoding
91 #CHECK-ERROR: [0x20,0x48,0x92,0x0f]
92 #CHECK-ERROR: ^
93 #CHECK-ERROR: warning: invalid instruction encoding
94 #CHECK-ERROR: [0x20,0x08,0x92,0x4f]
95 #CHECK-ERROR: ^
96 #CHECK-ERROR: warning: invalid instruction encoding
97 #CHECK-ERROR: [0x20,0x48,0x92,0x4f]
98 #CHECK-ERROR: ^
99 #CHECK-ERROR: warning: invalid instruction encoding
100 #CHECK-ERROR: [0x20,0x88,0x92,0x2f]
101 #CHECK-ERROR: ^
102 #CHECK-ERROR: warning: invalid instruction encoding
103 #CHECK-ERROR: [0x20,0xc8,0x92,0x2f]
104 #CHECK-ERROR: ^
105 #CHECK-ERROR: warning: invalid instruction encoding
106 #CHECK-ERROR: [0x20,0x88,0x92,0x6f]
107 #CHECK-ERROR: ^
108 #CHECK-ERROR: warning: invalid instruction encoding
109 #CHECK-ERROR: [0x20,0xc8,0x92,0x6f]
110 #CHECK-ERROR: ^
111
112 #FP16-ERROR: warning: invalid instruction encoding
113 #FP16-ERROR: [0x41,0x08,0xe3,0x1e]
114 #FP16-ERROR: ^
115
116 #FP16-NOT: [0x41,0x08,0xe3,0x1e]
117
0 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
1 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
2
3 #A fullfp16 instruction, for testing the interaction of the features
4 [0x41,0x08,0xe3,0x1e]
5
6 [0x20,0xec,0x22,0x0e]
7 [0x20,0xec,0xa2,0x0e]
8 [0x20,0xec,0x22,0x4e]
9 [0x20,0xec,0xa2,0x4e]
10 [0x20,0xcc,0x22,0x2e]
11 [0x20,0xcc,0xa2,0x2e]
12 [0x20,0xcc,0x22,0x6e]
13 [0x20,0xcc,0xa2,0x6e]
14
15 #indexed variants:
16
17 [0x20,0x08,0xb2,0x0f]
18 [0x20,0x48,0xb2,0x0f]
19 [0x20,0x08,0xb2,0x4f]
20 [0x20,0x48,0xb2,0x4f]
21 [0x20,0x88,0xb2,0x2f]
22 [0x20,0xc8,0xb2,0x2f]
23 [0x20,0x88,0xb2,0x6f]
24 [0x20,0xc8,0xb2,0x6f]
25
26 [0x20,0x08,0x92,0x0f]
27 [0x20,0x48,0x92,0x0f]
28 [0x20,0x08,0x92,0x4f]
29 [0x20,0x48,0x92,0x4f]
30 [0x20,0x88,0x92,0x2f]
31 [0x20,0xc8,0x92,0x2f]
32 [0x20,0x88,0x92,0x6f]
33 [0x20,0xc8,0x92,0x6f]
34
35 #FP16: fmul h1, h2, h3
36
37 #CHECK: fmlal v0.2s, v1.2h, v2.2h
38 #CHECK: fmlsl v0.2s, v1.2h, v2.2h
39 #CHECK: fmlal v0.4s, v1.4h, v2.4h
40 #CHECK: fmlsl v0.4s, v1.4h, v2.4h
41 #CHECK: fmlal2 v0.2s, v1.2h, v2.2h
42 #CHECK: fmlsl2 v0.2s, v1.2h, v2.2h
43 #CHECK: fmlal2 v0.4s, v1.4h, v2.4h
44 #CHECK: fmlsl2 v0.4s, v1.4h, v2.4h
45
46 #CHECK: fmlal v0.2s, v1.2h, v2.h[7]
47 #CHECK: fmlsl v0.2s, v1.2h, v2.h[7]
48 #CHECK: fmlal v0.4s, v1.4h, v2.h[7]
49 #CHECK: fmlsl v0.4s, v1.4h, v2.h[7]
50 #CHECK: fmlal2 v0.2s, v1.2h, v2.h[7]
51 #CHECK: fmlsl2 v0.2s, v1.2h, v2.h[7]
52 #CHECK: fmlal2 v0.4s, v1.4h, v2.h[7]
53 #CHECK: fmlsl2 v0.4s, v1.4h, v2.h[7]
54
55 #CHECK: fmlal v0.2s, v1.2h, v2.h[5]
56 #CHECK: fmlsl v0.2s, v1.2h, v2.h[5]
57 #CHECK: fmlal v0.4s, v1.4h, v2.h[5]
58 #CHECK: fmlsl v0.4s, v1.4h, v2.h[5]
59 #CHECK: fmlal2 v0.2s, v1.2h, v2.h[5]
60 #CHECK: fmlsl2 v0.2s, v1.2h, v2.h[5]
61 #CHECK: fmlal2 v0.4s, v1.4h, v2.h[5]
62 #CHECK: fmlsl2 v0.4s, v1.4h, v2.h[5]
63
0 # RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+neon,+fp16fml --disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+neon,-fullfp16,+fp16fml --disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple arm-none-linux-gnu --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-COPROC
3 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
4 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
5 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
6 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,-fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
7 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,-fp16fml,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
8 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
9 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fp16fml,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
10 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
11 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
12 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon,+fullfp16,-fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
13 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon,-fp16fml,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
14 # RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon,+fp16fml,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
15
16 [0x91,0x08,0x20,0xfc]
17 [0x91,0x08,0xa0,0xfc]
18 [0x52,0x08,0x21,0xfc]
19 [0x52,0x08,0xa1,0xfc]
20 [0x99,0x08,0x00,0xfe]
21 [0x99,0x08,0x10,0xfe]
22 [0x7a,0x08,0x01,0xfe]
23 [0x7a,0x08,0x11,0xfe]
24
25 #A fullfp16 instruction, for testing the interaction of the features
26 [0x80,0x09,0x30,0xee]
27
28 #CHECK: vfmal.f16 d0, s1, s2
29 #CHECK: vfmsl.f16 d0, s1, s2
30 #CHECK: vfmal.f16 q0, d1, d2
31 #CHECK: vfmsl.f16 q0, d1, d2
32 #CHECK: vfmal.f16 d0, s1, s2[1]
33 #CHECK: vfmsl.f16 d0, s1, s2[1]
34 #CHECK: vfmal.f16 q0, d1, d2[3]
35 #CHECK: vfmsl.f16 q0, d1, d2[3]
36 #CHECK: vadd.f16 s0, s1, s0
37
38 #CHECK-COPROC: stc2 p8, c0, [r0], #-580
39 #CHECK-COPROC: stc2 p8, c0, [r0], #580
40 #CHECK-COPROC: stc2 p8, c0, [r1], #-328
41 #CHECK-COPROC: stc2 p8, c0, [r1], #328
42 #CHECK-COPROC: mcr2 p8, #0, r0, c0, c9, #4
43 #CHECK-COPROC: mrc2 p8, #0, r0, c0, c9, #4
44 #CHECK-COPROC: mcr2 p8, #0, r0, c1, c10, #3
45 #CHECK-COPROC: mrc2 p8, #0, r0, c1, c10, #3
46 #CHECK-COPROC: cdp p9, #3, c0, c0, c0, #4
47
48 #CHECK-INVALID: warning: invalid instruction encoding
49 #CHECK-INVALID: [0x91,0x08,0x20,0xfc]
50 #CHECK-INVALID: ^
51 #CHECK-INVALID: warning: invalid instruction encoding
52 #CHECK-INVALID: [0x91,0x08,0xa0,0xfc]
53 #CHECK-INVALID: ^
54 #CHECK-INVALID: warning: invalid instruction encoding
55 #CHECK-INVALID: [0x52,0x08,0x21,0xfc]
56 #CHECK-INVALID: ^
57 #CHECK-INVALID: warning: invalid instruction encoding
58 #CHECK-INVALID: [0x52,0x08,0xa1,0xfc]
59 #CHECK-INVALID: ^
60 #CHECK-INVALID: warning: invalid instruction encoding
61 #CHECK-INVALID: [0x99,0x08,0x00,0xfe]
62 #CHECK-INVALID: ^
63 #CHECK-INVALID: warning: invalid instruction encoding
64 #CHECK-INVALID: [0x99,0x08,0x10,0xfe]
65 #CHECK-INVALID: ^
66 #CHECK-INVALID: warning: invalid instruction encoding
67 #CHECK-INVALID: [0x7a,0x08,0x01,0xfe]
68 #CHECK-INVALID: ^
69 #CHECK-INVALID: warning: invalid instruction encoding
70 #CHECK-INVALID: [0x7a,0x08,0x11,0xfe]
71 #CHECK-INVALID: ^
72
73 #FP16-INVALID: warning: invalid instruction encoding
74 #FP16-INVALID: [0x80,0x09,0x30,0xee]
75 #FP16-INVALID: ^
76
77 #FP16-NOT: [0x80,0x09,0x30,0xee]
0 # RUN: llvm-mc -triple thumb -mattr=+neon,+fp16fml --disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple thumb -mattr=+neon,-fullfp16,+fp16fml --disassemble < %s | FileCheck %s
2 # RUN: not llvm-mc -triple thumb --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
3 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
4 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
5 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
6 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,-fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
7 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,-fp16fml,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
8 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
9 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fp16fml,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
10 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
11 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
12 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fullfp16,-fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
13 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,-fp16fml,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16
14 # RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fp16fml,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-INVALID,FP16-INVALID
15
16 [0x20,0xfc,0x91,0x08]
17 [0xa0,0xfc,0x91,0x08]
18 [0x21,0xfc,0x52,0x08]
19 [0xa1,0xfc,0x52,0x08]
20 [0x00,0xfe,0x99,0x08]
21 [0x10,0xfe,0x99,0x08]
22 [0x01,0xfe,0x7a,0x08]
23 [0x11,0xfe,0x7a,0x08]
24
25 #A fullfp16 instruction, for testing the interaction of the features
26 [0x30,0xee,0x80,0x09]
27
28 #CHECK: vfmal.f16 d0, s1, s2
29 #CHECK: vfmsl.f16 d0, s1, s2
30 #CHECK: vfmal.f16 q0, d1, d2
31 #CHECK: vfmsl.f16 q0, d1, d2
32 #CHECK: vfmal.f16 d0, s1, s2[1]
33 #CHECK: vfmsl.f16 d0, s1, s2[1]
34 #CHECK: vfmal.f16 q0, d1, d2[3]
35 #CHECK: vfmsl.f16 q0, d1, d2[3]
36 #CHECK: vadd.f16 s0, s1, s0
37
38 #CHECK-INVALID: warning: invalid instruction encoding
39 #CHECK-INVALID: [0x20,0xfc,0x91,0x08]
40 #CHECK-INVALID: ^
41 #CHECK-INVALID: warning: invalid instruction encoding
42 #CHECK-INVALID: [0xa0,0xfc,0x91,0x08]
43 #CHECK-INVALID: ^
44 #CHECK-INVALID: warning: invalid instruction encoding
45 #CHECK-INVALID: [0x21,0xfc,0x52,0x08]
46 #CHECK-INVALID: ^
47 #CHECK-INVALID: warning: invalid instruction encoding
48 #CHECK-INVALID: [0xa1,0xfc,0x52,0x08]
49 #CHECK-INVALID: ^
50 #CHECK-INVALID: warning: invalid instruction encoding
51 #CHECK-INVALID: [0x00,0xfe,0x99,0x08]
52 #CHECK-INVALID: ^
53 #CHECK-INVALID: warning: invalid instruction encoding
54 #CHECK-INVALID: [0x10,0xfe,0x99,0x08]
55 #CHECK-INVALID: ^
56 #CHECK-INVALID: warning: invalid instruction encoding
57 #CHECK-INVALID: [0x01,0xfe,0x7a,0x08]
58 #CHECK-INVALID: ^
59 #CHECK-INVALID: warning: invalid instruction encoding
60 #CHECK-INVALID: [0x11,0xfe,0x7a,0x08]
61 #CHECK-INVALID: ^
62
63 #FP16-INVALID: warning: invalid instruction encoding
64 #FP16-INVALID: [0x30,0xee,0x80,0x09]
65 #FP16-INVALID: ^
66
67 #FP16-NOT: [0x30,0xee,0x80,0x09]
447447 ARM::ArchKind::INVALID, "fp16"));
448448 EXPECT_TRUE(testARMExtension("cortex-a55",
449449 ARM::ArchKind::INVALID, "fp16"));
450 EXPECT_FALSE(testARMExtension("cortex-a55",
451 ARM::ArchKind::INVALID, "fp16fml"));
450452 EXPECT_TRUE(testARMExtension("cortex-a75",
451453 ARM::ArchKind::INVALID, "fp16"));
454 EXPECT_FALSE(testARMExtension("cortex-a75",
455 ARM::ArchKind::INVALID, "fp16fml"));
452456 EXPECT_FALSE(testARMExtension("cortex-r52",
453457 ARM::ArchKind::INVALID, "ras"));
454458 EXPECT_FALSE(testARMExtension("iwmmxt", ARM::ArchKind::INVALID, "crc"));
480484 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_1A, "ras"));
481485 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_2A, "spe"));
482486 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_2A, "fp16"));
487 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_2A, "fp16fml"));
483488 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_3A, "fp16"));
489 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_3A, "fp16fml"));
484490 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_4A, "fp16"));
491 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_4A, "fp16fml"));
485492 EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8R, "ras"));
486493 EXPECT_FALSE(testARMExtension("generic",
487494 ARM::ArchKind::ARMV8MBaseline, "crc"));
535542 std::vector Features;
536543 unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP |
537544 ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP |
538 ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS | ARM::AEK_FP16;
545 ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS | ARM::AEK_FP16 |
546 ARM::AEK_FP16FML;
539547
540548 for (unsigned i = 0; i <= Extensions; i++)
541549 EXPECT_TRUE(i == 0 ? !ARM::getExtensionFeatures(i, Features)
563571 {"sec", "nosec", nullptr, nullptr},
564572 {"virt", "novirt", nullptr, nullptr},
565573 {"fp16", "nofp16", "+fullfp16", "-fullfp16"},
574 {"fp16fml", "nofp16fml", "+fp16fml", "-fp16fml"},
566575 {"ras", "noras", "+ras", "-ras"},
567576 {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
568577 {"os", "noos", nullptr, nullptr},
863872 AArch64::ArchKind::INVALID, "fp16"));
864873 EXPECT_TRUE(testAArch64Extension("cortex-a55",
865874 AArch64::ArchKind::INVALID, "fp16"));
875 EXPECT_FALSE(testAArch64Extension("cortex-a55",
876 AArch64::ArchKind::INVALID, "fp16fml"));
866877 EXPECT_TRUE(testAArch64Extension("cortex-a75",
867878 AArch64::ArchKind::INVALID, "fp16"));
879 EXPECT_FALSE(testAArch64Extension("cortex-a75",
880 AArch64::ArchKind::INVALID, "fp16fml"));
868881 EXPECT_FALSE(testAArch64Extension("thunderx2t99",
869882 AArch64::ArchKind::INVALID, "ras"));
870883 EXPECT_FALSE(testAArch64Extension("thunderx",
885898 EXPECT_FALSE(testAArch64Extension(
886899 "generic", AArch64::ArchKind::ARMV8_2A, "fp16"));
887900 EXPECT_FALSE(testAArch64Extension(
901 "generic", AArch64::ArchKind::ARMV8_2A, "fp16fml"));
902 EXPECT_FALSE(testAArch64Extension(
888903 "generic", AArch64::ArchKind::ARMV8_3A, "fp16"));
889904 EXPECT_FALSE(testAArch64Extension(
905 "generic", AArch64::ArchKind::ARMV8_3A, "fp16fml"));
906 EXPECT_FALSE(testAArch64Extension(
890907 "generic", AArch64::ArchKind::ARMV8_4A, "fp16"));
908 EXPECT_FALSE(testAArch64Extension(
909 "generic", AArch64::ArchKind::ARMV8_4A, "fp16fml"));
891910 }
892911
893912 TEST(TargetParserTest, AArch64ExtensionFeatures) {
897916 AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
898917 AArch64::AEK_RAS | AArch64::AEK_LSE |
899918 AArch64::AEK_RDM | AArch64::AEK_SVE |
900 AArch64::AEK_DOTPROD | AArch64::AEK_RCPC;
919 AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
920 AArch64::AEK_FP16FML;
901921
902922 for (unsigned i = 0; i <= Extensions; i++)
903923 EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)
924944 {"fp", "nofp", "+fp-armv8", "-fp-armv8"},
925945 {"simd", "nosimd", "+neon", "-neon"},
926946 {"fp16", "nofp16", "+fullfp16", "-fullfp16"},
947 {"fp16fml", "nofp16fml", "+fp16fml", "-fp16fml"},
927948 {"profile", "noprofile", "+spe", "-spe"},
928949 {"ras", "noras", "+ras", "-ras"},
929950 {"lse", "nolse", "+lse", "-lse"},