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[X86] Add patterns to fold a 64-bit load into the EVEX vcvtph2ps instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317548 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 11 months ago
2 changed file(s) with 20 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
71957195
71967196 }
71977197
7198 let Predicates = [HasAVX512] in {
7198 let Predicates = [HasAVX512] in
71997199 defm VCVTPH2PSZ : avx512_cvtph2ps,
72007200 avx512_cvtph2ps_sae,
72017201 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
7202 let Predicates = [HasVLX] in {
7203 defm VCVTPH2PSZ256 : avx512_cvtph2ps
7204 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
7205 defm VCVTPH2PSZ128 : avx512_cvtph2ps
7206 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
7207 }
7202
7203 let Predicates = [HasVLX] in {
7204 defm VCVTPH2PSZ256 : avx512_cvtph2ps
7205 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
7206 defm VCVTPH2PSZ128 : avx512_cvtph2ps
7207 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
7208
7209 // Pattern match vcvtph2ps of a scalar i64 load.
7210 def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))),
7211 (VCVTPH2PSZ128rm addr:$src)>;
7212 def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzload_v2i64 addr:$src)))),
7213 (VCVTPH2PSZ128rm addr:$src)>;
7214 def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert
7215 (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
7216 (VCVTPH2PSZ128rm addr:$src)>;
72087217 }
72097218
72107219 multiclass avx512_cvtps2ph
176176 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar:
177177 ; X32-AVX512VL: # BB#0:
178178 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
179 ; X32-AVX512VL-NEXT: vmovsd (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x00]
180 ; X32-AVX512VL-NEXT: # xmm0 = mem[0],zero
181 ; X32-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0]
179 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00]
182180 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
183181 ;
184182 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar:
185183 ; X64-AVX512VL: # BB#0:
186 ; X64-AVX512VL-NEXT: vmovsd (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x07]
187 ; X64-AVX512VL-NEXT: # xmm0 = mem[0],zero
188 ; X64-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0]
184 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07]
189185 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
190186 %load = load i64, i64* %ptr
191187 %ins1 = insertelement <2 x i64> undef, i64 %load, i32 0
210206 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar2:
211207 ; X32-AVX512VL: # BB#0:
212208 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
213 ; X32-AVX512VL-NEXT: vmovsd (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x00]
214 ; X32-AVX512VL-NEXT: # xmm0 = mem[0],zero
215 ; X32-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0]
209 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00]
216210 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
217211 ;
218212 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar2:
219213 ; X64-AVX512VL: # BB#0:
220 ; X64-AVX512VL-NEXT: vmovsd (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x07]
221 ; X64-AVX512VL-NEXT: # xmm0 = mem[0],zero
222 ; X64-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0]
214 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07]
223215 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
224216 %load = load i64, i64* %ptr
225217 %ins = insertelement <2 x i64> undef, i64 %load, i32 0