llvm.org GIT mirror llvm / c2d98bc
Remove some not-really-used variables, as warned about by icc (#593, partial). Patch by Erick Tryzelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 11 years ago
12 changed file(s) with 19 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
690690 }
691691
692692 bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
693
694 static unsigned round = 0;
695 (void) round;
696
697693 // Set to true if we have any spills
698694 bool anotherRoundNeeded = false;
699695
242242 // Compute the latency for the node. We use the sum of the latencies for
243243 // all nodes flagged together into this SUnit.
244244 SU->Latency = 0;
245 bool SawMachineOpcode = false;
246245 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
247246 if (N->isMachineOpcode()) {
248 SawMachineOpcode = true;
249247 SU->Latency += InstrItins.
250248 getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
251249 }
17131713 MachineFunction *CurMF = FuncInfo.MF;
17141714
17151715 // Figure out which block is immediately after the current one.
1716 MachineBasicBlock *NextBlock = 0;
17171716 MachineFunction::iterator BBI = CR.CaseBB;
17181717
1719 if (++BBI != FuncInfo.MF->end())
1720 NextBlock = BBI;
1718 if (++BBI != FuncInfo.MF->end()) {}
17211719
17221720 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
17231721
17861784 MachineFunction *CurMF = FuncInfo.MF;
17871785
17881786 // Figure out which block is immediately after the current one.
1789 MachineBasicBlock *NextBlock = 0;
17901787 MachineFunction::iterator BBI = CR.CaseBB;
17911788
1792 if (++BBI != FuncInfo.MF->end())
1793 NextBlock = BBI;
1789 if (++BBI != FuncInfo.MF->end()) {}
17941790
17951791 Case& FrontCase = *CR.Range.first;
17961792 Case& BackCase = *(CR.Range.second-1);
557557
558558 SmallVector Uses;
559559 while (++MII != MBB->end()) {
560 bool FoundUse = false;
561560 bool FoundKill = false;
562561 const TargetInstrDesc &TID = MII->getDesc();
563562 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
580579 const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
581580 if (RC && !RC->contains(NewReg))
582581 return false;
583 FoundUse = true;
584582 if (MO.isKill())
585583 FoundKill = true;
586584
301301 char *ssp; /* start of string matched by subsubRE */
302302 char *sep; /* end of string matched by subsubRE */
303303 char *oldssp; /* previous ssp */
304 char *dp;
305304
306305 AT("diss", start, stop, startst, stopst);
307306 sp = start;
360359 esub = es - 1;
361360 /* did innards match? */
362361 if (slow(m, sp, rest, ssub, esub) != NULL) {
363 dp = dissect(m, sp, rest, ssub, esub);
362 char *dp = dissect(m, sp, rest, ssub, esub);
364363 assert(dp == rest);
365364 } else /* no */
366365 assert(sp == rest);
398397 }
399398 assert(sep == rest); /* must exhaust substring */
400399 assert(slow(m, ssp, sep, ssub, esub) == rest);
401 dp = dissect(m, ssp, sep, ssub, esub);
402 assert(dp == sep);
400 {
401 char *dp = dissect(m, ssp, sep, ssub, esub);
402 assert(dp == sep);
403 }
403404 sp = rest;
404405 break;
405406 case OCH_:
433434 else
434435 assert(OP(m->g->strip[esub]) == O_CH);
435436 }
436 dp = dissect(m, sp, rest, ssub, esub);
437 assert(dp == rest);
437 {
438 char *dp = dissect(m, sp, rest, ssub, esub);
439 assert(dp == rest);
440 }
438441 sp = rest;
439442 break;
440443 case O_PLUS:
115115 return false;
116116 }
117117
118 static bool Timeout = false;
119118 static void TimeOutHandler(int Sig) {
120 Timeout = true;
121119 }
122120
123121 static void SetMemoryLimits (unsigned size)
232230
233231 // Install a timeout handler.
234232 if (secondsToWait) {
235 Timeout = false;
236233 Act.sa_sigaction = 0;
237234 Act.sa_handler = TimeOutHandler;
238235 sigemptyset(&Act.sa_mask);
261261 bool HasImmOffset = false;
262262 bool HasShift = false;
263263 bool isLdStMul = false;
264 bool isPopPush = false;
265264 unsigned Opc = Entry.NarrowOpc1;
266265 unsigned OpNum = 3; // First 'rest' of operands.
267266 switch (Entry.WideOpc) {
300299 unsigned Mode = MI->getOperand(1).getImm();
301300 if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
302301 Opc = Entry.NarrowOpc2;
303 isPopPush = true;
304302 OpNum = 2;
305303 } else if (Entry.WideOpc == ARM::t2LDM_RET ||
306304 !isARMLowRegister(BaseReg) ||
28752875
28762876 SmallVector MemOpChains;
28772877 for (unsigned i = 0; i != NumOps; ++i) {
2878 bool inMem = false;
28792878 SDValue Arg = Outs[i].Val;
28802879 ISD::ArgFlagsTy Flags = Outs[i].Flags;
28812880
29622961 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
29632962 isPPC64, isTailCall, false, MemOpChains,
29642963 TailCallArguments, dl);
2965 inMem = true;
29662964 }
29672965 ArgOffset += PtrByteSize;
29682966 break;
30023000 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
30033001 isPPC64, isTailCall, false, MemOpChains,
30043002 TailCallArguments, dl);
3005 inMem = true;
30063003 }
30073004 if (isPPC64)
30083005 ArgOffset += 8;
118118 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
119119 << getFunctionNumber() << '_' << MO.getIndex();
120120
121 MCSymbol *NegatedSymbol = 0;
122121 switch (MO.getTargetFlags()) {
123122 default:
124123 llvm_unreachable("Unknown target flag on GV operand");
128127 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
129128 break;
130129 // Subtract the pic base.
131 NegatedSymbol = GetPICBaseSymbol();
130 GetPICBaseSymbol();
132131 break;
133132 }
134133
51975197 DebugLoc dl = Op.getDebugLoc();
51985198 EVT VT = Op.getValueType();
51995199 EVT EltVT = VT;
5200 unsigned EltNum = 1;
52015200 if (VT.isVector()) {
52025201 EltVT = VT.getVectorElementType();
5203 EltNum = VT.getVectorNumElements();
5202 VT.getVectorNumElements();
52045203 }
52055204 std::vector CV;
52065205 if (EltVT == MVT::f64) {
225225 bool isUs = isImmUs(Offset);
226226 unsigned FramePtr = XCore::R10;
227227
228 MachineInstr *New = 0;
229228 if (!isUs) {
230229 if (!RS) {
231230 std::string msg;
238237 loadConstant(MBB, II, ScratchReg, Offset, dl);
239238 switch (MI.getOpcode()) {
240239 case XCore::LDWFI:
241 New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
240 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
242241 .addReg(FramePtr)
243242 .addReg(ScratchReg, RegState::Kill);
244243 break;
245244 case XCore::STWFI:
246 New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
245 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
247246 .addReg(Reg, getKillRegState(isKill))
248247 .addReg(FramePtr)
249248 .addReg(ScratchReg, RegState::Kill);
250249 break;
251250 case XCore::LDAWFI:
252 New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
251 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
253252 .addReg(FramePtr)
254253 .addReg(ScratchReg, RegState::Kill);
255254 break;
259258 } else {
260259 switch (MI.getOpcode()) {
261260 case XCore::LDWFI:
262 New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
261 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
263262 .addReg(FramePtr)
264263 .addImm(Offset);
265264 break;
266265 case XCore::STWFI:
267 New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
266 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
268267 .addReg(Reg, getKillRegState(isKill))
269268 .addReg(FramePtr)
270269 .addImm(Offset);
271270 break;
272271 case XCore::LDAWFI:
273 New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
272 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
274273 .addReg(FramePtr)
275274 .addImm(Offset);
276275 break;
190190 if (&*BBI != SI)
191191 return;
192192
193 bool RemovedPreds = false;
194
195193 // Ok, we have this really simple case, walk the PHI operands, looking for
196194 // constants. Walk from the end to remove operands from the end when
197195 // possible, and to avoid invalidating "i".
203201 RevectorBlockTo(PN->getIncomingBlock(i-1),
204202 SI->getSuccessor(DestCase));
205203 ++NumSwThread;
206 RemovedPreds = true;
207204
208205 // If there were two predecessors before this simplification, or if the
209206 // PHI node contained all the same value except for the one we just