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Merging r227809: ------------------------------------------------------------------------ r227809 | jvoung | 2015-02-02 08:56:50 -0800 (Mon, 02 Feb 2015) | 16 lines Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0. Summary: Previously it only avoided optimizing signed comparisons to 0. Sometimes the DAGCombiner will optimize the unsigned comparisons to 0 before it gets to the peephole pass, but sometimes it doesn't. Fix for PR22373. Test Plan: test/CodeGen/ARM/sub-cmp-peephole.ll Reviewers: jfb, manmanren Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D7274 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@227864 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
2 changed file(s) with 83 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
23992399 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
24002400 // Conservatively refuse to convert an instruction which isn't in the same
24012401 // BB as the comparison.
2402 // For CMPri, we need to check Sub, thus we can't return here.
2402 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2403 // Thus we cannot return here.
24032404 if (CmpInstr->getOpcode() == ARM::CMPri ||
24042405 CmpInstr->getOpcode() == ARM::t2CMPri)
24052406 MI = nullptr;
24782479 case ARM::t2EORrr:
24792480 case ARM::t2EORri: {
24802481 // Scan forward for the use of CPSR
2481 // When checking against MI: if it's a conditional code requires
2482 // checking of V bit, then this is not safe to do.
2482 // When checking against MI: if it's a conditional code that requires
2483 // checking of the V bit or C bit, then this is not safe to do.
24832484 // It is safe to remove CmpInstr if CPSR is redefined or killed.
24842485 // If we are done with the basic block, we need to check whether CPSR is
24852486 // live-out.
25462547 OperandsToUpdate.push_back(
25472548 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
25482549 }
2549 } else
2550 } else {
2551 // No Sub, so this is x = y, z; cmp x, 0.
25502552 switch (CC) {
2551 default:
2553 case ARMCC::EQ: // Z
2554 case ARMCC::NE: // Z
2555 case ARMCC::MI: // N
2556 case ARMCC::PL: // N
2557 case ARMCC::AL: // none
25522558 // CPSR can be used multiple times, we should continue.
25532559 break;
2554 case ARMCC::VS:
2555 case ARMCC::VC:
2556 case ARMCC::GE:
2557 case ARMCC::LT:
2558 case ARMCC::GT:
2559 case ARMCC::LE:
2560 case ARMCC::HS: // C
2561 case ARMCC::LO: // C
2562 case ARMCC::VS: // V
2563 case ARMCC::VC: // V
2564 case ARMCC::HI: // C Z
2565 case ARMCC::LS: // C Z
2566 case ARMCC::GE: // N V
2567 case ARMCC::LT: // N V
2568 case ARMCC::GT: // Z N V
2569 case ARMCC::LE: // Z N V
2570 // The instruction uses the V bit or C bit which is not safe.
25602571 return false;
25612572 }
2573 }
25622574 }
25632575 }
25642576
8585
8686 if.end11: ; preds = %num2long.exit
8787 ret i32 23
88 }
89
90 ; When considering the producer of cmp's src as the subsuming instruction,
91 ; only consider that when the comparison is to 0.
92 define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
93 entry:
94 ; CHECK-LABEL: cmp_src_nonzero:
95 ; CHECK: sub
96 ; CHECK: cmp
97 %sub = sub i32 %a, %b
98 %cmp = icmp eq i32 %sub, 17
99 %ret = select i1 %cmp, i32 %x, i32 %y
100 ret i32 %ret
88101 }
89102
90103 define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
143156 store i32 %sub, i32* @t
144157 ret double %ret
145158 }
159
160 declare void @abort()
161 declare void @exit(i32)
162
163 ; If the comparison uses the V bit (signed overflow/underflow), we can't
164 ; omit the comparison.
165 define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
166 entry:
167 ; CHECK-LABEL: cmp_slt0
168 ; CHECK: sub
169 ; CHECK: cmp
170 ; CHECK: bge
171 %load = load i32* @t, align 4
172 %sub = sub i32 %load, 17
173 %cmp = icmp slt i32 %sub, 0
174 br i1 %cmp, label %if.then, label %if.else
175
176 if.then:
177 call void @abort()
178 unreachable
179
180 if.else:
181 call void @exit(i32 0)
182 unreachable
183 }
184
185 ; Same for the C bit. (Note the ult X, 0 is trivially
186 ; false, so the DAG combiner may or may not optimize it).
187 define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
188 entry:
189 ; CHECK-LABEL: cmp_ult0
190 ; CHECK: sub
191 ; CHECK: cmp
192 ; CHECK: bhs
193 %load = load i32* @t, align 4
194 %sub = sub i32 %load, 17
195 %cmp = icmp ult i32 %sub, 0
196 br i1 %cmp, label %if.then, label %if.else
197
198 if.then:
199 call void @abort()
200 unreachable
201
202 if.else:
203 call void @exit(i32 0)
204 unreachable
205 }