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[ARM] Add remaining miscellaneous MVE instructions. This final batch includes the tail-predicated versions of the low-overhead loop instructions (LETP); the VPSEL instruction to select between two vector registers based on the predicate mask without having to open a VPT block; and VPNOT which complements the predicate mask in place. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364292 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
6 changed file(s) with 451 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
38943894
38953895 let Defs = [P0];
38963896 }
3897
3898 def MVE_VPSEL : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
3899 "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
3900 bits<4> Qn;
3901 bits<4> Qd;
3902 bits<4> Qm;
3903
3904 let Inst{28} = 0b1;
3905 let Inst{25-23} = 0b100;
3906 let Inst{22} = Qd{3};
3907 let Inst{21-20} = 0b11;
3908 let Inst{19-17} = Qn{2-0};
3909 let Inst{16} = 0b1;
3910 let Inst{15-13} = Qd{2-0};
3911 let Inst{12-9} = 0b0111;
3912 let Inst{8} = 0b1;
3913 let Inst{7} = Qn{3};
3914 let Inst{6} = 0b0;
3915 let Inst{5} = Qm{3};
3916 let Inst{4} = 0b0;
3917 let Inst{3-1} = Qm{2-0};
3918 let Inst{0} = 0b1;
3919 }
3920
3921 foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
3922 "i8", "i16", "i32", "f16", "f32"] in
3923 def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
3924 (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
3925
3926 def MVE_VPNOT : MVE_p<(outs), (ins), NoItinerary,
3927 "vpnot", "", "", vpred_n, "", []> {
3928 let Inst{31-0} = 0b11111110001100010000111101001101;
3929 let Unpredictable{19-17} = 0b111;
3930 let Unpredictable{12} = 0b1;
3931 let Unpredictable{7} = 0b1;
3932 let Unpredictable{5} = 0b1;
3933 let Defs = [P0];
3934 let Uses = [P0];
3935
3936 let Constraints = "";
3937 }
3938
3939 class MVE_loltp_start size>
3940 : t2LOL<(outs GPRlr:$LR), iops, asm, ops> {
3941 bits<4> Rn;
3942 let Predicates = [HasMVEInt];
3943 let Inst{22} = 0b0;
3944 let Inst{21-20} = size;
3945 let Inst{19-16} = Rn{3-0};
3946 let Inst{12} = 0b0;
3947 }
3948
3949 class MVE_DLSTP size>
3950 : MVE_loltp_start<(ins rGPR:$Rn), asm, "$LR, $Rn", size> {
3951 let Inst{13} = 0b1;
3952 let Inst{11-1} = 0b00000000000;
3953 let Unpredictable{10-1} = 0b1111111111;
3954 }
3955
3956 class MVE_WLSTP size>
3957 : MVE_loltp_start<(ins rGPR:$Rn, wlslabel_u11:$label),
3958 asm, "$LR, $Rn, $label", size> {
3959 bits<11> label;
3960 let Inst{13} = 0b0;
3961 let Inst{11} = label{0};
3962 let Inst{10-1} = label{10-1};
3963 }
3964
3965 def MVE_DLSTP_8 : MVE_DLSTP<"dlstp.8", 0b00>;
3966 def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
3967 def MVE_DLSTP_32 : MVE_DLSTP<"dlstp.32", 0b10>;
3968 def MVE_DLSTP_64 : MVE_DLSTP<"dlstp.64", 0b11>;
3969
3970 def MVE_WLSTP_8 : MVE_WLSTP<"wlstp.8", 0b00>;
3971 def MVE_WLSTP_16 : MVE_WLSTP<"wlstp.16", 0b01>;
3972 def MVE_WLSTP_32 : MVE_WLSTP<"wlstp.32", 0b10>;
3973 def MVE_WLSTP_64 : MVE_WLSTP<"wlstp.64", 0b11>;
3974
3975 class MVE_loltp_end
3976 : t2LOL {
3977 let Predicates = [HasMVEInt];
3978 let Inst{22-21} = 0b00;
3979 let Inst{19-16} = 0b1111;
3980 let Inst{12} = 0b0;
3981 }
3982
3983 def MVE_LETP : MVE_loltp_end<(outs GPRlr:$LRout),
3984 (ins GPRlr:$LRin, lelabel_u11:$label),
3985 "letp", "$LRin, $label"> {
3986 bits<11> label;
3987 let Inst{20} = 0b1;
3988 let Inst{13} = 0b0;
3989 let Inst{11} = label{0};
3990 let Inst{10-1} = label{10-1};
3991 }
3992
3993 def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
3994 let Inst{20} = 0b0;
3995 let Inst{13} = 0b1;
3996 let Inst{11-1} = 0b00000000000;
3997 let Unpredictable{21-20} = 0b11;
3998 let Unpredictable{11-1} = 0b11111111111;
3999 }
371371 def bflabel_s12 : BFLabelOp<"true", "false", "12", "ARM::fixup_bfc_target">;
372372 def bflabel_s16 : BFLabelOp<"true", "false", "16", "ARM::fixup_bf_target">;
373373 def bflabel_s18 : BFLabelOp<"true", "false", "18", "ARM::fixup_bfl_target">;
374 def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls">;
375 def lelabel_u11 : BFLabelOp<"false", "true", "11", "ARM::fixup_le">;
374
375 def wlslabel_u11_asmoperand : AsmOperandClass {
376 let Name = "WLSLabel";
377 let RenderMethod = "addImmOperands";
378 let PredicateMethod = "isUnsignedOffset<11, 1>";
379 let DiagnosticString =
380 "loop end is out of range or not a positive multiple of 2";
381 }
382 def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls"> {
383 let ParserMatchClass = wlslabel_u11_asmoperand;
384 }
385 def lelabel_u11_asmoperand : AsmOperandClass {
386 let Name = "LELabel";
387 let RenderMethod = "addImmOperands";
388 let PredicateMethod = "isLEOffset";
389 let DiagnosticString =
390 "loop start is out of range or not a negative multiple of 2";
391 }
392 def lelabel_u11 : BFLabelOp<"false", "true", "11", "ARM::fixup_le"> {
393 let ParserMatchClass = lelabel_u11_asmoperand;
394 }
376395
377396 def bfafter_target : Operand {
378397 let EncoderMethod = "getBFAfterTargetOpValue";
10121012 return false;
10131013 }
10141014
1015 // checks whether this operand is an offset suitable for the LE /
1016 // LETP instructions in Arm v8.1M
1017 bool isLEOffset() const {
1018 if (!isImm()) return false;
1019 if (isa(Imm.Val)) return true;
1020 if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) {
1021 int64_t Val = CE->getValue();
1022 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1023 }
1024 return false;
1025 }
1026
10151027 // checks whether this operand is a memory operand computed as an offset
10161028 // applied to PC. the offset may have 8 bits of magnitude and is represented
10171029 // with two bits of shift. textually it may be either [pc, #imm], #imm or
62126224 Mnemonic == "vmule" || Mnemonic == "vmult" ||
62136225 Mnemonic == "vrintne" ||
62146226 Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6227 Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
62156228 Mnemonic.startswith("vq")))) {
62166229 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
62176230 if (CC != ~0U) {
62606273 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
62616274 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
62626275 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6263 Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6276 Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
62646277 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
62656278 if (CC != ~0U) {
62666279 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
63366349 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
63376350 (hasMVE() &&
63386351 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6339 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) {
6352 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6353 Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6354 Mnemonic.startswith("letp")))) {
63406355 // These mnemonics are never predicable
63416356 CanAcceptPredicationCode = false;
63426357 } else if (!isThumb()) {
65986613 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
65996614 return true;
66006615
6601 if (Mnemonic.startswith("vctp"))
6616 if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
66026617 return false;
66036618
66046619 if (Mnemonic.startswith("vmov") &&
77397754 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
77407755 "predicable, but condition "
77417756 "code specified");
7742 break;
7743 }
7744 case ARM::t2WLS: {
7745 int idx = Opcode == ARM::t2WLS ? 3 : 4;
7746 if (!static_cast(*Operands[idx]).isUnsignedOffset<11, 1>())
7747 return Error(Operands[idx]->getStartLoc(),
7748 "loop end is out of range or not a positive multiple of 2");
7749 break;
7750 }
7751 case ARM::t2LEUpdate: {
7752 if (Inst.getOperand(2).isImm() &&
7753 !(Inst.getOperand(2).getImm() < 0 &&
7754 Inst.getOperand(2).getImm() >= -4094 &&
7755 (Inst.getOperand(2).getImm() & 1) == 0))
7756 return Error(Operands[2]->getStartLoc(),
7757 "loop start is out of range or not a negative multiple of 2");
77587757 break;
77597758 }
77607759 case ARM::t2BFi:
59475947 const void *Decoder) {
59485948 DecodeStatus S = MCDisassembler::Success;
59495949
5950 if (Inst.getOpcode() == ARM::MVE_LCTP)
5951 return S;
5952
59505953 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
59515954 fieldFromInstruction(Insn, 1, 10) << 1;
59525955 switch (Inst.getOpcode()) {
59535956 case ARM::t2LEUpdate:
5957 case ARM::MVE_LETP:
59545958 Inst.addOperand(MCOperand::createReg(ARM::LR));
59555959 Inst.addOperand(MCOperand::createReg(ARM::LR));
59565960 LLVM_FALLTHROUGH;
59605964 return MCDisassembler::Fail;
59615965 break;
59625966 case ARM::t2WLS:
5967 case ARM::MVE_WLSTP_8:
5968 case ARM::MVE_WLSTP_16:
5969 case ARM::MVE_WLSTP_32:
5970 case ARM::MVE_WLSTP_64:
59635971 Inst.addOperand(MCOperand::createReg(ARM::LR));
59645972 if (!Check(S,
59655973 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
59695977 return MCDisassembler::Fail;
59705978 break;
59715979 case ARM::t2DLS:
5980 case ARM::MVE_DLSTP_8:
5981 case ARM::MVE_DLSTP_16:
5982 case ARM::MVE_DLSTP_32:
5983 case ARM::MVE_DLSTP_64:
59725984 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
59735985 if (Rn == 0xF) {
5974 return MCDisassembler::Fail;
5986 // Enforce all the rest of the instruction bits in LCTP, which
5987 // won't have been reliably checked based on LCTP's own tablegen
5988 // record, because we came to this decode by a roundabout route.
5989 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
5990 if ((Insn & ~SBZMask) != CanonicalLCTP)
5991 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
5992 if (Insn != CanonicalLCTP)
5993 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
5994
5995 Inst.setOpcode(ARM::MVE_LCTP);
59755996 } else {
59765997 Inst.addOperand(MCOperand::createReg(ARM::LR));
59775998 if (!Check(S, DecoderGPRRegisterClass(Inst,
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t
6 # RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
7
8 # CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f]
9 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
10 vpsel q0, q5, q2
11
12 # CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f]
13 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
14 vpnot
15
16 # CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3]
17 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
18 wlstp.8 lr, r0, #1668
19
20 # CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3]
21 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
22 wlstp.16 lr, r0, #1668
23
24 # CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd]
25 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
26 wlstp.32 lr, r4, #2706
27
28 # CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd]
29 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
30 wlstp.64 lr, lr, #3026
31
32 # CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6]
33 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
34 wlstp.8 lr, r5, #3436
35
36 # CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2]
37 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
38 wlstp.16 lr, r1, #1060
39
40 # CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7]
41 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
42 wlstp.32 lr, r7, #4036
43
44 # CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9]
45 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
46 wlstp.8 lr, r1, #538
47
48 # CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2]
49 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
50 wlstp.8 lr, r10, #1404
51
52 # CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2]
53 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
54 wlstp.8 lr, r10, #1408
55
56 # CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc]
57 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
58 wlstp.8 lr, r10, #2358
59
60 # CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf]
61 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
62 wlstp.8 lr, r10, #4086
63
64 # CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca]
65 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
66 wlstp.8 lr, r11, #1442
67
68 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
69 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
70 wlstp.8 lr, r10, #1443
71
72 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
73 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
74 wlstp.8 lr, r10, #4096
75
76 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
77 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
78 wlstp.8 lr, sp, #1442
79
80 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
81 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
82 wlstp.16 lr, sp, #1442
83
84 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
85 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
86 wlstp.32 r10, r11, #1442
87
88 # CHECK: wlstp.8 lr, r1, .Lendloop @ encoding: [0x01'A',0xf0'A',0x01'A',0xc0'A']
89 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
90 wlstp.8 lr, r1, .Lendloop
91
92 # CHECK: wlstp.16 lr, r2, .Lendloop @ encoding: [0x12'A',0xf0'A',0x01'A',0xc0'A']
93 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
94 wlstp.16 lr, r2, .Lendloop
95
96 # CHECK: wlstp.32 lr, r3, .Lendloop @ encoding: [0x23'A',0xf0'A',0x01'A',0xc0'A']
97 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
98 wlstp.32 lr, r3, .Lendloop
99
100 # CHECK: wlstp.64 lr, r5, .Lendloop @ encoding: [0x35'A',0xf0'A',0x01'A',0xc0'A']
101 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
102 wlstp.64 lr, r5, .Lendloop
103
104 # CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0]
105 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
106 dlstp.8 lr, r5
107
108 # CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0]
109 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
110 dlstp.16 lr, r5
111
112 # CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0]
113 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
114 dlstp.32 lr, r7
115
116 # CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0]
117 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
118 dlstp.64 lr, r2
119
120 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
121 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
122 dlstp.64 lr, sp
123
124 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
125 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
126 dlstp.64 r10, r0
127
128 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
129 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
130 dlstp.64 lr, pc
131
132 # CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
133 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
134 letp lr, #-2
135
136 # CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
137 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
138 letp lr, #-8
139
140 # CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
141 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
142 letp lr, #-4094
143
144 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
145 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
146 letp r0, #-8
147
148 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
149 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
150 letp lr, #8
151
152 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
153 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
154 letp lr, #-4096
155
156 # CHECK: letp lr, .Lstartloop @ encoding: [0x1f'A',0xf0'A',0x01'A',0xc0'A']
157 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
158 letp lr, .Lstartloop
159
160 # CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
161 # ERROR-NOMVE: [[@LINE+1]]:1: error: instruction requires: mve
162 lctp
163
164 # CHECK: it eq @ encoding: [0x08,0xbf]
165 it eq
166 # CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
167 # ERROR-NOMVE: [[@LINE+1]]:1: error: instruction requires: mve
168 lctpeq
169
170 vpste
171 vpselt.s16 q0, q1, q2
172 vpsele.i32 q0, q1, q2
173 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
174 # CHECK: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
175 # CHECK: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
0 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
1 # RUN: FileCheck --check-prefix=ERROR < %t %s
2 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
3 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
4
5 # CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f]
6 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
7 [0x3b,0xfe,0x05,0x0f]
8
9 # CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f]
10 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
11 [0x31,0xfe,0x4d,0x0f]
12
13 # CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3]
14 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
15 [0x00,0xf0,0x43,0xc3]
16
17 # CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3]
18 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
19 [0x10,0xf0,0x43,0xc3]
20
21 # CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd]
22 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
23 [0x24,0xf0,0x49,0xcd]
24
25 # CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd]
26 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
27 [0x3e,0xf0,0xe9,0xcd]
28
29 # CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6]
30 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
31 [0x05,0xf0,0xb7,0xc6]
32
33 # CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2]
34 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
35 [0x11,0xf0,0x13,0xc2]
36
37 # CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7]
38 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
39 [0x27,0xf0,0xe3,0xc7]
40
41 # CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9]
42 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
43 [0x01,0xf0,0x0d,0xc9]
44
45 # CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2]
46 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
47 [0x0a,0xf0,0xbf,0xc2]
48
49 # CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2]
50 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
51 [0x0a,0xf0,0xc1,0xc2]
52
53 # CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc]
54 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
55 [0x0a,0xf0,0x9b,0xcc]
56
57 # CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf]
58 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
59 [0x0a,0xf0,0xfb,0xcf]
60
61 # CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca]
62 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
63 [0x0b,0xf0,0xd1,0xca]
64
65 # CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0]
66 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
67 [0x05,0xf0,0x01,0xe0]
68
69 # CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0]
70 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
71 [0x15,0xf0,0x01,0xe0]
72
73 # CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0]
74 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
75 [0x27,0xf0,0x01,0xe0]
76
77 # CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0]
78 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
79 [0x32,0xf0,0x01,0xe0]
80
81 # CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
82 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
83 [0x1f,0xf0,0x01,0xc8]
84
85 # CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
86 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
87 [0x1f,0xf0,0x05,0xc0]
88
89 # CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
90 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
91 [0x1f,0xf0,0xff,0xcf]
92
93 # CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
94 # CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
95 [0x0f,0xf0,0x01,0xe0]
96
97 # ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
98 [0x1f,0xf0,0x01,0xe0]
99
100 # ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
101 [0x4f,0xf0,0x01,0xe0]
102
103 # The following tests have to go last because of the NOMVE-NOT checks.
104
105 # CHECK: it eq @ encoding: [0x08,0xbf]
106 # CHECK-NOMVE: it eq @ encoding: [0x08,0xbf]
107 [0x08,0xbf]
108 # CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
109 # CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
110 [0x0f,0xf0,0x01,0xe0]