llvm.org GIT mirror llvm / c219c0a
Merge from mainline. When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a sub-register being used. The MachineOperand::getSubReg() method is only valid for virtual registers, so we have to recover the sub-register index manually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@80552 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 11 years ago
2 changed file(s) with 84 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
802802 ReusedOp NewOp = Op;
803803 Reuses.erase(Reuses.begin()+ro);
804804
805 // MI may be using only a sub-register of PhysRegUsed.
806 unsigned RealPhysRegUsed = MI->getOperand(NewOp.Operand).getReg();
807 unsigned SubIdx = 0;
808 assert(TargetRegisterInfo::isPhysicalRegister(RealPhysRegUsed) &&
809 "A reuse cannot be a virtual register");
810 if (PRRU != RealPhysRegUsed) {
811 // What was the sub-register index?
812 unsigned SubReg;
813 for (SubIdx = 1; (SubReg = TRI->getSubReg(PRRU, SubIdx)); SubIdx++)
814 if (SubReg == RealPhysRegUsed)
815 break;
816 assert(SubReg == RealPhysRegUsed &&
817 "Operand physreg is not a sub-register of PhysRegUsed");
818 }
819
805820 // Ok, we're going to try to reload the assigned physreg into the
806821 // slot that we were supposed to in the first place. However, that
807822 // register could hold a reuse. Check to see if it conflicts or
834849 Spills.ClobberPhysReg(NewPhysReg);
835850 Spills.ClobberPhysReg(NewOp.PhysRegReused);
836851
837 unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg();
838852 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
839853 MI->getOperand(NewOp.Operand).setReg(RReg);
840854 MI->getOperand(NewOp.Operand).setSubReg(0);
0 ; RUN: llvm-as < %s | llc -march=x86
1 ; PR4753
2
3 ; This function has a sub-register reuse undone.
4
5 @uint8 = external global i32 ; [#uses=3]
6
7 declare signext i8 @foo(i32, i8 signext) nounwind readnone
8
9 declare signext i8 @bar(i32, i8 signext) nounwind readnone
10
11 define i32 @uint80(i8 signext %p_52) nounwind {
12 entry:
13 %0 = sext i8 %p_52 to i16 ; [#uses=1]
14 %1 = tail call i32 @func_24(i16 zeroext %0, i8 signext ptrtoint (i8 (i32, i8)* @foo to i8)) nounwind; [#uses=1]
15 %2 = trunc i32 %1 to i8 ; [#uses=1]
16 %3 = or i8 %2, 1 ; [#uses=1]
17 %4 = tail call i32 @safe(i32 1) nounwind ; [#uses=0]
18 %5 = tail call i32 @func_24(i16 zeroext 0, i8 signext undef) nounwind; [#uses=1]
19 %6 = trunc i32 %5 to i8 ; [#uses=1]
20 %7 = xor i8 %3, %p_52 ; [#uses=1]
21 %8 = xor i8 %7, %6 ; [#uses=1]
22 %9 = icmp ne i8 %p_52, 0 ; [#uses=1]
23 %10 = zext i1 %9 to i8 ; [#uses=1]
24 %11 = tail call i32 @func_24(i16 zeroext ptrtoint (i8 (i32, i8)* @bar to i16), i8 signext %10) nounwind; [#uses=1]
25 %12 = tail call i32 @func_24(i16 zeroext 0, i8 signext 1) nounwind; [#uses=0]
26 br i1 undef, label %bb2, label %bb
27
28 bb: ; preds = %entry
29 br i1 undef, label %bb2, label %bb3
30
31 bb2: ; preds = %bb, %entry
32 br label %bb3
33
34 bb3: ; preds = %bb2, %bb
35 %iftmp.2.0 = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; [#uses=1]
36 %13 = icmp ne i32 %11, %iftmp.2.0 ; [#uses=1]
37 %14 = tail call i32 @safe(i32 -2) nounwind ; [#uses=0]
38 %15 = zext i1 %13 to i8 ; [#uses=1]
39 %16 = tail call signext i8 @func_53(i8 signext undef, i8 signext 1, i8 signext %15, i8 signext %8) nounwind; [#uses=0]
40 br i1 undef, label %bb5, label %bb4
41
42 bb4: ; preds = %bb3
43 %17 = volatile load i32* @uint8, align 4 ; [#uses=0]
44 br label %bb5
45
46 bb5: ; preds = %bb4, %bb3
47 %18 = volatile load i32* @uint8, align 4 ; [#uses=0]
48 %19 = sext i8 undef to i16 ; [#uses=1]
49 %20 = tail call i32 @func_24(i16 zeroext %19, i8 signext 1) nounwind; [#uses=0]
50 br i1 undef, label %return, label %bb6.preheader
51
52 bb6.preheader: ; preds = %bb5
53 %21 = sext i8 %p_52 to i32 ; [#uses=1]
54 %22 = volatile load i32* @uint8, align 4 ; [#uses=0]
55 %23 = tail call i32 (...)* @safefuncts(i32 %21, i32 1) nounwind; [#uses=0]
56 unreachable
57
58 return: ; preds = %bb5
59 ret i32 undef
60 }
61
62 declare i32 @func_24(i16 zeroext, i8 signext)
63
64 declare i32 @safe(i32)
65
66 declare signext i8 @func_53(i8 signext, i8 signext, i8 signext, i8 signext)
67
68 declare i32 @safefuncts(...)