llvm.org GIT mirror llvm / c1fa073
MIRParser: Allow regclass specification on operand You can now define the register class of a virtual register on the operand itself avoiding the need to use a "registers:" block. Example: "%0:gr64 = COPY %rax" Differential Revision: https://reviews.llvm.org/D22398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 3 years ago
7 changed file(s) with 154 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
4040 using namespace llvm;
4141
4242 PerFunctionMIParsingState::PerFunctionMIParsingState(MachineFunction &MF,
43 SourceMgr &SM, const SlotMapping &IRSlots)
44 : MF(MF), SM(&SM), IRSlots(IRSlots) {
43 SourceMgr &SM, const SlotMapping &IRSlots,
44 const Name2RegClassMap &Names2RegClasses,
45 const Name2RegBankMap &Names2RegBanks)
46 : MF(MF), SM(&SM), IRSlots(IRSlots), Names2RegClasses(Names2RegClasses),
47 Names2RegBanks(Names2RegBanks) {
4548 }
4649
4750 VRegInfo &PerFunctionMIParsingState::getVRegInfo(unsigned Num) {
138141 bool parseVirtualRegister(VRegInfo *&Info);
139142 bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
140143 bool parseRegisterFlag(unsigned &Flags);
144 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
141145 bool parseSubRegisterIndex(unsigned &SubReg);
142146 bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx);
143147 bool parseRegisterOperand(MachineOperand &Dest,
877881 }
878882 }
879883
884 bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
885 if (Token.isNot(MIToken::Identifier))
886 return error("expected a register class or register bank name");
887 StringRef::iterator Loc = Token.location();
888 StringRef Name = Token.stringValue();
889
890 // Was it a register class?
891 auto RCNameI = PFS.Names2RegClasses.find(Name);
892 if (RCNameI != PFS.Names2RegClasses.end()) {
893 lex();
894 const TargetRegisterClass &RC = *RCNameI->getValue();
895
896 switch (RegInfo.Kind) {
897 case VRegInfo::UNKNOWN:
898 case VRegInfo::NORMAL:
899 RegInfo.Kind = VRegInfo::NORMAL;
900 if (RegInfo.Explicit && RegInfo.D.RC != &RC) {
901 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
902 return error(Loc, Twine("conflicting register classes, previously: ") +
903 Twine(TRI.getRegClassName(RegInfo.D.RC)));
904 }
905 RegInfo.D.RC = &RC;
906 RegInfo.Explicit = true;
907 return false;
908
909 case VRegInfo::GENERIC:
910 case VRegInfo::REGBANK:
911 return error(Loc, "register class specification on generic register");
912 }
913 llvm_unreachable("Unexpected register kind");
914 }
915
916 // Should be a register bank.
917 auto RBNameI = PFS.Names2RegBanks.find(Name);
918 lex();
919 if (RBNameI == PFS.Names2RegBanks.end())
920 return error(Loc, "expected a register class or register bank name");
921
922 const RegisterBank &RegBank = *RBNameI->getValue();
923 switch (RegInfo.Kind) {
924 case VRegInfo::UNKNOWN:
925 case VRegInfo::GENERIC:
926 case VRegInfo::REGBANK:
927 RegInfo.Kind = VRegInfo::REGBANK;
928 if (RegInfo.Explicit && RegInfo.D.RegBank != &RegBank)
929 return error(Loc, "conflicting register banks");
930 RegInfo.D.RegBank = &RegBank;
931 RegInfo.Explicit = true;
932 return false;
933
934 case VRegInfo::NORMAL:
935 return error(Loc, "register class specification on normal register");
936 }
937 llvm_unreachable("Unexpected register kind");
938 }
939
880940 bool MIParser::parseRegisterFlag(unsigned &Flags) {
881941 const unsigned OldFlags = Flags;
882942 switch (Token.kind()) {
10021062 return true;
10031063 if (!TargetRegisterInfo::isVirtualRegister(Reg))
10041064 return error("subregister index expects a virtual register");
1065 }
1066 if (Token.is(MIToken::colon)) {
1067 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1068 return error("register class specification expects a virtual register");
1069 lex();
1070 if (parseRegisterClassOrBank(*RegInfo))
1071 return true;
10051072 }
10061073 MachineRegisterInfo &MRI = MF.getRegInfo();
10071074 if ((Flags & RegState::Define) == 0) {
4444 unsigned PreferredReg = 0;
4545 };
4646
47 typedef StringMap Name2RegClassMap;
48 typedef StringMap Name2RegBankMap;
49
4750 struct PerFunctionMIParsingState {
4851 BumpPtrAllocator Allocator;
4952 MachineFunction &MF;
5053 SourceMgr *SM;
5154 const SlotMapping &IRSlots;
55 const Name2RegClassMap &Names2RegClasses;
56 const Name2RegBankMap &Names2RegBanks;
5257
5358 DenseMap MBBSlots;
5459 DenseMap VRegInfos;
5863 DenseMap JumpTableSlots;
5964
6065 PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
61 const SlotMapping &IRSlots);
66 const SlotMapping &IRSlots,
67 const Name2RegClassMap &Names2RegClasses,
68 const Name2RegBankMap &Names2RegBanks);
6269
6370 VRegInfo &getVRegInfo(unsigned VReg);
6471 };
5454 StringMap> Functions;
5555 SlotMapping IRSlots;
5656 /// Maps from register class names to register classes.
57 StringMap Names2RegClasses;
57 Name2RegClassMap Names2RegClasses;
5858 /// Maps from register bank names to register banks.
59 StringMap Names2RegBanks;
59 Name2RegBankMap Names2RegBanks;
6060
6161 public:
6262 MIRParserImpl(std::unique_ptr Contents, StringRef Filename,
324324 return error(Twine("no machine function information for function '") +
325325 MF.getName() + "' in the MIR file");
326326 // TODO: Recreate the machine function.
327 initNames2RegClasses(MF);
328 initNames2RegBanks(MF);
327329 const yaml::MachineFunction &YamlMF = *It->getValue();
328330 if (YamlMF.Alignment)
329331 MF.setAlignment(YamlMF.Alignment);
337339 if (YamlMF.Selected)
338340 MF.getProperties().set(MachineFunctionProperties::Property::Selected);
339341
340 PerFunctionMIParsingState PFS(MF, SM, IRSlots);
342 PerFunctionMIParsingState PFS(MF, SM, IRSlots, Names2RegClasses,
343 Names2RegBanks);
341344 if (parseRegisterInfo(PFS, YamlMF))
342345 return true;
343346 if (!YamlMF.Constants.empty()) {
817820
818821 const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,
819822 StringRef Name) {
820 initNames2RegClasses(MF);
821823 auto RegClassInfo = Names2RegClasses.find(Name);
822824 if (RegClassInfo == Names2RegClasses.end())
823825 return nullptr;
826828
827829 const RegisterBank *MIRParserImpl::getRegBank(const MachineFunction &MF,
828830 StringRef Name) {
829 initNames2RegBanks(MF);
830831 auto RegBankInfo = Names2RegBanks.find(Name);
831832 if (RegBankInfo == Names2RegBanks.end())
832833 return nullptr;
0 # RUN: llc -o - %s -mtriple=aarch64-- -run-pass=none | FileCheck %s
1 # REQUIRES: global-isel
2 # Test various aspects of register bank specification on machine operands.
3 --- |
4 define void @func() { ret void }
5 ...
6 ---
7 # CHECK-LABEL: name: func
8 # CHECK: registers:
9 # CHECK: - { id: 0, class: gpr }
10 # CHECK: - { id: 1, class: fpr }
11 name: func
12 body: |
13 bb.0:
14 %0 : gpr(s64) = COPY %x9
15 %x9 = COPY %0
16
17 %3 : fpr(s64) = COPY %d0
18 %d1 = COPY %3 : fpr
19 ...
0 # RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s
1 # This test ensures that an error is reported for specifying the register class
2 # of a physical register.
3 --- |
4 define void @t() { ret void }
5 ...
6 ---
7 name: t
8 body: |
9 bb.0:
10 ; CHECK: [[@LINE+1]]:10: register class specification expects a virtual register
11 %eax : gr32 = COPY %rdx
12 ...
0 # RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s
1 # This test ensures that an error is reported for specifying the register class
2 # of a physical register.
3 --- |
4 define void @t() { ret void }
5 ...
6 ---
7 name: t
8 body: |
9 bb.0:
10 %0 : gr32 = COPY %rdx
11 ; CHECK: [[@LINE+1]]:24: conflicting register classes, previously: GR32
12 NOOP implicit %0 : gr32_abcd
13 ...
0 # RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
1 # Test various aspects of register class specification on machine operands.
2 --- |
3 define void @func() { ret void }
4 ...
5 ---
6 # CHECK-LABEL: name: func
7 # CHECK: registers:
8 # CHECK: - { id: 0, class: gr32 }
9 # CHECK: - { id: 1, class: gr64 }
10 # CHECK: - { id: 2, class: gr32 }
11 # CHECK: - { id: 3, class: gr16 }
12 name: func
13 body: |
14 bb.0:
15 %0 : gr32 = COPY %rax
16 %1.sub_32bit : gr64 = COPY %eax
17 %rdx = COPY %1
18 %2 = COPY %ecx
19 %ecx = COPY %2 : gr32
20
21 %3 : gr16 = COPY %bx
22 %bx = COPY %3 : gr16
23 ...