llvm.org GIT mirror llvm / c1ef24c
ms inline asm: Don't add x86 segment registers to the clobber list. Clang tries to check the clobber list but doesn't list segment registers in its x86 register list. This fixes PR20343. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303 91177308-0d34-0410-b5e6-96231b3b80d8 Nico Weber 6 years ago
3 changed file(s) with 10 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
163163 unsigned &ErrorInfo,
164164 bool MatchingInlineAsm) = 0;
165165
166 /// Allows targets to let registers opt out of clobber lists.
167 virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
168
166169 /// Allow a target to add special case operand matching for things that
167170 /// tblgen doesn't/can't handle effectively. For example, literal
168171 /// immediates on ARM. TableGen expects a token operand, but the parser
45094509 continue;
45104510
45114511 // Register operand.
4512 if (Operand.isReg() && !Operand.needAddressOf()) {
4512 if (Operand.isReg() && !Operand.needAddressOf() &&
4513 !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
45134514 unsigned NumDefs = Desc.getNumDefs();
45144515 // Clobber.
45154516 if (NumDefs && Operand.getMCOperandNum() < NumDefs)
695695 unsigned &ErrorInfo,
696696 bool MatchingInlineAsm) override;
697697
698 virtual bool OmitRegisterFromClobberLists(unsigned RegNo) override;
699
698700 /// doSrcDstMatch - Returns true if operands are matching in their
699701 /// word size (%si and %di, %esi and %edi, etc.). Order depends on
700702 /// the parsing mode (Intel vs. AT&T).
25192521 return true;
25202522 }
25212523
2524 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
2525 return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
2526 }
25222527
25232528 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
25242529 StringRef IDVal = DirectiveID.getIdentifier();