llvm.org GIT mirror llvm / c1dcb8d
Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 6 years ago
4 changed file(s) with 10 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
3838 /// layout, etc.
3939 ///
4040 TargetMachine &TM;
41 const TargetInstrInfo *TII;
4241
4342 static char ID;
4443 Filler(TargetMachine &tm)
45 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
44 : MachineFunctionPass(ID), TM(tm) { }
4645
4746 virtual const char *getPassName() const {
4847 return "SPARC Delay Slot Filler";
126125 ++FilledSlots;
127126 Changed = true;
128127
128 const TargetInstrInfo *TII = TM.getInstrInfo();
129129 if (D == MBB.end())
130130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
131131 else
165165 if (J->getOpcode() == SP::RESTORErr
166166 || J->getOpcode() == SP::RESTOREri) {
167167 // change retl to ret.
168 slot->setDesc(TII->get(SP::RET));
168 slot->setDesc(TM.getInstrInfo()->get(SP::RET));
169169 return J;
170170 }
171171 }
475475 if (isDelayFiller(MBB, PrevInst))
476476 return false;
477477
478 const TargetInstrInfo *TII = TM.getInstrInfo();
479
478480 switch (PrevInst->getOpcode()) {
479481 default: break;
480482 case SP::ADDrr:
2828
2929 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
3030 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31 RI(ST, *this), Subtarget(ST) {
31 RI(ST), Subtarget(ST) {
3232 }
3333
3434 /// isLoadFromStackSlot - If the specified machine instruction is a direct
3333 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
3434 cl::desc("Reserve application registers (%g2-%g4)"));
3535
36 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
37 const TargetInstrInfo &tii)
38 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
36 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
37 : SparcGenRegisterInfo(SP::I7), Subtarget(st) {
3938 }
4039
4140 const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
107106 } else {
108107 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
109108 // scavenge a register here instead of reserving G1 all of the time.
109 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
110110 unsigned OffHi = (unsigned)Offset >> 10U;
111111 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
112112 // Emit G1 = G1 + I6
2626
2727 struct SparcRegisterInfo : public SparcGenRegisterInfo {
2828 SparcSubtarget &Subtarget;
29 const TargetInstrInfo &TII;
3029
31 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
30 SparcRegisterInfo(SparcSubtarget &st);
3231
3332 /// Code Generation virtual methods...
3433 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;