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Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 9 years ago
6 changed file(s) with 18 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
873873 case ARM::PICSTRB: Opcode = ARM::STRB; break;
874874 case ARM::PICSTRH: Opcode = ARM::STRH; break;
875875 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
876 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
876 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
877877 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
878878 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
879879 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
10791079 default:
10801080 return false;
10811081 case ARM::LDRi12:
1082 case ARM::LDRB:
1082 case ARM::LDRBi12:
10831083 case ARM::LDRD:
10841084 case ARM::LDRH:
10851085 case ARM::LDRSB:
10981098 default:
10991099 return false;
11001100 case ARM::LDRi12:
1101 case ARM::LDRB:
1101 case ARM::LDRBi12:
11021102 case ARM::LDRD:
11031103 case ARM::LDRH:
11041104 case ARM::LDRSB:
13751375 // return false for everything else.
13761376 unsigned Opc = MI->getOpcode();
13771377 switch (Opc) {
1378 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRB:
1378 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
13791379 case ARM::STR: case ARM::STRH: case ARM::STRB:
13801380 case ARM::t2LDRi12: case ARM::t2LDRi8:
13811381 case ARM::t2STRi12: case ARM::t2STRi8:
745745 RC = ARM::GPRRegisterClass;
746746 break;
747747 case MVT::i8:
748 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
748 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
749749 RC = ARM::GPRRegisterClass;
750750 break;
751751 case MVT::i32:
773773 if (isFloat)
774774 Offset /= 4;
775775
776 // The thumb and floating point instructions both take 2 operands, ARM takes
777 // another register.
778776 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
779777 TII.get(Opc), ResultReg)
780778 .addReg(Base).addImm(Offset));
3838 return ARM::LDRH;
3939 case ARM::LDRB_PRE:
4040 case ARM::LDRB_POST:
41 return ARM::LDRB;
41 return ARM::LDRBi12;
4242 case ARM::LDRSH_PRE:
4343 case ARM::LDRSH_POST:
4444 return ARM::LDRSH;
13991399 // Load
14001400
14011401
1402 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
1403 UnOpFrag<(load node:$Src)>>;
1402 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
1403 UnOpFrag<(load node:$Src)>>;
1404 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
1405 UnOpFrag<(zextloadi8 node:$Src)>>;
14041406
14051407 // Special LDR for loads from non-pc-relative constpools.
14061408 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
14191421 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
14201422 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
14211423 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1422
1423 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
1424 IIC_iLoad_bh_r, "ldrb", "\t$dst, $addr",
1425 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
14261424
14271425 // Loads with sign extension
14281426 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
31643162 Requires<[IsARM, IsDarwin]>;
31653163
31663164 // zextload i1 -> zextload i8
3167 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
3165 //def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
3166 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3167 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
31683168
31693169 // extload -> zextload
3170 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
3171 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
3170 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3171 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3172 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3173 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3174
31723175 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
31733176
31743177 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;