llvm.org GIT mirror llvm / c19f159
[release_36] Cherry-pick r232179. Original commit message: [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes. This patch fixes a bug in the shuffle lowering logic implemented by function 'lowerV2X128VectorShuffle'. The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR nodes. The problematic expansion only occurs when the shuffle mask M has an 'undef' element at position 2, and M is equivalent to mask <0,1,4,5>. In that case, the algorithm propagates the wrong vector to one of the two new EXTRACT_SUBVECTOR nodes. Example: ;; define <4 x double> @test(<4 x double> %A, <4 x double> %B) { entry: %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5> ret <4 x double> %0 } ;; Before this patch, llc (-mattr=+avx) generated: vinsertf128 $1, %xmm0, %ymm0, %ymm0 With this patch, llc correctly generates: vinsertf128 $1, %xmm1, %ymm0, %ymm0 Added test lower-vec-shuffle-bug.ll Differential Revision: http://reviews.llvm.org/D8259 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@232753 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 5 years ago
2 changed file(s) with 44 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
1009310093 VT.getVectorNumElements() / 2);
1009410094 // Check for patterns which can be matched with a single insert of a 128-bit
1009510095 // subvector.
10096 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10097 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10096 bool OnlyUsesV1 = isShuffleEquivalent(Mask, 0, 1, 0, 1);
10097 if (OnlyUsesV1 || isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
1009810098 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
1009910099 DAG.getIntPtrConstant(0));
1010010100 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10101 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10101 OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));
1010210102 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
1010310103 }
1010410104 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
0 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
1
2 define <4 x double> @test1(<4 x double> %A, <4 x double> %B) {
3 ; CHECK-LABEL: test1:
4 ; CHECK: # BB#0:
5 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
6 ; CHECK-NEXT: retq
7 entry:
8 %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32>
9 ret <4 x double> %0
10 }
11
12 define <4 x double> @test2(<4 x double> %A, <4 x double> %B) {
13 ; CHECK-LABEL: test2:
14 ; CHECK: # BB#0:
15 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
16 ; CHECK-NEXT: retq
17 entry:
18 %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32>
19 ret <4 x double> %0
20 }
21
22 define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
23 ; CHECK-LABEL: test3:
24 ; CHECK: # BB#0:
25 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
26 ; CHECK-NEXT: retq
27 entry:
28 %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32>
29 ret <4 x double> %0
30 }
31
32 define <4 x double> @test4(<4 x double> %A, <4 x double> %B) {
33 ; CHECK-LABEL: test4:
34 ; CHECK: # BB#0:
35 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
36 ; CHECK-NEXT: retq
37 entry:
38 %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32>
39 ret <4 x double> %0
40 }