llvm.org GIT mirror llvm / c18f4ef
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 7 years ago
17 changed file(s) with 706 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
634634 /// which do not reference a specific memory location should be less than
635635 /// this value. Those that do must not be less than this value, and can
636636 /// be used with SelectionDAG::getMemIntrinsicNode.
637 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150;
637 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+180;
638638
639639 //===--------------------------------------------------------------------===//
640640 /// MemIndexedMode enum - This enum defines the load / store indexed
830830 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
831831 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
832832 }
833 bool isMemVZ32() const {
834 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
835 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
836 }
837 bool isMemVZ64() const {
838 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
839 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
840 }
841
842 bool isMem512() const {
843 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
844 }
833845
834846 bool isAbsMem() const {
835847 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
887899 addMemOperands(Inst, N);
888900 }
889901 void addMemVY64Operands(MCInst &Inst, unsigned N) const {
902 addMemOperands(Inst, N);
903 }
904
905 void addMemVZ32Operands(MCInst &Inst, unsigned N) const {
906 addMemOperands(Inst, N);
907 }
908 void addMemVZ64Operands(MCInst &Inst, unsigned N) const {
909 addMemOperands(Inst, N);
910 }
911 void addMem512Operands(MCInst &Inst, unsigned N) const {
890912 addMemOperands(Inst, N);
891913 }
892914
284284 return;
285285 case TYPE_XMM256:
286286 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
287 return;
288 case TYPE_XMM512:
289 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
287290 return;
288291 case TYPE_REL8:
289292 isBranch = true;
442445 EA_BASES_64BIT
443446 REGS_XMM
444447 REGS_YMM
448 REGS_ZMM
445449 #undef ENTRY
446450 }
447451 } else {
564568 case TYPE_XMM64:
565569 case TYPE_XMM128:
566570 case TYPE_XMM256:
571 case TYPE_XMM512:
567572 case TYPE_DEBUGREG:
568573 case TYPE_CONTROLREG:
569574 return translateRMRegister(mcInst, insn);
12541254 return prefix##_EAX + index; \
12551255 case TYPE_R64: \
12561256 return prefix##_RAX + index; \
1257 case TYPE_XMM512: \
1258 return prefix##_ZMM0 + index; \
12571259 case TYPE_XMM256: \
12581260 return prefix##_YMM0 + index; \
12591261 case TYPE_XMM128: \
218218 ENTRY(XMM12) \
219219 ENTRY(XMM13) \
220220 ENTRY(XMM14) \
221 ENTRY(XMM15)
221 ENTRY(XMM15) \
222 ENTRY(XMM16) \
223 ENTRY(XMM17) \
224 ENTRY(XMM18) \
225 ENTRY(XMM19) \
226 ENTRY(XMM20) \
227 ENTRY(XMM21) \
228 ENTRY(XMM22) \
229 ENTRY(XMM23) \
230 ENTRY(XMM24) \
231 ENTRY(XMM25) \
232 ENTRY(XMM26) \
233 ENTRY(XMM27) \
234 ENTRY(XMM28) \
235 ENTRY(XMM29) \
236 ENTRY(XMM30) \
237 ENTRY(XMM31)
222238
223239 #define REGS_YMM \
224240 ENTRY(YMM0) \
236252 ENTRY(YMM12) \
237253 ENTRY(YMM13) \
238254 ENTRY(YMM14) \
239 ENTRY(YMM15)
255 ENTRY(YMM15) \
256 ENTRY(YMM16) \
257 ENTRY(YMM17) \
258 ENTRY(YMM18) \
259 ENTRY(YMM19) \
260 ENTRY(YMM20) \
261 ENTRY(YMM21) \
262 ENTRY(YMM22) \
263 ENTRY(YMM23) \
264 ENTRY(YMM24) \
265 ENTRY(YMM25) \
266 ENTRY(YMM26) \
267 ENTRY(YMM27) \
268 ENTRY(YMM28) \
269 ENTRY(YMM29) \
270 ENTRY(YMM30) \
271 ENTRY(YMM31)
272
273 #define REGS_ZMM \
274 ENTRY(ZMM0) \
275 ENTRY(ZMM1) \
276 ENTRY(ZMM2) \
277 ENTRY(ZMM3) \
278 ENTRY(ZMM4) \
279 ENTRY(ZMM5) \
280 ENTRY(ZMM6) \
281 ENTRY(ZMM7) \
282 ENTRY(ZMM8) \
283 ENTRY(ZMM9) \
284 ENTRY(ZMM10) \
285 ENTRY(ZMM11) \
286 ENTRY(ZMM12) \
287 ENTRY(ZMM13) \
288 ENTRY(ZMM14) \
289 ENTRY(ZMM15) \
290 ENTRY(ZMM16) \
291 ENTRY(ZMM17) \
292 ENTRY(ZMM18) \
293 ENTRY(ZMM19) \
294 ENTRY(ZMM20) \
295 ENTRY(ZMM21) \
296 ENTRY(ZMM22) \
297 ENTRY(ZMM23) \
298 ENTRY(ZMM24) \
299 ENTRY(ZMM25) \
300 ENTRY(ZMM26) \
301 ENTRY(ZMM27) \
302 ENTRY(ZMM28) \
303 ENTRY(ZMM29) \
304 ENTRY(ZMM30) \
305 ENTRY(ZMM31)
240306
241307 #define REGS_SEGMENT \
242308 ENTRY(ES) \
284350 REGS_MMX \
285351 REGS_XMM \
286352 REGS_YMM \
353 REGS_ZMM \
287354 REGS_SEGMENT \
288355 REGS_DEBUG \
289356 REGS_CONTROL \
318385 ALL_EA_BASES
319386 REGS_XMM
320387 REGS_YMM
388 REGS_ZMM
321389 #undef ENTRY
322390 SIB_INDEX_max
323391 } SIBIndex;
115115 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
116116 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
117117 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
118 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize")
119
118 ENUM_ENTRY(IC_VEX_L_W, 3, "requires VEX, L and W") \
119 ENUM_ENTRY(IC_VEX_L_W_XS, 4, "requires VEX, L, W and XS prefix") \
120 ENUM_ENTRY(IC_VEX_L_W_XD, 4, "requires VEX, L, W and XD prefix") \
121 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 4, "requires VEX, L, W and OpSize") \
122 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
123 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
124 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
125 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
126 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
127 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
128 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
129 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
130 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
131 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
132 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
133 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
134 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
135 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
136 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
137 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
138 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
139 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
140 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
141 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
142 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
143 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
144 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
145 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
146 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
147 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
148 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
149 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
150 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
151 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
152 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
153 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
154 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
155 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
156 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
157 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
158 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
159 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
160 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
161 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
162 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
163 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
164 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
165 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
166 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
167 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
168 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
169 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
170 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
171 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
172 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
173 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
174 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
175 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
176 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
177 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
178 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
179 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
180 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
181 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
182 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
183 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
184 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
185 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
186 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
187 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
188 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
189 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
190 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
191 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
192 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
193 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
194 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
195 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
196 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
197 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
198 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
199 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
200 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
201 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
202 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
203 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
204 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
205 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
206 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
207 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
208 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
209 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
210 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
211 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
212 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
213 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
214 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
215 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
216 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
217 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and OpSize")
120218
121219 #define ENUM_ENTRY(n, r, d) n,
122220 typedef enum {
223321 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
224322 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
225323 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
324 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
226325 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \
227326 ENUM_ENTRY(ENCODING_CW, "2-byte") \
228327 ENUM_ENTRY(ENCODING_CD, "4-byte") \
320419 ENUM_ENTRY(TYPE_XMM64, "8-byte") \
321420 ENUM_ENTRY(TYPE_XMM128, "16-byte") \
322421 ENUM_ENTRY(TYPE_XMM256, "32-byte") \
422 ENUM_ENTRY(TYPE_XMM512, "64-byte") \
423 ENUM_ENTRY(TYPE_VK8, "8-bit") \
424 ENUM_ENTRY(TYPE_VK16, "16-bit") \
323425 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
324426 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
325427 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
6464 void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
6565 printMemReference(MI, OpNo, O);
6666 }
67 void printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
68 printMemReference(MI, OpNo, O);
69 }
6770 void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
6871 printMemReference(MI, OpNo, O);
6972 }
7982 void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
8083 printMemReference(MI, OpNo, O);
8184 }
85 void printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
86 printMemReference(MI, OpNo, O);
87 }
8288 };
8389
8490 }
6868 O << "YMMWORD PTR ";
6969 printMemReference(MI, OpNo, O);
7070 }
71 void printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
72 O << "ZMMWORD PTR ";
73 printMemReference(MI, OpNo, O);
74 }
7175 void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
7276 O << "DWORD PTR ";
7377 printMemReference(MI, OpNo, O);
8892 O << "YMMWORD PTR ";
8993 printMemReference(MI, OpNo, O);
9094 }
95 void printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 O << "ZMMWORD PTR ";
97 printMemReference(MI, OpNo, O);
98 }
9199 };
92100
93101 }
461461 // prefix. Usually used for scalar instructions. Needed by disassembler.
462462 VEX_LIG = 1U << 6,
463463
464 // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field
465 // with following encoding:
466 // - 00 V128
467 // - 01 V256
468 // - 10 V512
469 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
470 // this will save 1 tsflag bit
471
472 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
473 // syntax support up to 32 512-bit register operands and up to 7 16-bit
474 // mask operands as well as source operand data swizzling/memory operand
475 // conversion, eviction hint, and rounding mode.
476 EVEX = 1U << 7,
477
478 // EVEX_K - Set if this instruction requires masking
479 EVEX_K = 1U << 8,
480
481 // EVEX_Z - Set if this instruction has EVEX.Z field set.
482 EVEX_Z = 1U << 9,
483
484 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
485 EVEX_L2 = 1U << 10,
486
487 // EVEX_B - Set if this instruction has EVEX.B field set.
488 EVEX_B = 1U << 11,
489
490 // EVEX_CD8E - compressed disp8 form, element-size
491 EVEX_CD8EShift = VEXShift + 12,
492 EVEX_CD8EMask = 3,
493
494 // EVEX_CD8V - compressed disp8 form, vector-width
495 EVEX_CD8VShift = EVEX_CD8EShift + 2,
496 EVEX_CD8VMask = 7,
497
464498 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
465499 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
466500 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
467501 /// storing a classifier in the imm8 field. To simplify our implementation,
468502 /// we handle this by storeing the classifier in the opcode field and using
469503 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
470 Has3DNow0F0FOpcode = 1U << 7,
504 Has3DNow0F0FOpcode = 1U << 17,
471505
472506 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
473507 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
474 MemOp4 = 1U << 8,
508 MemOp4 = 1U << 18,
475509
476510 /// XOP - Opcode prefix used by XOP instructions.
477 XOP = 1U << 9
511 XOP = 1U << 19
478512
479513 };
480514
532566 unsigned CurOp = 0;
533567 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
534568 ++CurOp;
535 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
536 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
569 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
570 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
571 // Special case for AVX-512 GATHER with 2 TIED_TO operands
572 // Skip the first 2 operands: dst, mask_wb
573 CurOp += 2;
574 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
575 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
537576 // Special case for GATHER with 2 TIED_TO operands
538577 // Skip the first 2 operands: dst, mask_wb
539578 CurOp += 2;
540 }
579 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
580 // SCATTER
581 ++CurOp;
541582 return CurOp;
542583 }
543584
568609 case X86II::MRMSrcMem: {
569610 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
570611 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
612 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
613 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
571614 unsigned FirstMemOp = 1;
572615 if (HasVEX_4V)
573616 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
574617 if (HasMemOp4)
575618 ++FirstMemOp;// Skip the register source (which is encoded in I8IMM).
576
619 if (HasEVEX_K)
620 ++FirstMemOp;// Skip the mask register
577621 // FIXME: Maybe lea should have its own form? This is a horrible hack.
578622 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
579623 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
610654 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
611655 /// higher) register? e.g. r8, xmm8, xmm13, etc.
612656 inline bool isX86_64ExtendedReg(unsigned RegNo) {
657 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) ||
658 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) ||
659 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) ||
660 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) ||
661 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) ||
662 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31))
663 return true;
664
613665 switch (RegNo) {
614666 default: break;
615667 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
620672 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
621673 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
622674 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
623 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
624 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
625 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
626 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
627675 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
628676 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
629677 return true;
630678 }
631679 return false;
632680 }
681
682 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
683 /// registers? e.g. zmm21, etc.
684 static inline bool is32ExtendedReg(unsigned RegNo) {
685 return ((RegNo > X86::XMM15 && RegNo <= X86::XMM31) ||
686 (RegNo > X86::YMM15 && RegNo <= X86::YMM31) ||
687 (RegNo > X86::ZMM15 && RegNo <= X86::ZMM31));
688 }
689
633690
634691 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
635692 return (reg == X86::SPL || reg == X86::BPL ||
8989 "Enable AVX-512 instructions",
9090 [FeatureAVX2]>;
9191 def FeatureERI : SubtargetFeature<"avx-512-eri", "HasERI", "true",
92 "Enable AVX-512 Exponential and Reciprocal Instructions">;
92 "Enable AVX-512 Exponential and Reciprocal Instructions",
93 [FeatureAVX512]>;
9394 def FeatureCDI : SubtargetFeature<"avx-512-cdi", "HasCDI", "true",
94 "Enable AVX-512 Conflict Detection Instructions">;
95 "Enable AVX-512 Conflict Detection Instructions",
96 [FeatureAVX512]>;
9597 def FeaturePFI : SubtargetFeature<"avx-512-pfi", "HasPFI", "true",
96 "Enable AVX-512 PreFetch Instructions">;
98 "Enable AVX-512 PreFetch Instructions",
99 [FeatureAVX512]>;
97100
98101 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
99102 "Enable packed carry-less multiplication instructions",
9595 def SSEPackedDouble : Domain<2>;
9696 def SSEPackedInt : Domain<3>;
9797
98 // Class specifying the vector form of the decompressed
99 // displacement of 8-bit.
100 class CD8VForm val> {
101 bits<3> Value = val;
102 }
103 def CD8VF : CD8VForm<0>; // v := VL
104 def CD8VH : CD8VForm<1>; // v := VL/2
105 def CD8VQ : CD8VForm<2>; // v := VL/4
106 def CD8VO : CD8VForm<3>; // v := VL/8
107 def CD8VT1 : CD8VForm<4>; // v := 1
108 def CD8VT2 : CD8VForm<5>; // v := 2
109 def CD8VT4 : CD8VForm<6>; // v := 4
110 def CD8VT8 : CD8VForm<7>; // v := 8
111
98112 // Prefix byte classes which are used to indicate to the ad-hoc machine code
99113 // emitter that various prefix bytes are required.
100114 class OpSize { bit hasOpSizePrefix = 1; }
131145 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
132146 class VEX_L { bit hasVEX_L = 1; }
133147 class VEX_LIG { bit ignoresVEX_L = 1; }
148 class EVEX : VEX { bit hasEVEXPrefix = 1; }
149 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
150 class EVEX_K { bit hasEVEX_K = 1; }
151 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
152 class EVEX_B { bit hasEVEX_B = 1; }
153 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
154 class EVEX_CD8 {
155 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
156 !if(!eq(esize, 16), 0b01,
157 !if(!eq(esize, 32), 0b10,
158 !if(!eq(esize, 64), 0b11, ?))));
159 bits<3> EVEX_CD8V = form.Value;
160 }
134161 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
135162 class MemOp4 { bit hasMemOp4Prefix = 1; }
136163 class XOP { bit hasXOP_Prefix = 1; }
176203 // to be encoded in a immediate field?
177204 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
178205 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
206 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
207 bit hasEVEX_K = 0; // Does this inst require masking?
208 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
209 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
210 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
211 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
212 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
179213 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
180214 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
181215 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
199233 let TSFlags{37} = hasVEX_i8ImmReg;
200234 let TSFlags{38} = hasVEX_L;
201235 let TSFlags{39} = ignoresVEX_L;
202 let TSFlags{40} = has3DNow0F0FOpcode;
203 let TSFlags{41} = hasMemOp4Prefix;
204 let TSFlags{42} = hasXOP_Prefix;
236 let TSFlags{40} = hasEVEXPrefix;
237 let TSFlags{41} = hasEVEX_K;
238 let TSFlags{42} = hasEVEX_Z;
239 let TSFlags{43} = hasEVEX_L2;
240 let TSFlags{44} = hasEVEX_B;
241 let TSFlags{46-45} = EVEX_CD8E;
242 let TSFlags{49-47} = EVEX_CD8V;
243 let TSFlags{50} = has3DNow0F0FOpcode;
244 let TSFlags{51} = hasMemOp4Prefix;
245 let TSFlags{52} = hasXOP_Prefix;
205246 }
206247
207248 class PseudoI pattern>
552593 : Ii8, TA, OpSize,
553594 Requires<[HasAVX2]>;
554595
596
597 // AVX-512 Instruction Templates:
598 // Instructions introduced in AVX-512 (no SSE equivalent forms)
599 //
600 // AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
601 // AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
602 // AVX512PDI - AVX-512 instructions with TB, OpSize, double packed.
603 // AVX512PSI - AVX-512 instructions with TB, single packed.
604 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
605 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
606 // AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain.
607 // AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes.
608
609 class AVX5128I o, Format F, dag outs, dag ins, string asm,
610 list pattern, InstrItinClass itin = NoItinerary>
611 : I, T8, OpSize,
612 Requires<[HasAVX512]>;
613 class AVX512XS8I o, Format F, dag outs, dag ins, string asm,
614 list pattern, InstrItinClass itin = NoItinerary>
615 : I, T8XS,
616 Requires<[HasAVX512]>;
617 class AVX512XSI o, Format F, dag outs, dag ins, string asm,
618 list pattern, InstrItinClass itin = NoItinerary>
619 : I, XS,
620 Requires<[HasAVX512]>;
621 class AVX512XDI o, Format F, dag outs, dag ins, string asm,
622 list pattern, InstrItinClass itin = NoItinerary>
623 : I, XD,
624 Requires<[HasAVX512]>;
625 class AVX512BI o, Format F, dag outs, dag ins, string asm,
626 list pattern, InstrItinClass itin = NoItinerary>
627 : I, TB, OpSize,
628 Requires<[HasAVX512]>;
629 class AVX512BIi8 o, Format F, dag outs, dag ins, string asm,
630 list pattern, InstrItinClass itin = NoItinerary>
631 : Ii8, TB, OpSize,
632 Requires<[HasAVX512]>;
633 class AVX512SI o, Format F, dag outs, dag ins, string asm,
634 list pattern, InstrItinClass itin = NoItinerary>
635 : I, TB, OpSize,
636 Requires<[HasAVX512]>;
637 class AVX512AIi8 o, Format F, dag outs, dag ins, string asm,
638 list pattern, InstrItinClass itin = NoItinerary>
639 : Ii8, TA, OpSize,
640 Requires<[HasAVX512]>;
641 class AVX512Ii8 o, Format F, dag outs, dag ins, string asm,
642 list pattern, InstrItinClass itin = NoItinerary>
643 : Ii8,
644 Requires<[HasAVX512]>;
645 class AVX512PDI o, Format F, dag outs, dag ins, string asm,
646 list pattern, InstrItinClass itin = NoItinerary>
647 : I, TB,
648 OpSize, Requires<[HasAVX512]>;
649 class AVX512PSI o, Format F, dag outs, dag ins, string asm,
650 list pattern, InstrItinClass itin = NoItinerary>
651 : I, TB,
652 Requires<[HasAVX512]>;
653 class AVX512PIi8 o, Format F, dag outs, dag ins, string asm,
654 list pattern, Domain d, InstrItinClass itin = NoItinerary>
655 : Ii8, Requires<[HasAVX512]>;
656 class AVX512PI o, Format F, dag outs, dag ins, string asm,
657 list pattern, Domain d, InstrItinClass itin = NoItinerary>
658 : I, Requires<[HasAVX512]>;
659 class AVX512FMA3 o, Format F, dag outs, dag ins, string asm,
660 listpattern, InstrItinClass itin = NoItinerary>
661 : I, T8,
662 OpSize, EVEX_4V, Requires<[HasAVX512]>;
663
555664 // AES Instruction Templates:
556665 //
557666 // AES8I
316316 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
317317 }
318318
319 def X86MemVZ64Operand : AsmOperandClass {
320 let Name = "MemVZ64"; let PredicateMethod = "isMemVZ64";
321 }
322 def X86MemVZ32Operand : AsmOperandClass {
323 let Name = "MemVZ32"; let PredicateMethod = "isMemVZ32";
324 }
325 def X86Mem512AsmOperand : AsmOperandClass {
326 let Name = "Mem512"; let PredicateMethod = "isMem512";
327 }
328
319329 def X86AbsMemAsmOperand : AsmOperandClass {
320330 let Name = "AbsMem";
321331 let SuperClasses = [X86MemAsmOperand];
344354 let ParserMatchClass = X86Mem128AsmOperand; }
345355 def i256mem : X86MemOperand<"printi256mem"> {
346356 let ParserMatchClass = X86Mem256AsmOperand; }
357 def i512mem : X86MemOperand<"printi512mem"> {
358 let ParserMatchClass = X86Mem512AsmOperand; }
347359 def f32mem : X86MemOperand<"printf32mem"> {
348360 let ParserMatchClass = X86Mem32AsmOperand; }
349361 def f64mem : X86MemOperand<"printf64mem"> {
354366 let ParserMatchClass = X86Mem128AsmOperand; }
355367 def f256mem : X86MemOperand<"printf256mem">{
356368 let ParserMatchClass = X86Mem256AsmOperand; }
369 def f512mem : X86MemOperand<"printf512mem">{
370 let ParserMatchClass = X86Mem512AsmOperand; }
371 def v512mem : Operand {
372 let PrintMethod = "printf512mem";
373 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
374 let ParserMatchClass = X86Mem512AsmOperand; }
357375
358376 // Gather mem operands
359377 def vx32mem : X86MemOperand<"printi32mem">{
368386 def vy64mem : X86MemOperand<"printi64mem">{
369387 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
370388 let ParserMatchClass = X86MemVY64Operand; }
389 def vy64xmem : X86MemOperand<"printi64mem">{
390 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
391 let ParserMatchClass = X86MemVY64Operand; }
392 def vz32mem : X86MemOperand<"printi32mem">{
393 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
394 let ParserMatchClass = X86MemVZ32Operand; }
395 def vz64mem : X86MemOperand<"printi64mem">{
396 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
397 let ParserMatchClass = X86MemVZ64Operand; }
371398 }
372399
373400 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
589616 def HasAVX : Predicate<"Subtarget->hasAVX()">;
590617 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
591618 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
619 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
620 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
621 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
622 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
623 def HasCDI : Predicate<"Subtarget->hasCDI()">;
624 def HasPFI : Predicate<"Subtarget->hasPFI()">;
625 def HasEMI : Predicate<"Subtarget->hasERI()">;
592626
593627 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
594628 def HasAES : Predicate<"Subtarget->hasAES()">;
595629 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
596630 def HasFMA : Predicate<"Subtarget->hasFMA()">;
631 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
597632 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
598633 def HasXOP : Predicate<"Subtarget->hasXOP()">;
599634 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
700700 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
701701 return Reg;
702702 llvm_unreachable("Unexpected SIMD register");
703 return 0;
704 }
705
706 }
703 }
704
705 }
476476 HasBMI2 = false;
477477 HasRTM = false;
478478 HasHLE = false;
479 HasERI = false;
480 HasCDI = false;
481 HasPFI=false;
479482 HasADX = false;
480483 HasPRFCHW = false;
481484 HasRDSEED = false;
8080 case IC_64BIT_REXW_OPSIZE:
8181 return false;
8282 case IC_VEX:
83 return inheritsFrom(child, IC_VEX_W) ||
83 return inheritsFrom(child, IC_VEX_L_W) ||
84 inheritsFrom(child, IC_VEX_W) ||
8485 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
8586 case IC_VEX_XS:
86 return inheritsFrom(child, IC_VEX_W_XS) ||
87 return inheritsFrom(child, IC_VEX_L_W_XS) ||
88 inheritsFrom(child, IC_VEX_W_XS) ||
8789 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
8890 case IC_VEX_XD:
89 return inheritsFrom(child, IC_VEX_W_XD) ||
91 return inheritsFrom(child, IC_VEX_L_W_XD) ||
92 inheritsFrom(child, IC_VEX_W_XD) ||
9093 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
9194 case IC_VEX_OPSIZE:
92 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
95 return inheritsFrom(child, IC_VEX_L_W_OPSIZE) ||
96 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
9397 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
9498 case IC_VEX_W:
9599 case IC_VEX_W_XS:
99103 case IC_VEX_L:
100104 case IC_VEX_L_XS:
101105 case IC_VEX_L_XD:
102 return false;
103106 case IC_VEX_L_OPSIZE:
104 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
107 return false;
108 case IC_VEX_L_W:
109 case IC_VEX_L_W_XS:
110 case IC_VEX_L_W_XD:
105111 case IC_VEX_L_W_OPSIZE:
112 return false;
113 case IC_EVEX:
114 return inheritsFrom(child, IC_EVEX_W) ||
115 inheritsFrom(child, IC_EVEX_L_W);
116 case IC_EVEX_XS:
117 return inheritsFrom(child, IC_EVEX_W_XS) ||
118 inheritsFrom(child, IC_EVEX_L_W_XS);
119 case IC_EVEX_XD:
120 return inheritsFrom(child, IC_EVEX_W_XD) ||
121 inheritsFrom(child, IC_EVEX_L_W_XD);
122 case IC_EVEX_OPSIZE:
123 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
124 inheritsFrom(child, IC_EVEX_W_OPSIZE);
125 case IC_EVEX_W:
126 case IC_EVEX_W_XS:
127 case IC_EVEX_W_XD:
128 case IC_EVEX_W_OPSIZE:
129 return false;
130 case IC_EVEX_L:
131 case IC_EVEX_L_XS:
132 case IC_EVEX_L_XD:
133 case IC_EVEX_L_OPSIZE:
134 return false;
135 case IC_EVEX_L_W:
136 case IC_EVEX_L_W_XS:
137 case IC_EVEX_L_W_XD:
138 case IC_EVEX_L_W_OPSIZE:
139 return false;
140 case IC_EVEX_L2:
141 case IC_EVEX_L2_XS:
142 case IC_EVEX_L2_XD:
143 case IC_EVEX_L2_OPSIZE:
144 return false;
145 case IC_EVEX_L2_W:
146 case IC_EVEX_L2_W_XS:
147 case IC_EVEX_L2_W_XD:
148 case IC_EVEX_L2_W_OPSIZE:
149 return false;
150 case IC_EVEX_K:
151 return inheritsFrom(child, IC_EVEX_W_K) ||
152 inheritsFrom(child, IC_EVEX_L_W_K);
153 case IC_EVEX_XS_K:
154 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
155 inheritsFrom(child, IC_EVEX_L_W_XS_K);
156 case IC_EVEX_XD_K:
157 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
158 inheritsFrom(child, IC_EVEX_L_W_XD_K);
159 case IC_EVEX_OPSIZE_K:
160 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
161 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
162 case IC_EVEX_W_K:
163 case IC_EVEX_W_XS_K:
164 case IC_EVEX_W_XD_K:
165 case IC_EVEX_W_OPSIZE_K:
166 return false;
167 case IC_EVEX_L_K:
168 case IC_EVEX_L_XS_K:
169 case IC_EVEX_L_XD_K:
170 case IC_EVEX_L_OPSIZE_K:
171 return false;
172 case IC_EVEX_L_W_K:
173 case IC_EVEX_L_W_XS_K:
174 case IC_EVEX_L_W_XD_K:
175 case IC_EVEX_L_W_OPSIZE_K:
176 return false;
177 case IC_EVEX_L2_K:
178 case IC_EVEX_L2_B:
179 case IC_EVEX_L2_XS_K:
180 case IC_EVEX_L2_XD_K:
181 case IC_EVEX_L2_OPSIZE_K:
182 case IC_EVEX_L2_OPSIZE_B:
183 return false;
184 case IC_EVEX_L2_W_K:
185 case IC_EVEX_L2_W_XS_K:
186 case IC_EVEX_L2_W_XD_K:
187 case IC_EVEX_L2_W_OPSIZE_K:
188 case IC_EVEX_L2_W_OPSIZE_B:
106189 return false;
107190 default:
108191 llvm_unreachable("Unknown instruction class");
122205 assert(lower < IC_max);
123206
124207 #define ENUM_ENTRY(n, r, d) r,
208 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
209 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
125210 static int ranks[IC_max] = {
126211 INSTRUCTION_CONTEXTS
127212 };
128213 #undef ENUM_ENTRY
214 #undef ENUM_ENTRY_K_B
129215
130216 return (ranks[upper] > ranks[lower]);
131217 }
141227 default:
142228 llvm_unreachable("Unhandled instruction class");
143229 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
230 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
231 ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
144232 INSTRUCTION_CONTEXTS
145233 #undef ENUM_ENTRY
234 #undef ENUM_ENTRY_K_B
146235 }
147236 }
148237
235235 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
236236 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
237237 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
238 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
239 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
240 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
241 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
238242 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
239243 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
240244
294298 recogInstr.emitDecodePath(tables);
295299 }
296300
301 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
302 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
303
297304 InstructionContext RecognizableInstr::insnContext() const {
298305 InstructionContext insnContext;
299306
300 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
307 if (HasEVEXPrefix) {
308 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
309 char msg[200];
310 sprintf(msg, "Don't support VEX.L if EVEX_L2 is enabled: %s", Name.c_str());
311 llvm_unreachable(msg);
312 }
313 // VEX_L & VEX_W
314 if (HasVEX_LPrefix && HasVEX_WPrefix) {
315 if (HasOpSizePrefix)
316 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
317 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
318 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
319 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
320 Prefix == X86Local::TAXD)
321 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
322 else
323 insnContext = EVEX_KB(IC_EVEX_L_W);
324 } else if (HasVEX_LPrefix) {
325 // VEX_L
326 if (HasOpSizePrefix)
327 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
329 insnContext = EVEX_KB(IC_EVEX_L_XS);
330 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
331 Prefix == X86Local::TAXD)
332 insnContext = EVEX_KB(IC_EVEX_L_XD);
333 else
334 insnContext = EVEX_KB(IC_EVEX_L);
335 }
336 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 // EVEX_L2 & VEX_W
338 if (HasOpSizePrefix)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
340 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
341 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
342 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
343 Prefix == X86Local::TAXD)
344 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
345 else
346 insnContext = EVEX_KB(IC_EVEX_L2_W);
347 } else if (HasEVEX_L2Prefix) {
348 // EVEX_L2
349 if (HasOpSizePrefix)
350 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
351 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
352 Prefix == X86Local::TAXD)
353 insnContext = EVEX_KB(IC_EVEX_L2_XD);
354 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
355 insnContext = EVEX_KB(IC_EVEX_L2_XS);
356 else
357 insnContext = EVEX_KB(IC_EVEX_L2);
358 }
359 else if (HasVEX_WPrefix) {
360 // VEX_W
361 if (HasOpSizePrefix)
362 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364 insnContext = EVEX_KB(IC_EVEX_W_XS);
365 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366 Prefix == X86Local::TAXD)
367 insnContext = EVEX_KB(IC_EVEX_W_XD);
368 else
369 insnContext = EVEX_KB(IC_EVEX_W);
370 }
371 // No L, no W
372 else if (HasOpSizePrefix)
373 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
374 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
375 Prefix == X86Local::TAXD)
376 insnContext = EVEX_KB(IC_EVEX_XD);
377 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
378 insnContext = EVEX_KB(IC_EVEX_XS);
379 else
380 insnContext = EVEX_KB(IC_EVEX);
381 /// eof EVEX
382 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
301383 if (HasVEX_LPrefix && HasVEX_WPrefix) {
302384 if (HasOpSizePrefix)
303385 insnContext = IC_VEX_L_W_OPSIZE;
386 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
387 insnContext = IC_VEX_L_W_XS;
388 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
389 Prefix == X86Local::TAXD)
390 insnContext = IC_VEX_L_W_XD;
304391 else
305 llvm_unreachable("Don't support VEX.L and VEX.W together");
392 insnContext = IC_VEX_L_W;
306393 } else if (HasOpSizePrefix && HasVEX_LPrefix)
307394 insnContext = IC_VEX_L_OPSIZE;
308395 else if (HasOpSizePrefix && HasVEX_WPrefix)
640727 "Unexpected number of operands for MRMDestMemFrm");
641728 HANDLE_OPERAND(memory)
642729
730 if (HasEVEX_K)
731 HANDLE_OPERAND(writemaskRegister)
732
643733 if (HasVEX_4VPrefix)
644734 // FIXME: In AVX, the register below becomes the one encoded
645735 // in ModRMVEX and the one above the one in the VEX.VVVV field
664754
665755 HANDLE_OPERAND(roRegister)
666756
757 if (HasEVEX_K)
758 HANDLE_OPERAND(writemaskRegister)
759
667760 if (HasVEX_4VPrefix)
668761 // FIXME: In AVX, the register below becomes the one encoded
669762 // in ModRMVEX and the one above the one in the VEX.VVVV field
696789 "Unexpected number of operands for MRMSrcMemFrm");
697790
698791 HANDLE_OPERAND(roRegister)
792
793 if (HasEVEX_K)
794 HANDLE_OPERAND(writemaskRegister)
699795
700796 if (HasVEX_4VPrefix)
701797 // FIXME: In AVX, the register below becomes the one encoded
10781174 TYPE("i8imm", TYPE_IMM8)
10791175 TYPE("GR8", TYPE_R8)
10801176 TYPE("VR128", TYPE_XMM128)
1177 TYPE("VR128X", TYPE_XMM128)
10811178 TYPE("f128mem", TYPE_M128)
10821179 TYPE("f256mem", TYPE_M256)
1180 TYPE("f512mem", TYPE_M512)
10831181 TYPE("FR64", TYPE_XMM64)
1182 TYPE("FR64X", TYPE_XMM64)
10841183 TYPE("f64mem", TYPE_M64FP)
10851184 TYPE("sdmem", TYPE_M64FP)
10861185 TYPE("FR32", TYPE_XMM32)
1186 TYPE("FR32X", TYPE_XMM32)
10871187 TYPE("f32mem", TYPE_M32FP)
10881188 TYPE("ssmem", TYPE_M32FP)
10891189 TYPE("RST", TYPE_ST)
10901190 TYPE("i128mem", TYPE_M128)
10911191 TYPE("i256mem", TYPE_M256)
1192 TYPE("i512mem", TYPE_M512)
10921193 TYPE("i64i32imm_pcrel", TYPE_REL64)
10931194 TYPE("i16imm_pcrel", TYPE_REL16)
10941195 TYPE("i32imm_pcrel", TYPE_REL32)
11151216 TYPE("offset32", TYPE_MOFFS32)
11161217 TYPE("offset64", TYPE_MOFFS64)
11171218 TYPE("VR256", TYPE_XMM256)
1219 TYPE("VR256X", TYPE_XMM256)
1220 TYPE("VR512", TYPE_XMM512)
1221 TYPE("VK8", TYPE_VK8)
1222 TYPE("VK8WM", TYPE_VK8)
1223 TYPE("VK16", TYPE_VK16)
1224 TYPE("VK16WM", TYPE_VK16)
11181225 TYPE("GR16_NOAX", TYPE_Rv)
11191226 TYPE("GR32_NOAX", TYPE_Rv)
11201227 TYPE("GR64_NOAX", TYPE_R64)
11211228 TYPE("vx32mem", TYPE_M32)
11221229 TYPE("vy32mem", TYPE_M32)
1230 TYPE("vz32mem", TYPE_M32)
11231231 TYPE("vx64mem", TYPE_M64)
11241232 TYPE("vy64mem", TYPE_M64)
1233 TYPE("vy64xmem", TYPE_M64)
1234 TYPE("vz64mem", TYPE_M64)
11251235 errs() << "Unhandled type string " << s << "\n";
11261236 llvm_unreachable("Unhandled type string");
11271237 }
11481258 ENCODING("i8imm", ENCODING_IB)
11491259 // This is not a typo. Instructions like BLENDVPD put
11501260 // register IDs in 8-bit immediates nowadays.
1151 ENCODING("VR256", ENCODING_IB)
1152 ENCODING("VR128", ENCODING_IB)
11531261 ENCODING("FR32", ENCODING_IB)
11541262 ENCODING("FR64", ENCODING_IB)
1263 ENCODING("VR128", ENCODING_IB)
1264 ENCODING("VR256", ENCODING_IB)
1265 ENCODING("FR32X", ENCODING_IB)
1266 ENCODING("FR64X", ENCODING_IB)
1267 ENCODING("VR128X", ENCODING_IB)
1268 ENCODING("VR256X", ENCODING_IB)
1269 ENCODING("VR512", ENCODING_IB)
11551270 errs() << "Unhandled immediate encoding " << s << "\n";
11561271 llvm_unreachable("Unhandled immediate encoding");
11571272 }
11641279 ENCODING("GR64", ENCODING_RM)
11651280 ENCODING("GR8", ENCODING_RM)
11661281 ENCODING("VR128", ENCODING_RM)
1282 ENCODING("VR128X", ENCODING_RM)
11671283 ENCODING("FR64", ENCODING_RM)
11681284 ENCODING("FR32", ENCODING_RM)
1285 ENCODING("FR64X", ENCODING_RM)
1286 ENCODING("FR32X", ENCODING_RM)
11691287 ENCODING("VR64", ENCODING_RM)
11701288 ENCODING("VR256", ENCODING_RM)
1289 ENCODING("VR256X", ENCODING_RM)
1290 ENCODING("VR512", ENCODING_RM)
1291 ENCODING("VK8", ENCODING_RM)
1292 ENCODING("VK16", ENCODING_RM)
11711293 errs() << "Unhandled R/M register encoding " << s << "\n";
11721294 llvm_unreachable("Unhandled R/M register encoding");
11731295 }
11871309 ENCODING("DEBUG_REG", ENCODING_REG)
11881310 ENCODING("CONTROL_REG", ENCODING_REG)
11891311 ENCODING("VR256", ENCODING_REG)
1312 ENCODING("VR256X", ENCODING_REG)
1313 ENCODING("VR128X", ENCODING_REG)
1314 ENCODING("FR64X", ENCODING_REG)
1315 ENCODING("FR32X", ENCODING_REG)
1316 ENCODING("VR512", ENCODING_REG)
1317 ENCODING("VK8", ENCODING_REG)
1318 ENCODING("VK16", ENCODING_REG)
1319 ENCODING("VK8WM", ENCODING_REG)
1320 ENCODING("VK16WM", ENCODING_REG)
11901321 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
11911322 llvm_unreachable("Unhandled reg/opcode register encoding");
11921323 }
12001331 ENCODING("FR64", ENCODING_VVVV)
12011332 ENCODING("VR128", ENCODING_VVVV)
12021333 ENCODING("VR256", ENCODING_VVVV)
1334 ENCODING("FR32X", ENCODING_VVVV)
1335 ENCODING("FR64X", ENCODING_VVVV)
1336 ENCODING("VR128X", ENCODING_VVVV)
1337 ENCODING("VR256X", ENCODING_VVVV)
1338 ENCODING("VR512", ENCODING_VVVV)
1339 ENCODING("VK8", ENCODING_VVVV)
1340 ENCODING("VK16", ENCODING_VVVV)
12031341 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
12041342 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1343 }
1344
1345 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1346 (const std::string &s,
1347 bool hasOpSizePrefix) {
1348 ENCODING("VK8WM", ENCODING_WRITEMASK)
1349 ENCODING("VK16WM", ENCODING_WRITEMASK)
1350 errs() << "Unhandled mask register encoding " << s << "\n";
1351 llvm_unreachable("Unhandled mask register encoding");
12051352 }
12061353
12071354 OperandEncoding RecognizableInstr::memoryEncodingFromString
12151362 ENCODING("sdmem", ENCODING_RM)
12161363 ENCODING("f128mem", ENCODING_RM)
12171364 ENCODING("f256mem", ENCODING_RM)
1365 ENCODING("f512mem", ENCODING_RM)
12181366 ENCODING("f64mem", ENCODING_RM)
12191367 ENCODING("f32mem", ENCODING_RM)
12201368 ENCODING("i128mem", ENCODING_RM)
12211369 ENCODING("i256mem", ENCODING_RM)
1370 ENCODING("i512mem", ENCODING_RM)
12221371 ENCODING("f80mem", ENCODING_RM)
12231372 ENCODING("lea32mem", ENCODING_RM)
12241373 ENCODING("lea64_32mem", ENCODING_RM)
12291378 ENCODING("opaque512mem", ENCODING_RM)
12301379 ENCODING("vx32mem", ENCODING_RM)
12311380 ENCODING("vy32mem", ENCODING_RM)
1381 ENCODING("vz32mem", ENCODING_RM)
12321382 ENCODING("vx64mem", ENCODING_RM)
12331383 ENCODING("vy64mem", ENCODING_RM)
1384 ENCODING("vy64xmem", ENCODING_RM)
1385 ENCODING("vz64mem", ENCODING_RM)
12341386 errs() << "Unhandled memory encoding " << s << "\n";
12351387 llvm_unreachable("Unhandled memory encoding");
12361388 }
6565 bool HasMemOp4Prefix;
6666 /// The ignoreVEX_L field from the record
6767 bool IgnoresVEX_L;
68 /// The hasEVEXPrefix field from the record
69 bool HasEVEXPrefix;
70 /// The hasEVEX_L2Prefix field from the record
71 bool HasEVEX_L2Prefix;
72 /// The hasEVEX_K field from the record
73 bool HasEVEX_K;
74 /// The hasEVEX_B field from the record
75 bool HasEVEX_B;
6876 /// The hasLockPrefix field from the record
6977 bool HasLockPrefix;
7078 /// The isCodeGenOnly filed from the record
175183 bool hasOpSizePrefix);
176184 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
177185 bool HasOpSizePrefix);
186 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
187 bool HasOpSizePrefix);
178188
179189 /// handleOperand - Converts a single operand from the LLVM table format to
180190 /// the emitted table format, handling any duplicate operands it encounters