llvm.org GIT mirror llvm / c14bc77
Add more analysis of the sign bit of an srem instruction. If the LHS is negative then the result could go either way. If it's provably positive then so is the srem. Fixes PR9343 #7! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127146 91177308-0d34-0410-b5e6-96231b3b80d8 Nick Lewycky 8 years ago
3 changed file(s) with 44 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
459459 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
460460 }
461461 }
462
463 // The sign bit is the LHS's sign bit, except when the result of the
464 // remainder is zero.
465 if (Mask.isNegative() && KnownZero.isNonNegative()) {
466 APInt Mask2 = APInt::getSignBit(BitWidth);
467 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
468 ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne, TD,
469 Depth+1);
470 // If it's known zero, our sign bit is also zero.
471 if (LHSKnownZero.isNegative())
472 KnownZero |= LHSKnownZero;
473 }
474
462475 break;
463476 case Instruction::URem: {
464477 if (ConstantInt *Rem = dyn_cast(I->getOperand(1))) {
711711 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
712712 }
713713 }
714
715 // The sign bit is the LHS's sign bit, except when the result of the
716 // remainder is zero.
717 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
718 APInt Mask2 = APInt::getSignBit(BitWidth);
719 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
720 ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne,
721 Depth+1);
722 // If it's known zero, our sign bit is also zero.
723 if (LHSKnownZero.isNegative())
724 KnownZero |= LHSKnownZero;
725 }
714726 break;
715727 case Instruction::URem: {
716728 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);
474474 %cmp = icmp ult <2 x i32> %tmp11,
475475 ret <2 x i1> %cmp
476476 }
477
478 ; PR9343 #7
479 ; CHECK: @test50
480 ; CHECK: ret i1 true
481 define i1 @test50(i16 %X, i32 %Y) {
482 %A = zext i16 %X to i32
483 %B = srem i32 %A, %Y
484 %C = icmp sgt i32 %B, -1
485 ret i1 %C
486 }
487
488 ; CHECK: @test51
489 ; CHECK: ret i1 %C
490 define i1 @test51(i16 %X, i32 %Y) {
491 %A = sext i16 %X to i32
492 %B = srem i32 %A, %Y
493 %C = icmp sgt i32 %B, -1
494 ret i1 %C
495 }