llvm.org GIT mirror llvm / c136281
Replace silly uses of 'signed' with 'int' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273244 91177308-0d34-0410-b5e6-96231b3b80d8 David Majnemer 4 years ago
12 changed file(s) with 37 addition(s) and 37 deletion(s). Raw diff Collapse all Expand all
99 #ifndef LLVM_ADT_STRINGREF_H
1010 #define LLVM_ADT_STRINGREF_H
1111
12 #include "llvm/ADT/iterator_range.h"
1213 #include "llvm/Support/Compiler.h"
1314 #include
1415 #include
100101 const unsigned char *bytes_end() const {
101102 return reinterpret_cast(end());
102103 }
104 iterator_range bytes() const {
105 return make_range(bytes_begin(), bytes_end());
106 }
103107
104108 /// @}
105109 /// @name String Operations
7171
7272 /// Heuristics for estimating register pressure.
7373 unsigned ParallelLiveRanges;
74 signed HorizontalVerticalBalance;
74 int HorizontalVerticalBalance;
7575
7676 public:
7777 ResourcePriorityQueue(SelectionDAGISel *IS);
102102
103103 /// Single cost function reflecting benefit of scheduling SU
104104 /// in the current cycle.
105 signed SUSchedulingCost (SUnit *SU);
105 int SUSchedulingCost (SUnit *SU);
106106
107107 /// InitNumRegDefsLeft - Determine the # of regs defined by this node.
108108 ///
109109 void initNumRegDefsLeft(SUnit *SU);
110110 void updateNumRegDefsLeft(SUnit *SU);
111 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
112 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
111 int regPressureDelta(SUnit *SU, bool RawPressure = false);
112 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
113113
114114 bool empty() const override { return Queue.empty(); }
115115
1616 //===----------------------------------------------------------------------===//
1717
1818 #include "llvm/Analysis/ConstantFolding.h"
19 #include "llvm/ADT/STLExtras.h"
1920 #include "llvm/ADT/SmallPtrSet.h"
2021 #include "llvm/ADT/SmallVector.h"
2122 #include "llvm/ADT/StringMap.h"
563564 // directly if string length is small enough.
564565 StringRef Str;
565566 if (getConstantStringInfo(CE, Str) && !Str.empty()) {
566 unsigned StrLen = Str.size();
567 size_t StrLen = Str.size();
567568 unsigned NumBits = Ty->getPrimitiveSizeInBits();
568569 // Replace load with immediate integer if the result is an integer or fp
569570 // value.
572573 APInt StrVal(NumBits, 0);
573574 APInt SingleChar(NumBits, 0);
574575 if (DL.isLittleEndian()) {
575 for (signed i = StrLen-1; i >= 0; i--) {
576 SingleChar = (uint64_t) Str[i] &
577 std::numeric_limits::max();
576 for (unsigned char C : reverse(Str.bytes())) {
577 SingleChar = static_cast(C);
578578 StrVal = (StrVal << 8) | SingleChar;
579579 }
580580 } else {
581 for (unsigned i = 0; i < StrLen; i++) {
582 SingleChar = (uint64_t) Str[i] &
583 std::numeric_limits::max();
581 for (unsigned char C : Str.bytes()) {
582 SingleChar = static_cast(C);
584583 StrVal = (StrVal << 8) | SingleChar;
585584 }
586585 // Append NULL at the end.
46914691 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
46924692
46934693 // Determine the residual right-shift amount.
4694 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4694 int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
46954695
46964696 // If the shift is not a no-op (in which case this should be just a sign
46974697 // extend already), the truncated to type is legal, sign_extend is legal
3636 cl::ZeroOrMore, cl::init(false),
3737 cl::desc("Disable use of DFA during scheduling"));
3838
39 static cl::opt<signed> RegPressureThreshold(
39 static cl::opt<int> RegPressureThreshold(
4040 "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),
4141 cl::desc("Track reg pressure and switch priority to in-depth"));
4242
322322 }
323323 }
324324
325 signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
326 signed RegBalance = 0;
325 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
326 int RegBalance = 0;
327327
328328 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
329329 return RegBalance;
356356 /// The RawPressure flag makes this function to ignore
357357 /// existing reg file sizes, and report raw def/use
358358 /// balance.
359 signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
360 signed RegBalance = 0;
359 int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
360 int RegBalance = 0;
361361
362362 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
363363 return RegBalance;
397397
398398 /// Returns single number reflecting benefit of scheduling SU
399399 /// in the current cycle.
400 signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
400 int ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
401401 // Initial trivial priority.
402 signed ResCount = 1;
402 int ResCount = 1;
403403
404404 // Do not waste time on a node that is already scheduled.
405405 if (SU->isScheduled)
600600
601601 std::vector::iterator Best = Queue.begin();
602602 if (!DisableDFASched) {
603 signed BestCost = SUSchedulingCost(*Best);
603 int BestCost = SUSchedulingCost(*Best);
604604 for (std::vector::iterator I = std::next(Queue.begin()),
605605 E = Queue.end(); I != E; ++I) {
606606
94749474 // isEquivalentMaskless() is the code for testing if the AND can be removed
94759475 // factored out of the DAG recognition as the DAG can take several forms.
94769476
9477 static
9478 bool isEquivalentMaskless(unsigned CC, unsigned width,
9479 ISD::LoadExtType ExtType, signed AddConstant,
9480 signed CompConstant) {
9477 static bool isEquivalentMaskless(unsigned CC, unsigned width,
9478 ISD::LoadExtType ExtType, int AddConstant,
9479 int CompConstant) {
94819480 // By being careful about our equations and only writing the in term
94829481 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
94839482 // make them generally applicable to all bit widths.
9484 signed MaxUInt = (1 << width);
9483 int MaxUInt = (1 << width);
94859484
94869485 // For the purposes of these comparisons sign extending the type is
94879486 // equivalent to zero extending the add and displacing it by half the integer
930930 // ARM halfword load/stores and signed byte loads need an additional
931931 // operand.
932932 if (useAM3) {
933 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
933 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
934934 MIB.addReg(0);
935935 MIB.addImm(Imm);
936936 } else {
944944 // ARM halfword load/stores and signed byte loads need an additional
945945 // operand.
946946 if (useAM3) {
947 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
947 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
948948 MIB.addReg(0);
949949 MIB.addImm(Imm);
950950 } else {
17961796 MCOperand &MO = Inst.getOperand(1);
17971797 int64_t Value;
17981798 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1799 unsigned long long u64 = Value;
1800 signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
1801 if (s8 < -128 || s8 > 127)
1799 int s8 = Hi_32(Value);
1800 if (!isInt<8>(s8))
18021801 OutOfRange(IDLoc, s8, -128);
18031802 MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
18041803 MCConstantExpr::create(s8, Context), Context))); // upper 32
18051804 auto Expr = HexagonMCExpr::create(
1806 MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
1807 Context);
1805 MCConstantExpr::create(Lo_32(Value), Context), Context);
18081806 HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
18091807 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
18101808 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
415415 uint32_t Offset = Fixup.getOffset();
416416 unsigned NumBytes = getFixupKindNumBytes(Kind);
417417 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
418 char* InstAddr = Data + Offset;
418 char *InstAddr = Data + Offset;
419419
420420 Value = adjustFixupValue(Kind, FixupValue);
421421 if(!Value)
422422 return;
423 signed sValue = (signed)Value;
423 int sValue = (int)Value;
424424
425425 switch((unsigned)Kind) {
426426 default:
515515 unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
516516 assert(isInt<16>(MFI->getMaxAlignment()) &&
517517 "Function's alignment size requirement is not supported.");
518 int MaxAlign = - (signed) MFI->getMaxAlignment();
518 int MaxAlign = -(int)MFI->getMaxAlignment();
519519
520520 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
521521 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
261261
262262 def HA16 : SDNodeXForm
263263 // Transformation function: shift the immediate value down into the low bits.
264 signed int Val = N->getZExtValue();
264 int Val = N->getZExtValue();
265265 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
266266 }]>;
267267 def MB : SDNodeXForm
13971397 if (Op1 == &GEP)
13981398 return nullptr;
13991399
1400 signed DI = -1;
1400 int DI = -1;
14011401
14021402 for (auto I = PN->op_begin()+1, E = PN->op_end(); I !=E; ++I) {
14031403 GetElementPtrInst *Op2 = dyn_cast(*I);