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[GlobalISel][X86_64] Support for G_SITOFP The instruction selection is automatically handled by tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336703 91177308-0d34-0410-b5e6-96231b3b80d8 Alexander Ivchenko 2 years ago
5 changed file(s) with 644 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
211211 setAction({extOp, s64}, Legal);
212212 }
213213
214 getActionDefinitionsBuilder(G_SITOFP)
215 .legalForCartesianProduct({s32, s64})
216 .clampScalar(1, s32, s64)
217 .widenScalarToNextPow2(1)
218 .clampScalar(0, s32, s64)
219 .widenScalarToNextPow2(0);
220
214221 // Comparison
215222 setAction({G_ICMP, 1, s64}, Legal);
216223
197197 // Instruction having only floating-point operands (all scalars in VECRReg)
198198 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
199199 break;
200 case TargetOpcode::G_SITOFP: {
201 // Some of the floating-point instructions have mixed GPR and FP operands:
202 // fine-tune the computed mapping.
203 auto &Op0 = MI.getOperand(0);
204 auto &Op1 = MI.getOperand(1);
205 const LLT Ty0 = MRI.getType(Op0.getReg());
206 const LLT Ty1 = MRI.getType(Op1.getReg());
207 OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ true);
208 OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ false);
209 break;
210 }
200211 case TargetOpcode::G_TRUNC:
201212 case TargetOpcode::G_ANYEXT: {
202213 auto &Op0 = MI.getOperand(0);
239239
240240 define void @test_fconstant() {
241241 ret void
242 }
243
244 define float @int32_to_float(i32 %a) {
245 entry:
246 %conv = sitofp i32 %a to float
247 ret float %conv
248 }
249
250 define float @int64_to_float(i64 %a) {
251 entry:
252 %conv = sitofp i64 %a to float
253 ret float %conv
254 }
255
256 define double @int32_to_double(i32 %a) {
257 entry:
258 %conv = sitofp i32 %a to double
259 ret double %conv
260 }
261
262 define double @int64_to_double(i64 %a) {
263 entry:
264 %conv = sitofp i64 %a to double
265 ret double %conv
242266 }
243267
244268 ...
18161840 ; GREEDY: [[C1:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 2.000000e+00
18171841 %0(s32) = G_FCONSTANT float 1.0
18181842 %1(s64) = G_FCONSTANT double 2.0
1819 ...
1843
1844 ...
1845 ---
1846 name: int32_to_float
1847 alignment: 4
1848 legalized: true
1849 tracksRegLiveness: true
1850 registers:
1851 - { id: 0, class: _ }
1852 - { id: 1, class: _ }
1853 - { id: 2, class: _ }
1854 body: |
1855 bb.1.entry:
1856 liveins: $edi
1857
1858 ; FAST-LABEL: name: int32_to_float
1859 ; FAST: liveins: $edi
1860 ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1861 ; FAST: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s32)
1862 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32)
1863 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
1864 ; FAST: RET 0, implicit $xmm0
1865 ; GREEDY-LABEL: name: int32_to_float
1866 ; GREEDY: liveins: $edi
1867 ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1868 ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s32)
1869 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32)
1870 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
1871 ; GREEDY: RET 0, implicit $xmm0
1872 %0:_(s32) = COPY $edi
1873 %1:_(s32) = G_SITOFP %0(s32)
1874 %2:_(s128) = G_ANYEXT %1(s32)
1875 $xmm0 = COPY %2(s128)
1876 RET 0, implicit $xmm0
1877
1878 ...
1879 ---
1880 name: int64_to_float
1881 alignment: 4
1882 legalized: true
1883 tracksRegLiveness: true
1884 registers:
1885 - { id: 0, class: _ }
1886 - { id: 1, class: _ }
1887 - { id: 2, class: _ }
1888 body: |
1889 bb.1.entry:
1890 liveins: $rdi
1891
1892 ; FAST-LABEL: name: int64_to_float
1893 ; FAST: liveins: $rdi
1894 ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
1895 ; FAST: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s64)
1896 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32)
1897 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
1898 ; FAST: RET 0, implicit $xmm0
1899 ; GREEDY-LABEL: name: int64_to_float
1900 ; GREEDY: liveins: $rdi
1901 ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
1902 ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s64)
1903 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32)
1904 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
1905 ; GREEDY: RET 0, implicit $xmm0
1906 %0:_(s64) = COPY $rdi
1907 %1:_(s32) = G_SITOFP %0(s64)
1908 %2:_(s128) = G_ANYEXT %1(s32)
1909 $xmm0 = COPY %2(s128)
1910 RET 0, implicit $xmm0
1911
1912 ...
1913 ---
1914 name: int32_to_double
1915 alignment: 4
1916 legalized: true
1917 tracksRegLiveness: true
1918 registers:
1919 - { id: 0, class: _ }
1920 - { id: 1, class: _ }
1921 - { id: 2, class: _ }
1922 body: |
1923 bb.1.entry:
1924 liveins: $edi
1925
1926 ; FAST-LABEL: name: int32_to_double
1927 ; FAST: liveins: $edi
1928 ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1929 ; FAST: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s32)
1930 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64)
1931 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
1932 ; FAST: RET 0, implicit $xmm0
1933 ; GREEDY-LABEL: name: int32_to_double
1934 ; GREEDY: liveins: $edi
1935 ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1936 ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s32)
1937 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64)
1938 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
1939 ; GREEDY: RET 0, implicit $xmm0
1940 %0:_(s32) = COPY $edi
1941 %1:_(s64) = G_SITOFP %0(s32)
1942 %2:_(s128) = G_ANYEXT %1(s64)
1943 $xmm0 = COPY %2(s128)
1944 RET 0, implicit $xmm0
1945
1946 ...
1947 ---
1948 name: int64_to_double
1949 alignment: 4
1950 legalized: true
1951 tracksRegLiveness: true
1952 registers:
1953 - { id: 0, class: _ }
1954 - { id: 1, class: _ }
1955 - { id: 2, class: _ }
1956 body: |
1957 bb.1.entry:
1958 liveins: $rdi
1959
1960 ; FAST-LABEL: name: int64_to_double
1961 ; FAST: liveins: $rdi
1962 ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
1963 ; FAST: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s64)
1964 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64)
1965 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
1966 ; FAST: RET 0, implicit $xmm0
1967 ; GREEDY-LABEL: name: int64_to_double
1968 ; GREEDY: liveins: $rdi
1969 ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
1970 ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s64)
1971 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64)
1972 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
1973 ; GREEDY: RET 0, implicit $xmm0
1974 %0:_(s64) = COPY $rdi
1975 %1:_(s64) = G_SITOFP %0(s64)
1976 %2:_(s128) = G_ANYEXT %1(s64)
1977 $xmm0 = COPY %2(s128)
1978 RET 0, implicit $xmm0
1979
1980 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
2
3 --- |
4 ; ModuleID = 'sitofp.ll'
5 source_filename = "sitofp.c"
6 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
7 target triple = "x86_64-unknown-linux-gnu"
8
9 ; Function Attrs: norecurse nounwind readnone uwtable
10 define dso_local float @int8_to_float(i8 signext %a) local_unnamed_addr #0 {
11 entry:
12 %conv = sitofp i8 %a to float
13 ret float %conv
14 }
15
16 ; Function Attrs: norecurse nounwind readnone uwtable
17 define dso_local float @int16_to_float(i16 signext %a) local_unnamed_addr #0 {
18 entry:
19 %conv = sitofp i16 %a to float
20 ret float %conv
21 }
22
23 ; Function Attrs: norecurse nounwind readnone uwtable
24 define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 {
25 entry:
26 %conv = sitofp i32 %a to float
27 ret float %conv
28 }
29
30 ; Function Attrs: norecurse nounwind readnone uwtable
31 define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 {
32 entry:
33 %conv = sitofp i64 %a to float
34 ret float %conv
35 }
36
37 ; Function Attrs: norecurse nounwind readnone uwtable
38 define dso_local double @int8_to_double(i8 signext %a) local_unnamed_addr #0 {
39 entry:
40 %conv = sitofp i8 %a to double
41 ret double %conv
42 }
43
44 ; Function Attrs: norecurse nounwind readnone uwtable
45 define dso_local double @int16_to_double(i16 signext %a) local_unnamed_addr #0 {
46 entry:
47 %conv = sitofp i16 %a to double
48 ret double %conv
49 }
50
51 ; Function Attrs: norecurse nounwind readnone uwtable
52 define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 {
53 entry:
54 %conv = sitofp i32 %a to double
55 ret double %conv
56 }
57
58 ; Function Attrs: norecurse nounwind readnone uwtable
59 define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 {
60 entry:
61 %conv = sitofp i64 %a to double
62 ret double %conv
63 }
64
65 attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
66
67 !llvm.module.flags = !{!0}
68 !llvm.ident = !{!1}
69
70 !0 = !{i32 1, !"wchar_size", i32 4}
71 !1 = !{!"clang version 7.0.0 (http://llvm.org/git/clang.git a05f37359b23be7c068e19968c8f106edf6f2b34) (http://llvm.org/git/llvm.git d693de1fee74d455e20f96006aac50317ca1da6b)"}
72
73 ...
74 ---
75 name: int8_to_float
76 alignment: 4
77 tracksRegLiveness: true
78 registers:
79 - { id: 0, class: _ }
80 - { id: 1, class: _ }
81 - { id: 2, class: _ }
82 - { id: 3, class: _ }
83 body: |
84 bb.1.entry:
85 liveins: $edi
86
87 ; CHECK-LABEL: name: int8_to_float
88 ; CHECK: liveins: $edi
89 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
90 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
91 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
92 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
93 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
94 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
95 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
96 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
97 ; CHECK: RET 0, implicit $xmm0
98 %1:_(s32) = COPY $edi
99 %0:_(s8) = G_TRUNC %1(s32)
100 %2:_(s32) = G_SITOFP %0(s8)
101 %3:_(s128) = G_ANYEXT %2(s32)
102 $xmm0 = COPY %3(s128)
103 RET 0, implicit $xmm0
104
105 ...
106 ---
107 name: int16_to_float
108 alignment: 4
109 tracksRegLiveness: true
110 registers:
111 - { id: 0, class: _ }
112 - { id: 1, class: _ }
113 - { id: 2, class: _ }
114 - { id: 3, class: _ }
115 body: |
116 bb.1.entry:
117 liveins: $edi
118
119 ; CHECK-LABEL: name: int16_to_float
120 ; CHECK: liveins: $edi
121 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
122 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
123 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
124 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
125 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
126 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
127 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
128 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
129 ; CHECK: RET 0, implicit $xmm0
130 %1:_(s32) = COPY $edi
131 %0:_(s16) = G_TRUNC %1(s32)
132 %2:_(s32) = G_SITOFP %0(s16)
133 %3:_(s128) = G_ANYEXT %2(s32)
134 $xmm0 = COPY %3(s128)
135 RET 0, implicit $xmm0
136
137 ...
138 ---
139 name: int32_to_float
140 alignment: 4
141 tracksRegLiveness: true
142 registers:
143 - { id: 0, class: _ }
144 - { id: 1, class: _ }
145 - { id: 2, class: _ }
146 body: |
147 bb.1.entry:
148 liveins: $edi
149
150 ; CHECK-LABEL: name: int32_to_float
151 ; CHECK: liveins: $edi
152 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
153 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
154 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
155 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
156 ; CHECK: RET 0, implicit $xmm0
157 %0:_(s32) = COPY $edi
158 %1:_(s32) = G_SITOFP %0(s32)
159 %2:_(s128) = G_ANYEXT %1(s32)
160 $xmm0 = COPY %2(s128)
161 RET 0, implicit $xmm0
162
163 ...
164 ---
165 name: int64_to_float
166 alignment: 4
167 tracksRegLiveness: true
168 registers:
169 - { id: 0, class: _ }
170 - { id: 1, class: _ }
171 - { id: 2, class: _ }
172 body: |
173 bb.1.entry:
174 liveins: $rdi
175
176 ; CHECK-LABEL: name: int64_to_float
177 ; CHECK: liveins: $rdi
178 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
179 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
180 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
181 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
182 ; CHECK: RET 0, implicit $xmm0
183 %0:_(s64) = COPY $rdi
184 %1:_(s32) = G_SITOFP %0(s64)
185 %2:_(s128) = G_ANYEXT %1(s32)
186 $xmm0 = COPY %2(s128)
187 RET 0, implicit $xmm0
188
189 ...
190 ---
191 name: int8_to_double
192 alignment: 4
193 tracksRegLiveness: true
194 registers:
195 - { id: 0, class: _ }
196 - { id: 1, class: _ }
197 - { id: 2, class: _ }
198 - { id: 3, class: _ }
199 body: |
200 bb.1.entry:
201 liveins: $edi
202
203 ; CHECK-LABEL: name: int8_to_double
204 ; CHECK: liveins: $edi
205 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
206 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
207 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
208 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
209 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
210 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
211 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
212 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
213 ; CHECK: RET 0, implicit $xmm0
214 %1:_(s32) = COPY $edi
215 %0:_(s8) = G_TRUNC %1(s32)
216 %2:_(s64) = G_SITOFP %0(s8)
217 %3:_(s128) = G_ANYEXT %2(s64)
218 $xmm0 = COPY %3(s128)
219 RET 0, implicit $xmm0
220
221 ...
222 ---
223 name: int16_to_double
224 alignment: 4
225 tracksRegLiveness: true
226 registers:
227 - { id: 0, class: _ }
228 - { id: 1, class: _ }
229 - { id: 2, class: _ }
230 - { id: 3, class: _ }
231 body: |
232 bb.1.entry:
233 liveins: $edi
234
235 ; CHECK-LABEL: name: int16_to_double
236 ; CHECK: liveins: $edi
237 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
238 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
239 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
240 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
241 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
242 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
243 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
244 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
245 ; CHECK: RET 0, implicit $xmm0
246 %1:_(s32) = COPY $edi
247 %0:_(s16) = G_TRUNC %1(s32)
248 %2:_(s64) = G_SITOFP %0(s16)
249 %3:_(s128) = G_ANYEXT %2(s64)
250 $xmm0 = COPY %3(s128)
251 RET 0, implicit $xmm0
252
253 ...
254 ---
255 name: int32_to_double
256 alignment: 4
257 tracksRegLiveness: true
258 registers:
259 - { id: 0, class: _ }
260 - { id: 1, class: _ }
261 - { id: 2, class: _ }
262 body: |
263 bb.1.entry:
264 liveins: $edi
265
266 ; CHECK-LABEL: name: int32_to_double
267 ; CHECK: liveins: $edi
268 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
269 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
270 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
271 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
272 ; CHECK: RET 0, implicit $xmm0
273 %0:_(s32) = COPY $edi
274 %1:_(s64) = G_SITOFP %0(s32)
275 %2:_(s128) = G_ANYEXT %1(s64)
276 $xmm0 = COPY %2(s128)
277 RET 0, implicit $xmm0
278
279 ...
280 ---
281 name: int64_to_double
282 alignment: 4
283 tracksRegLiveness: true
284 registers:
285 - { id: 0, class: _ }
286 - { id: 1, class: _ }
287 - { id: 2, class: _ }
288 body: |
289 bb.1.entry:
290 liveins: $rdi
291
292 ; CHECK-LABEL: name: int64_to_double
293 ; CHECK: liveins: $rdi
294 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
295 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
296 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
297 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
298 ; CHECK: RET 0, implicit $xmm0
299 %0:_(s64) = COPY $rdi
300 %1:_(s64) = G_SITOFP %0(s64)
301 %2:_(s128) = G_ANYEXT %1(s64)
302 $xmm0 = COPY %2(s128)
303 RET 0, implicit $xmm0
304
305 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
2
3 --- |
4 ; ModuleID = 'sitofp_legal.ll'
5 source_filename = "sitofp.c"
6 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
7 target triple = "x86_64-unknown-linux-gnu"
8
9 ; Function Attrs: norecurse nounwind readnone uwtable
10 define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 {
11 entry:
12 %conv = sitofp i32 %a to float
13 ret float %conv
14 }
15
16 ; Function Attrs: norecurse nounwind readnone uwtable
17 define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 {
18 entry:
19 %conv = sitofp i64 %a to float
20 ret float %conv
21 }
22
23 ; Function Attrs: norecurse nounwind readnone uwtable
24 define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 {
25 entry:
26 %conv = sitofp i32 %a to double
27 ret double %conv
28 }
29
30 ; Function Attrs: norecurse nounwind readnone uwtable
31 define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 {
32 entry:
33 %conv = sitofp i64 %a to double
34 ret double %conv
35 }
36
37 attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
38
39 !llvm.module.flags = !{!0}
40 !llvm.ident = !{!1}
41
42 !0 = !{i32 1, !"wchar_size", i32 4}
43 !1 = !{!"clang version 7.0.0 (http://llvm.org/git/clang.git a05f37359b23be7c068e19968c8f106edf6f2b34) (http://llvm.org/git/llvm.git d693de1fee74d455e20f96006aac50317ca1da6b)"}
44
45 ...
46 ---
47 name: int32_to_float
48 alignment: 4
49 legalized: true
50 regBankSelected: true
51 tracksRegLiveness: true
52 registers:
53 - { id: 0, class: gpr }
54 - { id: 1, class: vecr }
55 - { id: 2, class: vecr }
56 body: |
57 bb.1.entry:
58 liveins: $edi
59
60 ; CHECK-LABEL: name: int32_to_float
61 ; CHECK: liveins: $edi
62 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
63 ; CHECK: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
64 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SSrr]]
65 ; CHECK: $xmm0 = COPY [[COPY1]]
66 ; CHECK: RET 0, implicit $xmm0
67 %0:gpr(s32) = COPY $edi
68 %1:vecr(s32) = G_SITOFP %0(s32)
69 %2:vecr(s128) = G_ANYEXT %1(s32)
70 $xmm0 = COPY %2(s128)
71 RET 0, implicit $xmm0
72
73 ...
74 ---
75 name: int64_to_float
76 alignment: 4
77 legalized: true
78 regBankSelected: true
79 tracksRegLiveness: true
80 registers:
81 - { id: 0, class: gpr }
82 - { id: 1, class: vecr }
83 - { id: 2, class: vecr }
84 body: |
85 bb.1.entry:
86 liveins: $rdi
87
88 ; CHECK-LABEL: name: int64_to_float
89 ; CHECK: liveins: $rdi
90 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
91 ; CHECK: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
92 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SSrr]]
93 ; CHECK: $xmm0 = COPY [[COPY1]]
94 ; CHECK: RET 0, implicit $xmm0
95 %0:gpr(s64) = COPY $rdi
96 %1:vecr(s32) = G_SITOFP %0(s64)
97 %2:vecr(s128) = G_ANYEXT %1(s32)
98 $xmm0 = COPY %2(s128)
99 RET 0, implicit $xmm0
100
101 ...
102 ---
103 name: int32_to_double
104 alignment: 4
105 legalized: true
106 regBankSelected: true
107 tracksRegLiveness: true
108 registers:
109 - { id: 0, class: gpr }
110 - { id: 1, class: vecr }
111 - { id: 2, class: vecr }
112 body: |
113 bb.1.entry:
114 liveins: $edi
115
116 ; CHECK-LABEL: name: int32_to_double
117 ; CHECK: liveins: $edi
118 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
119 ; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
120 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]]
121 ; CHECK: $xmm0 = COPY [[COPY1]]
122 ; CHECK: RET 0, implicit $xmm0
123 %0:gpr(s32) = COPY $edi
124 %1:vecr(s64) = G_SITOFP %0(s32)
125 %2:vecr(s128) = G_ANYEXT %1(s64)
126 $xmm0 = COPY %2(s128)
127 RET 0, implicit $xmm0
128
129 ...
130 ---
131 name: int64_to_double
132 alignment: 4
133 legalized: true
134 regBankSelected: true
135 tracksRegLiveness: true
136 registers:
137 - { id: 0, class: gpr }
138 - { id: 1, class: vecr }
139 - { id: 2, class: vecr }
140 body: |
141 bb.1.entry:
142 liveins: $rdi
143
144 ; CHECK-LABEL: name: int64_to_double
145 ; CHECK: liveins: $rdi
146 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
147 ; CHECK: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
148 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SDrr]]
149 ; CHECK: $xmm0 = COPY [[COPY1]]
150 ; CHECK: RET 0, implicit $xmm0
151 %0:gpr(s64) = COPY $rdi
152 %1:vecr(s64) = G_SITOFP %0(s64)
153 %2:vecr(s128) = G_ANYEXT %1(s64)
154 $xmm0 = COPY %2(s128)
155 RET 0, implicit $xmm0
156
157 ...