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ARM refactor more NEON VLD/VST instructions to use composite physregs Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
9 changed file(s) with 120 addition(s) and 171 deletion(s). Raw diff Collapse all Expand all
27592759 case ARM::VLD4q8oddPseudo_UPD:
27602760 case ARM::VLD4q16oddPseudo_UPD:
27612761 case ARM::VLD4q32oddPseudo_UPD:
2762 case ARM::VLD1DUPq8Pseudo:
2763 case ARM::VLD1DUPq16Pseudo:
2764 case ARM::VLD1DUPq32Pseudo:
2765 case ARM::VLD1DUPq8PseudoWB_fixed:
2766 case ARM::VLD1DUPq16PseudoWB_fixed:
2767 case ARM::VLD1DUPq32PseudoWB_fixed:
2768 case ARM::VLD1DUPq8PseudoWB_register:
2769 case ARM::VLD1DUPq16PseudoWB_register:
2770 case ARM::VLD1DUPq32PseudoWB_register:
2771 case ARM::VLD2DUPd8Pseudo:
2772 case ARM::VLD2DUPd16Pseudo:
2773 case ARM::VLD2DUPd32Pseudo:
2774 case ARM::VLD2DUPd8PseudoWB_fixed:
2775 case ARM::VLD2DUPd16PseudoWB_fixed:
2776 case ARM::VLD2DUPd32PseudoWB_fixed:
2777 case ARM::VLD2DUPd8PseudoWB_register:
2778 case ARM::VLD2DUPd16PseudoWB_register:
2779 case ARM::VLD2DUPd32PseudoWB_register:
2762 case ARM::VLD1DUPq8:
2763 case ARM::VLD1DUPq16:
2764 case ARM::VLD1DUPq32:
2765 case ARM::VLD1DUPq8wb_fixed:
2766 case ARM::VLD1DUPq16wb_fixed:
2767 case ARM::VLD1DUPq32wb_fixed:
2768 case ARM::VLD1DUPq8wb_register:
2769 case ARM::VLD1DUPq16wb_register:
2770 case ARM::VLD1DUPq32wb_register:
2771 case ARM::VLD2DUPd8:
2772 case ARM::VLD2DUPd16:
2773 case ARM::VLD2DUPd32:
2774 case ARM::VLD2DUPd8wb_fixed:
2775 case ARM::VLD2DUPd16wb_fixed:
2776 case ARM::VLD2DUPd32wb_fixed:
2777 case ARM::VLD2DUPd8wb_register:
2778 case ARM::VLD2DUPd16wb_register:
2779 case ARM::VLD2DUPd32wb_register:
27802780 case ARM::VLD4DUPd8Pseudo:
27812781 case ARM::VLD4DUPd16Pseudo:
27822782 case ARM::VLD4DUPd32Pseudo:
128128 }
129129
130130 static const NEONLdStTableEntry NEONLdStTable[] = {
131 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, false, SingleSpc, 2, 4,false},
132 { ARM::VLD1DUPq16PseudoWB_fixed, ARM::VLD1DUPq16wb_fixed, true, true, true, SingleSpc, 2, 4,false},
133 { ARM::VLD1DUPq16PseudoWB_register, ARM::VLD1DUPq16wb_register, true, true, true, SingleSpc, 2, 4,false},
134 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, false, SingleSpc, 2, 2,false},
135 { ARM::VLD1DUPq32PseudoWB_fixed, ARM::VLD1DUPq32wb_fixed, true, true, false, SingleSpc, 2, 2,false},
136 { ARM::VLD1DUPq32PseudoWB_register, ARM::VLD1DUPq32wb_register, true, true, true, SingleSpc, 2, 2,false},
137 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, false, SingleSpc, 2, 8,false},
138 { ARM::VLD1DUPq8PseudoWB_fixed, ARM::VLD1DUPq8wb_fixed, true, true, false, SingleSpc, 2, 8,false},
139 { ARM::VLD1DUPq8PseudoWB_register, ARM::VLD1DUPq8wb_register, true, true, true, SingleSpc, 2, 8,false},
140
141131 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
142132 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
143133 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
147137
148138 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
149139 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
150
151 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false},
152 { ARM::VLD2DUPd16PseudoWB_fixed, ARM::VLD2DUPd16wb_fixed, true, true, false, SingleSpc, 2, 4,false},
153 { ARM::VLD2DUPd16PseudoWB_register, ARM::VLD2DUPd16wb_register, true, true, true, SingleSpc, 2, 4,false},
154 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,false},
155 { ARM::VLD2DUPd32PseudoWB_fixed, ARM::VLD2DUPd32wb_fixed, true, true, false, SingleSpc, 2, 2,false},
156 { ARM::VLD2DUPd32PseudoWB_register, ARM::VLD2DUPd32wb_register, true, true, true, SingleSpc, 2, 2,false},
157 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,false},
158 { ARM::VLD2DUPd8PseudoWB_fixed, ARM::VLD2DUPd8wb_fixed, true, true, false, SingleSpc, 2, 8,false},
159 { ARM::VLD2DUPd8PseudoWB_register, ARM::VLD2DUPd8wb_register, true, true, true, SingleSpc, 2, 8,false},
160140
161141 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
162142 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
10891069 case ARM::VLD4q8oddPseudo_UPD:
10901070 case ARM::VLD4q16oddPseudo_UPD:
10911071 case ARM::VLD4q32oddPseudo_UPD:
1092 case ARM::VLD1DUPq8Pseudo:
1093 case ARM::VLD1DUPq16Pseudo:
1094 case ARM::VLD1DUPq32Pseudo:
1095 case ARM::VLD1DUPq8PseudoWB_fixed:
1096 case ARM::VLD1DUPq16PseudoWB_fixed:
1097 case ARM::VLD1DUPq32PseudoWB_fixed:
1098 case ARM::VLD1DUPq8PseudoWB_register:
1099 case ARM::VLD1DUPq16PseudoWB_register:
1100 case ARM::VLD1DUPq32PseudoWB_register:
1101 case ARM::VLD2DUPd8Pseudo:
1102 case ARM::VLD2DUPd16Pseudo:
1103 case ARM::VLD2DUPd32Pseudo:
1104 case ARM::VLD2DUPd8PseudoWB_fixed:
1105 case ARM::VLD2DUPd16PseudoWB_fixed:
1106 case ARM::VLD2DUPd32PseudoWB_fixed:
1107 case ARM::VLD2DUPd8PseudoWB_register:
1108 case ARM::VLD2DUPd16PseudoWB_register:
1109 case ARM::VLD2DUPd32PseudoWB_register:
11101072 case ARM::VLD3DUPd8Pseudo:
11111073 case ARM::VLD3DUPd16Pseudo:
11121074 case ARM::VLD3DUPd32Pseudo:
15881588 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
15891589 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
15901590
1591 case ARM::VLD2DUPd8PseudoWB_fixed: return ARM::VLD2DUPd8PseudoWB_register;
1592 case ARM::VLD2DUPd16PseudoWB_fixed: return ARM::VLD2DUPd16PseudoWB_register;
1593 case ARM::VLD2DUPd32PseudoWB_fixed: return ARM::VLD2DUPd32PseudoWB_register;
1591 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1592 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1593 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
15941594 }
15951595 return Opc; // If not one we handle, return it unchanged.
15961596 }
28902890 }
28912891
28922892 case ARMISD::VLD2DUP: {
2893 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2894 ARM::VLD2DUPd32Pseudo };
2893 unsigned Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2894 ARM::VLD2DUPd32 };
28952895 return SelectVLDDup(N, false, 2, Opcodes);
28962896 }
28972897
29082908 }
29092909
29102910 case ARMISD::VLD2DUP_UPD: {
2911 unsigned Opcodes[] = { ARM::VLD2DUPd8PseudoWB_fixed,
2912 ARM::VLD2DUPd16PseudoWB_fixed,
2913 ARM::VLD2DUPd32PseudoWB_fixed };
2911 unsigned Opcodes[] = { ARM::VLD2DUPd8wb_fixed, ARM::VLD2DUPd16wb_fixed,
2912 ARM::VLD2DUPd32wb_fixed };
29142913 return SelectVLDDup(N, true, 2, Opcodes);
29152914 }
29162915
9393 let ParserMethod = "parseVectorList";
9494 let RenderMethod = "addVecListOperands";
9595 }
96 def VecListDPair : RegisterOperandDPair"> {
96 def VecListDPair : RegisterOperandTwo"> {
9797 let ParserMatchClass = VecListDPairAsmOperand;
9898 }
9999 // Register list of three sequential D registers.
120120 let ParserMethod = "parseVectorList";
121121 let RenderMethod = "addVecListOperands";
122122 }
123 def VecListDPairSpaced : RegisterOperandDPairSpaced"> {
123 def VecListDPairSpaced : RegisterOperandTwoSpaced"> {
124124 let ParserMatchClass = VecListDPairSpacedAsmOperand;
125125 }
126126 // Register list of three D registers spaced by 2 (three Q registers).
152152 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
153153 }
154154 // Register list of two D registers, with "all lanes" subscripting.
155 def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
156 let Name = "VecListTwoDAllLanes";
155 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
156 let Name = "VecListDPairAllLanes";
157157 let ParserMethod = "parseVectorList";
158158 let RenderMethod = "addVecListOperands";
159159 }
160 def VecListTwoDAllLanes : RegisterOperand {
161 let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
160 def VecListDPairAllLanes : RegisterOperand
161 "printVectorListTwoAllLanes"> {
162 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
162163 }
163164 // Register list of two D registers spaced by 2 (two sequential Q registers).
164165 def VecListTwoQAllLanesAsmOperand : AsmOperandClass {
12751276 let Inst{4} = Rn{4};
12761277 let DecoderMethod = "DecodeVLD1DupInstruction";
12771278 }
1278 class VLD1QDUPPseudo : VLDQPseudo {
1279 let Pattern = [(set QPR:$dst,
1280 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1281 }
1282
12831279 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
12841280 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
12851281 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
12861282
1287 def VLD1DUPq8Pseudo : VLD1QDUPPseudo;
1288 def VLD1DUPq16Pseudo : VLD1QDUPPseudo;
1289 def VLD1DUPq32Pseudo : VLD1QDUPPseudo;
1290
12911283 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
12921284 (VLD1DUPd32 addrmode6:$addr)>;
1293 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1294 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1295
1296 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1297
1298 class VLD1QDUP op7_4, string Dt>
1299 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
1285
1286 class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1287 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
13001288 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1301 "vld1", Dt, "$Vd, $Rn", "", []> {
1289 "vld1", Dt, "$Vd, $Rn", "",
1290 [(set VecListDPairAllLanes:$Vd,
1291 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
13021292 let Rm = 0b1111;
13031293 let Inst{4} = Rn{4};
13041294 let DecoderMethod = "DecodeVLD1DupInstruction";
13051295 }
13061296
1307 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1308 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1309 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1310
1297 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1298 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1299 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1300
1301 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1302 (VLD1DUPq32 addrmode6:$addr)>;
1303
1304 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
13111305 // ...with address register writeback:
13121306 multiclass VLD1DUPWB op7_4, string Dt> {
13131307 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
13321326 }
13331327 multiclass VLD1QDUPWB op7_4, string Dt> {
13341328 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1335 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1329 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
13361330 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
13371331 "vld1", Dt, "$Vd, $Rn!",
13381332 "$Rn.addr = $wb", []> {
13421336 let AsmMatchConverter = "cvtVLDwbFixed";
13431337 }
13441338 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1345 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1339 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
13461340 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
13471341 "vld1", Dt, "$Vd, $Rn, $Rm",
13481342 "$Rn.addr = $wb", []> {
13591353 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
13601354 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
13611355 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1362
1363 def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo;
1364 def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo;
1365 def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo;
1366 def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo;
1367 def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo;
1368 def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo;
13691356
13701357 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
13711358 class VLD2DUP op7_4, string Dt, RegisterOperand VdTy>
13771364 let DecoderMethod = "DecodeVLD2DupInstruction";
13781365 }
13791366
1380 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>;
1381 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1382 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1383
1384 def VLD2DUPd8Pseudo : VLDQPseudo;
1385 def VLD2DUPd16Pseudo : VLDQPseudo;
1386 def VLD2DUPd32Pseudo : VLDQPseudo>;
1367 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1368 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1369 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
13871370
13881371 // ...with double-spaced registers (not used for codegen):
13891372 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>;
14131396 }
14141397 }
14151398
1416 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListTwoDAllLanes>;
1417 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1418 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1399 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1400 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1401 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
14191402
14201403 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>;
14211404 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>;
14221405 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1423
1424 def VLD2DUPd8PseudoWB_fixed : VLDQWBfixedPseudo ;
1425 def VLD2DUPd8PseudoWB_register : VLDQWBregisterPseudo;
1426 def VLD2DUPd16PseudoWB_fixed : VLDQWBfixedPseudo ;
1427 def VLD2DUPd16PseudoWB_register : VLDQWBregisterPseudo;
1428 def VLD2DUPd32PseudoWB_fixed : VLDQWBfixedPseudo ;
1429 def VLD2DUPd32PseudoWB_register : VLDQWBregisterPseudo;
14301406
14311407 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
14321408 class VLD3DUP op7_4, string Dt>
11321132 return VectorList.Count == 1;
11331133 }
11341134
1135 bool isVecListTwoDAllLanes() const {
1135 bool isVecListDPairAllLanes() const {
11361136 if (!isSingleSpacedVectorAllLanes()) return false;
1137 return VectorList.Count == 2;
1137 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1138 .contains(VectorList.RegNum));
11381139 }
11391140
11401141 bool isVecListTwoQAllLanes() const {
29802981 case NoLanes:
29812982 E = Parser.getTok().getLoc();
29822983 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2983 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2984
2984 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
29852985 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
29862986 break;
29872987 case AllLanes:
29882988 E = Parser.getTok().getLoc();
2989 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2990 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
29892991 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
29902992 S, E));
29912993 break;
31513153
31523154 switch (LaneKind) {
31533155 case NoLanes:
3154 // Non-lane two-register operands have been converted to the
3156 // Two-register operands have been converted to the
31553157 // composite register classes.
31563158 if (Count == 2) {
31573159 const MCRegisterClass *RC = (Spacing == 1) ?
31643166 (Spacing == 2), S, E));
31653167 break;
31663168 case AllLanes:
3169 // Two-register operands have been converted to the
3170 // composite register classes.
3171 if (Count == 2 && Spacing == 1) {
3172 const MCRegisterClass *RC = &ARMMCRegisterClasses[ARM::DPairRegClassID];
3173 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3174 }
31673175 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
31683176 (Spacing == 2),
31693177 S, E));
20002000
20012001 // First output register
20022002 switch (Inst.getOpcode()) {
2003 case ARM::VLD1q16:
2004 case ARM::VLD1q32:
2005 case ARM::VLD1q64:
2006 case ARM::VLD1q8:
2007 case ARM::VLD1q16wb_fixed:
2008 case ARM::VLD1q16wb_register:
2009 case ARM::VLD1q32wb_fixed:
2010 case ARM::VLD1q32wb_register:
2011 case ARM::VLD1q64wb_fixed:
2012 case ARM::VLD1q64wb_register:
2013 case ARM::VLD1q8wb_fixed:
2014 case ARM::VLD1q8wb_register:
2015 case ARM::VLD2d16:
2016 case ARM::VLD2d32:
2017 case ARM::VLD2d8:
2018 case ARM::VLD2d16wb_fixed:
2019 case ARM::VLD2d16wb_register:
2020 case ARM::VLD2d32wb_fixed:
2021 case ARM::VLD2d32wb_register:
2022 case ARM::VLD2d8wb_fixed:
2023 case ARM::VLD2d8wb_register:
2003 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2004 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2005 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2006 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2007 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2008 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2009 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2010 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2011 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2012
2013 // FIXME: These go in the VLDnDup* functions, not here.
2014 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2015 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2016 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2017 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
20242018 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
20252019 return MCDisassembler::Fail;
20262020 break;
25242518
25252519 align *= (1 << size);
25262520
2527 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2528 return MCDisassembler::Fail;
2521 switch (Inst.getOpcode()) {
2522 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2523 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2524 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2525 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2526 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2527 return MCDisassembler::Fail;
2528 break;
2529 default:
2530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2531 return MCDisassembler::Fail;
2532 break;
2533 }
25292534 if (Rm != 0xF) {
25302535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
25312536 return MCDisassembler::Fail;
25582563 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
25592564 align *= 2*size;
25602565
2561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2562 return MCDisassembler::Fail;
2566 switch (Inst.getOpcode()) {
2567 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2568 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2569 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2570 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2571 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2572 return MCDisassembler::Fail;
2573 break;
2574 default:
2575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2576 return MCDisassembler::Fail;
2577 break;
2578 }
25632579
25642580 if (Rm != 0xF)
25652581 Inst.addOperand(MCOperand::CreateImm(0));
10241024 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
10251025 }
10261026
1027 void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum,
1027 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
10281028 raw_ostream &O) {
10291029 unsigned Reg = MI->getOperand(OpNum).getReg();
10301030 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
10321032 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
10331033 }
10341034
1035 void ARMInstPrinter::printVectorListDPairSpaced(const MCInst *MI,
1036 unsigned OpNum,
1037 raw_ostream &O) {
1035 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1036 unsigned OpNum,
1037 raw_ostream &O) {
10381038 unsigned Reg = MI->getOperand(OpNum).getReg();
10391039 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
10401040 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
10711071 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
10721072 unsigned OpNum,
10731073 raw_ostream &O) {
1074 // Normally, it's not safe to use register enum values directly with
1075 // addition to get the next register, but for VFP registers, the
1076 // sort order is guaranteed because they're all of the form D.
1077 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1078 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
1074 unsigned Reg = MI->getOperand(OpNum).getReg();
1075 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1076 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1077 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
10791078 }
10801079
10811080 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
11011100 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
11021101 }
11031102
1104 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1105 raw_ostream &O) {
1106 // Normally, it's not safe to use register enum values directly with
1107 // addition to get the next register, but for VFP registers, the
1108 // sort order is guaranteed because they're all of the form D.
1109 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1110 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1111 }
1112
11131103 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
11141104 unsigned OpNum,
11151105 raw_ostream &O) {
132132 void printFBits32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
133133 void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
134134 void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
135 void printVectorListDPair(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136 void printVectorListDPairSpaced(const MCInst *MI, unsigned OpNum,
137 raw_ostream &O);
135 void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136 void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
137 raw_ostream &O);
138138 void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
139139 void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
140140 void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
145145 raw_ostream &O);
146146 void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum,
147147 raw_ostream &O);
148 void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
149 raw_ostream &O);
150148 void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
151149 raw_ostream &O);
152150 void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
578578 REG("VecListThreeD");
579579 REG("VecListFourD");
580580 REG("VecListOneDAllLanes");
581 REG("VecListTwoDAllLanes");
581 REG("VecListDPairAllLanes");
582582 REG("VecListTwoQAllLanes");
583583
584584 IMM("i32imm");