llvm.org GIT mirror llvm / c0f64ff
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead of opcode and number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
36 changed file(s) with 400 addition(s) and 356 deletion(s). Raw diff Collapse all Expand all
2626 class Value;
2727 class Function;
2828 class MachineBasicBlock;
29 class TargetInstrInfo;
3029 class TargetInstrDescriptor;
3130 class TargetMachine;
3231 class GlobalValue;
295294 ///
296295 class MachineInstr {
297296 short Opcode; // the opcode
298 short NumImplicitOps; // Number of implicit operands (which
297 unsigned short NumImplicitOps; // Number of implicit operands (which
299298 // are determined at construction time).
300299
301300 std::vector Operands; // the operands
313312 friend struct ilist_traits;
314313
315314 public:
316 /// MachineInstr ctor - This constructor reserves space for numOperand
317 /// operands.
318 MachineInstr(short Opcode, unsigned numOperands);
315 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
316 /// opcode 0 and no operands.
317 MachineInstr();
319318
320319 /// MachineInstr ctor - This constructor create a MachineInstr and add the
321 /// implicit operands. It reserves space for numOperand operands.
322 MachineInstr(const TargetInstrInfo &TII, short Opcode, unsigned numOperands);
320 /// implicit operands. It reserves space for number of operands specified by
321 /// TargetInstrDescriptor.
322 MachineInstr(const TargetInstrDescriptor &TID);
323323
324324 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
325325 /// the MachineInstr is created and added to the end of the specified basic
326326 /// block.
327327 ///
328 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
328 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
329329
330330 ~MachineInstr();
331331
1818
1919 #include "llvm/CodeGen/MachineBasicBlock.h"
2020 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/Target/TargetMachine.h"
2221
2322 namespace llvm {
23
24 class TargetInstrDescriptor;
2425
2526 class MachineInstrBuilder {
2627 MachineInstr *MI;
8283 };
8384
8485 /// BuildMI - Builder interface. Specify how to create the initial instruction
85 /// itself. NumOperands is the number of operands to the machine instruction to
86 /// allow for memory efficient representation of machine instructions.
86 /// itself.
8787 ///
88 inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
89 unsigned NumOperands) {
90 return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands));
88 inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
89 return MachineInstrBuilder(new MachineInstr(TID));
9190 }
9291
9392 /// BuildMI - This version of the builder sets up the first operand as a
94 /// destination virtual register. NumOperands is the number of additional add*
95 /// calls that are expected, not including the destination register.
93 /// destination virtual register.
9694 ///
97 inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
98 unsigned NumOperands, unsigned DestReg) {
99 return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands+1))
100 .addReg(DestReg, true);
95 inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
96 unsigned DestReg) {
97 return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
10198 }
10299
103100 /// BuildMI - This version of the builder inserts the newly-built
104101 /// instruction before the given position in the given MachineBasicBlock, and
105102 /// sets up the first operand as a destination virtual register.
106 /// NumOperands is the number of additional add* calls that are expected,
107 /// not including the destination register.
108103 ///
109104 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
110105 MachineBasicBlock::iterator I,
111 int Opcode, unsigned NumOperands,
106 const TargetInstrDescriptor &TID,
112107 unsigned DestReg) {
113 MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
114 getInstrInfo(), Opcode, NumOperands+1);
108 MachineInstr *MI = new MachineInstr(TID);
115109 BB.insert(I, MI);
116110 return MachineInstrBuilder(MI).addReg(DestReg, true);
117111 }
122116 ///
123117 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
124118 MachineBasicBlock::iterator I,
125 int Opcode, unsigned NumOperands) {
126 MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
127 getInstrInfo(), Opcode, NumOperands);
119 const TargetInstrDescriptor &TID) {
120 MachineInstr *MI = new MachineInstr(TID);
128121 BB.insert(I, MI);
129122 return MachineInstrBuilder(MI);
130123 }
133126 /// instruction at the end of the given MachineBasicBlock, and does NOT take a
134127 /// destination register.
135128 ///
136 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
137 unsigned NumOperands) {
138 return BuildMI(*BB, BB->end(), Opcode, NumOperands);
129 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
130 const TargetInstrDescriptor &TID) {
131 return BuildMI(*BB, BB->end(), TID);
139132 }
140133
141134 /// BuildMI - This version of the builder inserts the newly-built
142135 /// instruction at the end of the given MachineBasicBlock, and sets up the first
143 /// operand as a destination virtual register. NumOperands is the number of
144 /// additional add* calls that are expected, not including the destination
145 /// register.
136 /// operand as a destination virtual register.
146137 ///
147 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
148 unsigned NumOperands, unsigned DestReg) {
149 return BuildMI(*BB, BB->end(), Opcode, NumOperands, DestReg);
138 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
139 const TargetInstrDescriptor &TID,
140 unsigned DestReg) {
141 return BuildMI(*BB, BB->end(), TID, DestReg);
150142 }
151143
152144 } // End llvm namespace
5151
5252
5353 MachineInstr* ilist_traits::createSentinel() {
54 MachineInstr* dummy = new MachineInstr(0, 0);
54 MachineInstr* dummy = new MachineInstr();
5555 LeakDetector::removeGarbageObject(dummy);
5656 return dummy;
5757 }
3131 extern const TargetInstrDescriptor *TargetInstrDescriptors;
3232 }
3333
34 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
35 /// not a resize for them. It is expected that if you use this that you call
36 /// add* methods below to fill up the operands, instead of the Set methods.
37 /// Eventually, the "resizing" ctors will be phased out.
38 ///
39 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
40 : Opcode(opcode), NumImplicitOps(0), parent(0) {
41 Operands.reserve(numOperands);
34 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
35 /// opcode 0 and no operands.
36 MachineInstr::MachineInstr()
37 : Opcode(0), NumImplicitOps(0), parent(0) {
4238 // Make sure that we get added to a machine basicblock
4339 LeakDetector::addGarbageObject(this);
4440 }
7167 }
7268
7369 /// MachineInstr ctor - This constructor create a MachineInstr and add the
74 /// implicit operands. It reserves space for numOperand operands.
75 MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
76 unsigned numOperands)
77 : Opcode(opcode), NumImplicitOps(0), parent(0) {
78 const TargetInstrDescriptor &TID = TII.get(opcode);
70 /// implicit operands. It reserves space for number of operands specified by
71 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
72 /// instructions with variable number of operands).
73 MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
74 : Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
7975 if (TID.ImplicitDefs)
8076 for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
8177 NumImplicitOps++;
8278 if (TID.ImplicitUses)
8379 for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
8480 NumImplicitOps++;
85 Operands.reserve(NumImplicitOps + numOperands);
81 Operands.reserve(NumImplicitOps + TID.numOperands);
8682 addImplicitDefUseOperands(TID);
8783 // Make sure that we get added to a machine basicblock
8884 LeakDetector::addGarbageObject(this);
9187 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
9288 /// MachineInstr is created and added to the end of the specified basic block.
9389 ///
94 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
95 unsigned numOperands)
96 : Opcode(opcode), NumImplicitOps(0), parent(0) {
90 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
91 const TargetInstrDescriptor &TID)
92 : Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
9793 assert(MBB && "Cannot use inserting ctor with null basic block!");
98 const TargetInstrDescriptor &TID = MBB->getParent()->getTarget().
99 getInstrInfo()->get(opcode);
10094 if (TID.ImplicitDefs)
10195 for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
10296 NumImplicitOps++;
10397 if (TID.ImplicitUses)
10498 for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
10599 NumImplicitOps++;
106 Operands.reserve(NumImplicitOps + numOperands);
100 Operands.reserve(NumImplicitOps + TID.numOperands);
107101 addImplicitDefUseOperands(TID);
108102 // Make sure that we get added to a machine basicblock
109103 LeakDetector::addGarbageObject(this);
394394 #endif
395395
396396 // Create the new machine instruction.
397 MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
397 MachineInstr *MI = new MachineInstr(II);
398398
399399 // Add result register values for things that are defined by this
400400 // instruction.
517517
518518 // Create the inline asm machine instruction.
519519 MachineInstr *MI =
520 new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
520 new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
521521
522522 // Add the asm string as an external symbol operand.
523523 const char *AsmStr =
293293 }
294294 unsigned PHIReg = ValueMap[PN];
295295 assert(PHIReg && "PHI node does not have an assigned virtual register!");
296 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
296297 for (unsigned i = 0; i != NumElements; ++i)
297 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
298 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
298299 }
299300 }
300301 }
1818 using namespace llvm;
1919
2020 ARMInstrInfo::ARMInstrInfo()
21 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
21 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
22 RI(*this) {
2223 }
2324
2425 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
5354 const std::vector &Cond)const{
5455 // Can only insert uncond branches so far.
5556 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
56 BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
57 BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
5758 }
1515 #include "ARM.h"
1616 #include "llvm/CodeGen/MachineInstrBuilder.h"
1717 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
1820 #include "llvm/Support/Compiler.h"
1921
2022 using namespace llvm;
5961 RsOp.setReg(Rm);
6062 } else {
6163 unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
62 BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
63 .addImm(ARMShift::LSL);
64 BuildMI(MBB, I, MF.getTarget().getInstrInfo()->get(ARM::MOV),
65 scratch).addReg(Rm).addImm(0).addImm(ARMShift::LSL);
6466 RmOp.setReg(scratch);
6567 }
6668 }
2121 #include "llvm/Target/TargetFrameInfo.h"
2222 #include "llvm/Target/TargetMachine.h"
2323 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Target/TargetInstrInfo.h"
2425 #include "llvm/ADT/STLExtras.h"
2526 #include
2627 using namespace llvm;
3435 return NoFramePointerElim || MFI->hasVarSizedObjects();
3536 }
3637
37 ARMRegisterInfo::ARMRegisterInfo()
38 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
38 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
39 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
40 TII(tii) {
3941 }
4042
4143 void ARMRegisterInfo::
4345 unsigned SrcReg, int FI,
4446 const TargetRegisterClass *RC) const {
4547 assert (RC == ARM::IntRegsRegisterClass);
46 BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
48 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
4749 }
4850
4951 void ARMRegisterInfo::
5153 unsigned DestReg, int FI,
5254 const TargetRegisterClass *RC) const {
5355 assert (RC == ARM::IntRegsRegisterClass);
54 BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
56 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
5557 }
5658
5759 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
6365 RC == ARM::DFPRegsRegisterClass);
6466
6567 if (RC == ARM::IntRegsRegisterClass)
66 BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
68 BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
6769 .addImm(ARMShift::LSL);
6870 else if (RC == ARM::FPRegsRegisterClass)
69 BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
71 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
7072 else
71 BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
73 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
7274 }
7375
7476 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
108110
109111 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
110112 // sub sp, sp, amount
111 BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
113 BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
112114 .addImm(0).addImm(ARMShift::LSL);
113115 } else {
114116 // add sp, sp, amount
115117 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
116 BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
118 BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
117119 .addImm(0).addImm(ARMShift::LSL);
118120 }
119121 }
154156 // Insert a set of r12 with the full address
155157 // r12 = r13 + offset
156158 MachineBasicBlock *MBB2 = MI.getParent();
157 BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
159 BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
158160 .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
159161
160162 // Replace the FrameIndex with r12
190192 MFI->setStackSize(NumBytes);
191193
192194 //sub sp, sp, #NumBytes
193 BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
195 BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
194196 .addImm(0).addImm(ARMShift::LSL);
195197
196198 if (HasFP) {
197 BuildMI(MBB, MBBI, ARM::STR, 3)
199 BuildMI(MBB, MBBI, TII.get(ARM::STR))
198200 .addReg(ARM::R11).addReg(ARM::R13).addImm(0);
199 BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
201 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
200202 addImm(ARMShift::LSL);
201203 }
202204 }
211213 int NumBytes = (int) MFI->getStackSize();
212214
213215 if (hasFP(MF)) {
214 BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
216 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
215217 addImm(ARMShift::LSL);
216 BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
218 BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
217219 }
218220
219221 //add sp, sp, #NumBytes
220 BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
222 BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
221223 .addImm(0).addImm(ARMShift::LSL);
222224 }
223225
2020 namespace llvm {
2121
2222 class Type;
23 class TargetInstrInfo;
2324
2425 struct ARMRegisterInfo : public ARMGenRegisterInfo {
26 const TargetInstrInfo &TII;
2527
26 ARMRegisterInfo();
28 ARMRegisterInfo(const TargetInstrInfo &tii);
2729
2830 /// Code Generation virtual methods...
2931 void storeRegToStackSlot(MachineBasicBlock &MBB,
109109 // One-way branch.
110110 if (FBB == 0) {
111111 if (Cond.empty()) // Unconditional branch
112 BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
112 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
113113 else // Conditional branch
114114 if (isAlphaIntCondCode(Cond[0].getImm()))
115 BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
115 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
116116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
117117 else
118 BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
118 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
119119 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
120120 return;
121121 }
122122
123123 // Two-way Conditional Branch.
124124 if (isAlphaIntCondCode(Cond[0].getImm()))
125 BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
125 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
126126 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
127127 else
128 BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
128 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
129129 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
130 BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB);
130 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
131131 }
132132
133133 static unsigned AlphaRevCondCode(unsigned Opcode) {
229229
230230 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
231231 MachineBasicBlock::iterator MI) const {
232 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
232 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
233233 .addReg(Alpha::R31);
234234 }
235235
1414 #include "Alpha.h"
1515 #include "llvm/CodeGen/MachineFunctionPass.h"
1616 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetInstrInfo.h"
1719 #include "llvm/ADT/SetOperations.h"
1820 #include "llvm/ADT/Statistic.h"
1921 #include "llvm/Support/CommandLine.h"
4143 }
4244
4345 bool runOnMachineFunction(MachineFunction &F) {
46 const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
4447 bool Changed = false;
4548 MachineInstr* prev[3] = {0,0,0};
4649 unsigned count = 0;
6972 prev[0] = prev[1];
7073 prev[1] = prev[2];
7174 prev[2] = 0;
72 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
75 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
7376 .addReg(Alpha::R31);
7477 Changed = true; nopintro += 1;
7578 count += 1;
8083 MI->getOperand(1).getImmedValue()) {
8184 prev[0] = prev[2];
8285 prev[1] = prev[2] = 0;
83 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
86 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
8487 .addReg(Alpha::R31);
85 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
88 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
8689 .addReg(Alpha::R31);
8790 Changed = true; nopintro += 2;
8891 count += 2;
9295 && prev[2]->getOperand(1).getImmedValue() ==
9396 MI->getOperand(1).getImmedValue()) {
9497 prev[0] = prev[1] = prev[2] = 0;
95 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
98 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
9699 .addReg(Alpha::R31);
97 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
100 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
98101 .addReg(Alpha::R31);
99 BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
102 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
100103 .addReg(Alpha::R31);
101104 Changed = true; nopintro += 3;
102105 count += 3;
129132 if (ub || AlignAll) {
130133 //we can align stuff for free at this point
131134 while (count % 4) {
132 BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
135 BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
133136 .addReg(Alpha::R31).addReg(Alpha::R31);
134137 ++count;
135138 ++nopalign;
2424 #include "llvm/Target/TargetFrameInfo.h"
2525 #include "llvm/Target/TargetMachine.h"
2626 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
2728 #include "llvm/Support/CommandLine.h"
2829 #include "llvm/Support/Debug.h"
2930 #include "llvm/ADT/STLExtras.h"
6566 //<< FrameIdx << "\n";
6667 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
6768 if (RC == Alpha::F4RCRegisterClass)
68 BuildMI(MBB, MI, Alpha::STS, 3)
69 BuildMI(MBB, MI, TII.get(Alpha::STS))
6970 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7071 else if (RC == Alpha::F8RCRegisterClass)
71 BuildMI(MBB, MI, Alpha::STT, 3)
72 BuildMI(MBB, MI, TII.get(Alpha::STT))
7273 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7374 else if (RC == Alpha::GPRCRegisterClass)
74 BuildMI(MBB, MI, Alpha::STQ, 3)
75 BuildMI(MBB, MI, TII.get(Alpha::STQ))
7576 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
7677 else
7778 abort();
8586 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
8687 //<< FrameIdx << "\n";
8788 if (RC == Alpha::F4RCRegisterClass)
88 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
89 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
8990 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
9091 else if (RC == Alpha::F8RCRegisterClass)
91 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
92 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
9293 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
9394 else if (RC == Alpha::GPRCRegisterClass)
94 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
95 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
9596 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
9697 else
9798 abort();
115116 unsigned InReg = MI->getOperand(1).getReg();
116117 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
117118 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
118 NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
119 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
119120 .addReg(Alpha::F31);
120121 } else { // load -> move
121122 unsigned OutReg = MI->getOperand(0).getReg();
122123 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
123124 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
124 NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
125 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
125126 .addReg(Alpha::F31);
126127 }
127128 }
139140 const TargetRegisterClass *RC) const {
140141 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
141142 if (RC == Alpha::GPRCRegisterClass) {
142 BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
143 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
143144 } else if (RC == Alpha::F4RCRegisterClass) {
144 BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
145 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
145146 } else if (RC == Alpha::F8RCRegisterClass) {
146 BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
147 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
147148 } else {
148149 std::cerr << "Attempt to copy register that is not GPR or FPR";
149150 abort();
208209
209210 MachineInstr *New;
210211 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
211 New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
212 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
212213 .addImm(-Amount).addReg(Alpha::R30);
213214 } else {
214215 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
215 New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
216 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
216217 .addImm(Amount).addReg(Alpha::R30);
217218 }
218219
269270 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
270271 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
271272 //insert the new
272 MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28)
273 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
273274 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
274275 MBB.insert(II, nMI);
275276 } else {
287288 static int curgpdist = 0;
288289
289290 //handle GOP offset
290 BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
291 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
291292 .addGlobalAddress(const_cast(MF.getFunction()))
292293 .addReg(Alpha::R27).addImm(++curgpdist);
293 BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
294 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
294295 .addGlobalAddress(const_cast(MF.getFunction()))
295296 .addReg(Alpha::R29).addImm(curgpdist);
296297
297298 //evil const_cast until MO stuff setup to handle const
298 BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
299 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
299300 .addGlobalAddress(const_cast(MF.getFunction()));
300301
301302 // Get the number of bytes to allocate from the FrameInfo
326327 // adjust stack pointer: r30 -= numbytes
327328 NumBytes = -NumBytes;
328329 if (NumBytes >= IMM_LOW) {
329 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
330 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
330331 .addReg(Alpha::R30);
331332 } else if (getUpper16(NumBytes) >= IMM_LOW) {
332 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
333 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
333334 .addReg(Alpha::R30);
334 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
335 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
335336 .addReg(Alpha::R30);
336337 } else {
337338 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
341342 //now if we need to, save the old FP and set the new
342343 if (FP)
343344 {
344 BuildMI(MBB, MBBI, Alpha::STQ, 3)
345 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
345346 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
346347 //this must be the last instr in the prolog
347 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15)
348 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
348349 .addReg(Alpha::R30).addReg(Alpha::R30);
349350 }
350351
367368 if (FP)
368369 {
369370 //copy the FP into the SP (discards allocas)
370 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15)
371 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
371372 .addReg(Alpha::R15);
372373 //restore the FP
373 BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
374 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
374375 }
375376
376377 if (NumBytes != 0)
377378 {
378379 if (NumBytes <= IMM_HIGH) {
379 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
380 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
380381 .addReg(Alpha::R30);
381382 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
382 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
383 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
383384 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
384 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
385 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
385386 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
386387 } else {
387388 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
1818
1919 namespace llvm {
2020
21 class TargetInstrInfo;
2122 class Type;
2223
2324 struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
2020 //===----------------------------------------------------------------------===//
2121
2222 #include "IA64.h"
23 #include "IA64InstrInfo.h"
24 #include "IA64TargetMachine.h"
2325 #include "llvm/CodeGen/MachineFunctionPass.h"
2426 #include "llvm/CodeGen/MachineInstrBuilder.h"
2527 #include "llvm/ADT/SetOperations.h"
98100
99101 if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
100102 // there is a conflict, insert a stop and reset PendingRegWrites
101 CurrentInsn = BuildMI(MBB, CurrentInsn, IA64::STOP, 0);
103 CurrentInsn = BuildMI(MBB, CurrentInsn,
104 TM.getInstrInfo()->get(IA64::STOP), 0);
102105 PendingRegWrites=OrigWrites; // carry over current writes to next insn
103106 Changed=true; StopBitsAdded++; // update stats
104107 } else { // otherwise, track additional pending writes
138138 //
139139 MachineFunction &MF = DAG.getMachineFunction();
140140 MachineFrameInfo *MFI = MF.getFrameInfo();
141 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
141142
142143 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
143144 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
224225 // Create a vreg to hold the output of (what will become)
225226 // the "alloc" instruction
226227 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
227 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
228 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
228229 // we create a PSEUDO_ALLOC (pseudo)instruction for now
229230 /*
230231 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
254255 // here we actually do the moving of args, and store them to the stack
255256 // too if this is a varargs function:
256257 for (int i = 0; i < count && i < 8; ++i) {
257 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
258 BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
258259 if(F.isVarArg()) {
259260 // if this is a varargs function, we copy the input registers to the stack
260261 int FI = MFI->CreateFixedObject(8, tempOffset);
261262 tempOffset+=8; //XXX: is it safe to use r22 like this?
262 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
263 BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
263264 // FIXME: we should use st8.spill here, one day
264 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
265 BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
265266 }
266267 }
267268
1818 using namespace llvm;
1919
2020 IA64InstrInfo::IA64InstrInfo()
21 : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])) {
21 : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
22 RI(*this) {
2223 }
2324
2425
5051 const std::vector &Cond)const {
5152 // Can only insert uncond branches so far.
5253 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
53 BuildMI(&MBB, IA64::BRL_NOTCALL, 1).addMBB(TBB);
54 BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
5455 }
2525 #include "llvm/Target/TargetFrameInfo.h"
2626 #include "llvm/Target/TargetMachine.h"
2727 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
2829 #include "llvm/Support/CommandLine.h"
2930 #include "llvm/ADT/STLExtras.h"
3031 #include
3132 using namespace llvm;
3233
3334
34 IA64RegisterInfo::IA64RegisterInfo()
35 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
35 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
37 TII(tii) {}
3638
3739 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3840 MachineBasicBlock::iterator MI,
4042 const TargetRegisterClass *RC) const{
4143
4244 if (RC == IA64::FPRegisterClass) {
43 BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
45 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx).addReg(SrcReg);
4446 } else if (RC == IA64::GRRegisterClass) {
45 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
47 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(SrcReg);
4648 }
4749 else if (RC == IA64::PRRegisterClass) {
4850 /* we use IA64::r2 as a temporary register for doing this hackery. */
4951 // first we load 0:
50 BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
52 BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
5153 // then conditionally add 1:
52 BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
54 BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
5355 .addImm(1).addReg(SrcReg);
5456 // and then store it to the stack
55 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
57 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
5658 } else assert(0 &&
5759 "sorry, I don't know how to store this sort of reg in the stack\n");
5860 }
6365 const TargetRegisterClass *RC)const{
6466
6567 if (RC == IA64::FPRegisterClass) {
66 BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
68 BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
6769 } else if (RC == IA64::GRRegisterClass) {
68 BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
70 BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
6971 } else if (RC == IA64::PRRegisterClass) {
7072 // first we load a byte from the stack into r2, our 'predicate hackery'
7173 // scratch reg
72 BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
74 BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
7375 // then we compare it to zero. If it _is_ zero, compare-not-equal to
7476 // r0 gives us 0, which is what we want, so that's nice.
75 BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
77 BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
7678 } else assert(0 &&
7779 "sorry, I don't know how to load this sort of reg from the stack\n");
7880 }
8486
8587 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
8688 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
87 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
89 BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
8890 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
8991 else // otherwise, MOV works (for both gen. regs and FP regs)
90 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
92 BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
9193 }
9294
9395 const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
120122 void IA64RegisterInfo::
121123 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
122124 MachineBasicBlock::iterator I) const {
123 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
124125 if (hasFP(MF)) {
125126 // If we have a frame pointer, turn the adjcallstackup instruction into a
126127 // 'sub SP, ' and the adjcallstackdown instruction into 'add SP,
136137
137138 MachineInstr *New;
138139 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
139 New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
140 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
140141 .addImm(-Amount);
141142 } else {
142143 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
143 New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
144 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
144145 .addImm(Amount);
145146 }
146147
157158 MachineInstr &MI = *II;
158159 MachineBasicBlock &MBB = *MI.getParent();
159160 MachineFunction &MF = *MBB.getParent();
160 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
161161
162162 bool FP = hasFP(MF);
163163
186186 // Fix up the old:
187187 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
188188 //insert the new
189 MachineInstr* nMI=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r22)
189 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
190190 .addReg(BaseRegister).addImm(Offset);
191191 MBB.insert(II, nMI);
192192 } else { // it's big
193193 //fix up the old:
194194 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
195195 MachineInstr* nMI;
196 nMI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
196 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
197197 MBB.insert(II, nMI);
198 nMI=BuildMI(TII, IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
198 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
199199 .addReg(IA64::r22);
200200 MBB.insert(II, nMI);
201201 }
206206 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
207207 MachineBasicBlock::iterator MBBI = MBB.begin();
208208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
210209 MachineInstr *MI;
211210 bool FP = hasFP(MF);
212211
251250 }
252251 }
253252
254 MI=BuildMI(TII, IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0). \
253 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
255254 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
256255 MBB.insert(MBBI, MI);
257256
283282
284283 // adjust stack pointer: r12 -= numbytes
285284 if (NumBytes <= 8191) {
286 MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
285 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
287286 addImm(-NumBytes);
288287 MBB.insert(MBBI, MI);
289288 } else { // we use r22 as a scratch register here
290 MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
289 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
291290 // FIXME: MOVLSI32 expects a _u_32imm
292291 MBB.insert(MBBI, MI); // first load the decrement into r22
293 MI=BuildMI(TII,IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
292 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
294293 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
295294 }
296295
297296 // now if we need to, save the old FP and set the new
298297 if (FP) {
299 MI = BuildMI(TII, IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
298 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
300299 MBB.insert(MBBI, MI);
301300 // this must be the last instr in the prolog ? (XXX: why??)
302 MI = BuildMI(TII, IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
301 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
303302 MBB.insert(MBBI, MI);
304303 }
305304
308307 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
309308 MachineBasicBlock &MBB) const {
310309 const MachineFrameInfo *MFI = MF.getFrameInfo();
311 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
312310 MachineBasicBlock::iterator MBBI = prior(MBB.end());
313311 MachineInstr *MI;
314312 assert(MBBI->getOpcode() == IA64::RET &&
323321 if (FP)
324322 {
325323 //copy the FP into the SP (discards allocas)
326 MI=BuildMI(TII, IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
324 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
327325 MBB.insert(MBBI, MI);
328326 //restore the FP
329 MI=BuildMI(TII, IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
327 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
330328 MBB.insert(MBBI, MI);
331329 }
332330
333331 if (NumBytes != 0)
334332 {
335333 if (NumBytes <= 8191) {
336 MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
334 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
337335 addImm(NumBytes);
338336 MBB.insert(MBBI, MI);
339337 } else {
340 MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
338 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
341339 MBB.insert(MBBI, MI);
342 MI=BuildMI(TII, IA64::ADD, 2, IA64::r12).addReg(IA64::r12).
340 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
343341 addReg(IA64::r22);
344342 MBB.insert(MBBI, MI);
345343 }
2020
2121 namespace llvm {
2222
23 class TargetInstrInfo;
24
2325 struct IA64RegisterInfo : public IA64GenRegisterInfo {
24 IA64RegisterInfo();
26 const TargetInstrInfo &TII;
27
28 IA64RegisterInfo(const TargetInstrInfo &tii);
2529
2630 /// Code Generation virtual methods...
2731 void storeRegToStackSlot(MachineBasicBlock &MBB,
7272
7373
7474 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
75 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
7576 // Give the blocks of the function a dense, in-order, numbering.
7677 Fn.RenumberBlocks();
7778 BlockSizes.resize(Fn.getNumBlockIDs());
164165 MachineInstr *OldBranch = I;
165166
166167 // Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
167 BuildMI(MBB, I, PPC::BCC, 3)
168 BuildMI(MBB, I, TII->get(PPC::BCC))
168169 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
169170
170171 // Uncond branch to the real destination.
171 I = BuildMI(MBB, I, PPC::B, 1).addMBB(Dest);
172 I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest);
172173
173174 // Remove the old branch from the function.
174175 OldBranch->eraseFromParent();
249249 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
250250 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
251251
252 const TargetInstrInfo &TII = *TM.getInstrInfo();
252253 MachineBasicBlock &EntryBB = *Fn.begin();
253254 // Emit the following code into the entry block:
254255 // InVRSAVE = MFVRSAVE
255256 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
256257 // MTVRSAVE UpdatedVRSAVE
257258 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
258 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
259 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
260 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
259 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
260 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
261 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
261262
262263 // Find all return blocks, outputting a restore in each epilog.
263 const TargetInstrInfo &TII = *TM.getInstrInfo();
264264 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
265265 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
266266 IP = BB->end(); --IP;
272272 IP = I2;
273273
274274 // Emit: MTVRSAVE InVRSave
275 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
275 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
276276 }
277277 }
278278 }
283283 ///
284284 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
285285 if (!GlobalBaseReg) {
286 const TargetInstrInfo &TII = *TM.getInstrInfo();
286287 // Insert the set of GlobalBaseReg into the first MBB of the function
287288 MachineBasicBlock &FirstMBB = BB->getParent()->front();
288289 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
290291
291292 if (PPCLowering.getPointerTy() == MVT::i32) {
292293 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
293 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
294 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
294 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
295 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
295296 } else {
296297 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
297 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR8, 0, PPC::LR8);
298 BuildMI(FirstMBB, MBBI, PPC::MFLR8, 1, GlobalBaseReg);
298 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
299 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
299300 }
300301 }
301302 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
25922592 MachineBasicBlock *
25932593 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
25942594 MachineBasicBlock *BB) {
2595 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
25952596 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
25962597 MI->getOpcode() == PPC::SELECT_CC_I8 ||
25972598 MI->getOpcode() == PPC::SELECT_CC_F4 ||
26172618 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
26182619 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
26192620 unsigned SelectPred = MI->getOperand(4).getImm();
2620 BuildMI(BB, PPC::BCC, 3)
2621 BuildMI(BB, TII->get(PPC::BCC))
26212622 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
26222623 MachineFunction *F = BB->getParent();
26232624 F->getBasicBlockList().insert(It, copy0MBB);
26462647 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
26472648 // ...
26482649 BB = sinkMBB;
2649 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2650 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
26502651 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
26512652 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
26522653
170170
171171 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
172172 MachineBasicBlock::iterator MI) const {
173 BuildMI(MBB, MI, PPC::NOP, 0);
173 BuildMI(MBB, MI, get(PPC::NOP));
174174 }
175175
176176
256256 // One-way branch.
257257 if (FBB == 0) {
258258 if (Cond.empty()) // Unconditional branch
259 BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
259 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
260260 else // Conditional branch
261 BuildMI(&MBB, PPC::BCC, 3)
261 BuildMI(&MBB, get(PPC::BCC))
262262 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
263263 return;
264264 }
265265
266266 // Two-way Conditional Branch.
267 BuildMI(&MBB, PPC::BCC, 3)
267 BuildMI(&MBB, get(PPC::BCC))
268268 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
269 BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
269 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
270270 }
271271
272272 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
102102 const TargetRegisterClass *RC) const {
103103 if (RC == PPC::GPRCRegisterClass) {
104104 if (SrcReg != PPC::LR) {
105 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
105 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
106 FrameIdx);
106107 } else {
107108 // FIXME: this spills LR immediately to memory in one step. To do this,
108109 // we use R11, which we know cannot be used in the prolog/epilog. This is
109110 // a hack.
110 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
111 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
111 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
112 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
112113 FrameIdx);
113114 }
114115 } else if (RC == PPC::G8RCRegisterClass) {
115116 if (SrcReg != PPC::LR8) {
116 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg), FrameIdx);
117 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
118 FrameIdx);
117119 } else {
118120 // FIXME: this spills LR immediately to memory in one step. To do this,
119121 // we use R11, which we know cannot be used in the prolog/epilog. This is
120122 // a hack.
121 BuildMI(MBB, MI, PPC::MFLR8, 1, PPC::X11);
122 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(PPC::X11),
123 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
124 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
123125 FrameIdx);
124126 }
125127 } else if (RC == PPC::F8RCRegisterClass) {
126 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
128 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
129 FrameIdx);
127130 } else if (RC == PPC::F4RCRegisterClass) {
128 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
131 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
132 FrameIdx);
129133 } else if (RC == PPC::CRRCRegisterClass) {
130134 // FIXME: We use R0 here, because it isn't available for RA.
131135 // We need to store the CR in the low 4-bits of the saved value. First,
132136 // issue a MFCR to save all of the CRBits.
133 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
137 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
134138
135139 // If the saved register wasn't CR0, shift the bits left so that they are in
136140 // CR0's slot.
137141 if (SrcReg != PPC::CR0) {
138142 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
139143 // rlwinm r0, r0, ShiftBits, 0, 31.
140 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
144 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
141145 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
142146 }
143147
144 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
148 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
149 FrameIdx);
145150 } else if (RC == PPC::VRRCRegisterClass) {
146151 // We don't have indexed addressing for vector loads. Emit:
147152 // R11 = ADDI FI#
148153 // Dest = LVX R0, R11
149154 //
150155 // FIXME: We use R0 here, because it isn't available for RA.
151 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
152 BuildMI(MBB, MI, PPC::STVX, 3)
156 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
157 FrameIdx, 0, 0);
158 BuildMI(MBB, MI, TII.get(PPC::STVX))
153159 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
154160 } else {
155161 assert(0 && "Unknown regclass!");
164170 const TargetRegisterClass *RC) const {
165171 if (RC == PPC::GPRCRegisterClass) {
166172 if (DestReg != PPC::LR) {
167 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
173 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
168174 } else {
169 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
170 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
176 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
171177 }
172178 } else if (RC == PPC::G8RCRegisterClass) {
173179 if (DestReg != PPC::LR8) {
174 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
180 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
175181 } else {
176 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, PPC::R11), FrameIdx);
177 BuildMI(MBB, MI, PPC::MTLR8, 1).addReg(PPC::R11);
182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
183 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
178184 }
179185 } else if (RC == PPC::F8RCRegisterClass) {
180 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
186 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
181187 } else if (RC == PPC::F4RCRegisterClass) {
182 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
183189 } else if (RC == PPC::CRRCRegisterClass) {
184190 // FIXME: We use R0 here, because it isn't available for RA.
185 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
191 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
186192
187193 // If the reloaded register isn't CR0, shift the bits right so that they are
188194 // in the right CR's slot.
189195 if (DestReg != PPC::CR0) {
190196 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
191197 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
192 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
198 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
193199 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
194200 }
195201
196 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
202 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
197203 } else if (RC == PPC::VRRCRegisterClass) {
198204 // We don't have indexed addressing for vector loads. Emit:
199205 // R11 = ADDI FI#
200206 // Dest = LVX R0, R11
201207 //
202208 // FIXME: We use R0 here, because it isn't available for RA.
203 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
204 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
209 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
210 FrameIdx, 0, 0);
211 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
205212 } else {
206213 assert(0 && "Unknown regclass!");
207214 abort();
213220 unsigned DestReg, unsigned SrcReg,
214221 const TargetRegisterClass *RC) const {
215222 if (RC == PPC::GPRCRegisterClass) {
216 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
223 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
217224 } else if (RC == PPC::G8RCRegisterClass) {
218 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
225 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
219226 } else if (RC == PPC::F4RCRegisterClass) {
220 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
227 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
221228 } else if (RC == PPC::F8RCRegisterClass) {
222 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
229 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
223230 } else if (RC == PPC::CRRCRegisterClass) {
224 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
231 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
225232 } else if (RC == PPC::VRRCRegisterClass) {
226 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
233 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
227234 } else {
228235 std::cerr << "Attempt to copy register that is not GPR or FPR";
229236 abort();
344351 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
345352 if (OpNum == 0) { // move -> store
346353 unsigned InReg = MI->getOperand(1).getReg();
347 NewMI = addFrameReference(BuildMI(TII, PPC::STW,
348 3).addReg(InReg), FrameIndex);
354 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
355 FrameIndex);
349356 } else { // move -> load
350357 unsigned OutReg = MI->getOperand(0).getReg();
351 NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
358 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
359 FrameIndex);
352360 }
353361 } else if ((Opc == PPC::OR8 &&
354362 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
355363 if (OpNum == 0) { // move -> store
356364 unsigned InReg = MI->getOperand(1).getReg();
357 NewMI = addFrameReference(BuildMI(TII, PPC::STD,
358 3).addReg(InReg), FrameIndex);
365 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
366 FrameIndex);
359367 } else { // move -> load
360368 unsigned OutReg = MI->getOperand(0).getReg();
361 NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
369 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
362370 }
363371 } else if (Opc == PPC::FMRD) {
364372 if (OpNum == 0) { // move -> store
365373 unsigned InReg = MI->getOperand(1).getReg();
366 NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
367 3).addReg(InReg), FrameIndex);
374 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
375 FrameIndex);
368376 } else { // move -> load
369377 unsigned OutReg = MI->getOperand(0).getReg();
370 NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
378 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
371379 }
372380 } else if (Opc == PPC::FMRS) {
373381 if (OpNum == 0) { // move -> store
374382 unsigned InReg = MI->getOperand(1).getReg();
375 NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
376 3).addReg(InReg), FrameIndex);
383 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
384 FrameIndex);
377385 } else { // move -> load
378386 unsigned OutReg = MI->getOperand(0).getReg();
379 NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
387 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
380388 }
381389 }
382390
454462 // Constructing the constant and adding would take 3 instructions.
455463 // Fortunately, a frame greater than 32K is rare.
456464 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
457 BuildMI(MBB, II, PPC::ADDI, 2, PPC::R0)
465 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
458466 .addReg(PPC::R31)
459467 .addImm(FrameSize);
460468 } else if (LP64) {
461 BuildMI(MBB, II, PPC::LD, 2, PPC::X0)
469 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
462470 .addImm(0)
463471 .addReg(PPC::X1);
464472 } else {
465 BuildMI(MBB, II, PPC::LWZ, 2, PPC::R0)
473 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
466474 .addImm(0)
467475 .addReg(PPC::R1);
468476 }
470478 // Grow the stack and update the stack pointer link, then
471479 // determine the address of new allocated space.
472480 if (LP64) {
473 BuildMI(MBB, II, PPC::STDUX, 3)
481 BuildMI(MBB, II, TII.get(PPC::STDUX))
474482 .addReg(PPC::X0)
475483 .addReg(PPC::X1)
476484 .addReg(MI.getOperand(1).getReg());
477 BuildMI(MBB, II, PPC::ADDI8, 2, MI.getOperand(0).getReg())
485 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
478486 .addReg(PPC::X1)
479487 .addImm(maxCallFrameSize);
480488 } else {
481 BuildMI(MBB, II, PPC::STWUX, 3)
489 BuildMI(MBB, II, TII.get(PPC::STWUX))
482490 .addReg(PPC::R0)
483491 .addReg(PPC::R1)
484492 .addReg(MI.getOperand(1).getReg());
485 BuildMI(MBB, II, PPC::ADDI, 2, MI.getOperand(0).getReg())
493 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
486494 .addReg(PPC::R1)
487495 .addImm(maxCallFrameSize);
488496 }
558566
559567 if (!isInt16(Offset)) {
560568 // Insert a set of r0 with the full offset value before the ld, st, or add
561 BuildMI(MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
562 BuildMI(MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
569 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
570 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
563571
564572 // convert into indexed form of the instruction
565573 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
639647 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
640648 // instruction selector. Based on the vector registers that have been used,
641649 // transform this into the appropriate ORI instruction.
642 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
650 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
651 const TargetInstrInfo &TII) {
643652 unsigned UsedRegMask = 0;
644653 for (unsigned i = 0; i != 32; ++i)
645654 if (UsedRegs[VRRegNo[i]])
669678 RemoveVRSaveCode(MI);
670679 return;
671680 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
672 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
681 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
673682 .addReg(SrcReg).addImm(UsedRegMask);
674683 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
675 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
684 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
676685 .addReg(SrcReg).addImm(UsedRegMask >> 16);
677686 } else {
678 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
687 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
679688 .addReg(SrcReg).addImm(UsedRegMask >> 16);
680 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
689 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
681690 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
682691 }
683692
749758 // process it.
750759 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
751760 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
752 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
761 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
753762 break;
754763 }
755764 }
774783 int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
775784
776785 if (!Subtarget.isPPC64()) {
777 BuildMI(MBB, MBBI, PPC::STW, 3)
786 BuildMI(MBB, MBBI, TII.get(PPC::STW))
778787 .addReg(PPC::R31).addImm(Offset).addReg(PPC::R1);
779788 } else {
780 BuildMI(MBB, MBBI, PPC::STD, 3)
789 BuildMI(MBB, MBBI, TII.get(PPC::STD))
781790 .addReg(PPC::X31).addImm(Offset/4).addReg(PPC::X1);
782791 }
783792 }
793802 if (MaxAlign > TargetAlign) {
794803 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
795804 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
796 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
805 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
797806 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
798 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
807 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
799808 .addImm(NegFrameSize);
800 BuildMI(MBB, MBBI, PPC::STWUX, 3)
809 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
801810 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
802811 } else if (isInt16(NegFrameSize)) {
803 BuildMI(MBB, MBBI, PPC::STWU, 3,
812 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
804813 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
805814 } else {
806 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegFrameSize >> 16);
807 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
815 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
816 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
808817 .addImm(NegFrameSize & 0xFFFF);
809 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
818 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
810819 .addReg(PPC::R0);
811820 }
812821 } else { // PPC64.
813822 if (MaxAlign > TargetAlign) {
814823 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
815824 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
816 BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
825 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
817826 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
818 BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
827 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
819828 .addImm(NegFrameSize);
820 BuildMI(MBB, MBBI, PPC::STDUX, 3)
829 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
821830 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
822831 } else if (isInt16(NegFrameSize)) {
823 BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
832 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
824833 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
825834 } else {
826 BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegFrameSize >> 16);
827 BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
835 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
836 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
828837 .addImm(NegFrameSize & 0xFFFF);
829 BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1)
838 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
830839 .addReg(PPC::X0);
831840 }
832841 }
836845 unsigned LabelID = DebugInfo->NextLabelID();
837846
838847 // Mark effective beginning of when frame pointer becomes valid.
839 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
848 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(LabelID);
840849
841850 // Show update of SP.
842851 MachineLocation SPDst(MachineLocation::VirtualFP);
856865 // If there is a frame pointer, copy R1 into R31
857866 if (HasFP) {
858867 if (!Subtarget.isPPC64()) {
859 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
868 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
869 .addReg(PPC::R1);
860870 } else {
861 BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1);
871 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
872 .addReg(PPC::X1);
862873 }
863874 }
864875 }
883894 if (!Subtarget.isPPC64()) {
884895 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
885896 !MFI->hasVarSizedObjects()) {
886 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
897 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
887898 .addReg(PPC::R1).addImm(FrameSize);
888899 } else {
889 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
900 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
890901 }
891902 } else {
892903 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
893904 !MFI->hasVarSizedObjects()) {
894 BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1)
905 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
895906 .addReg(PPC::X1).addImm(FrameSize);
896907 } else {
897 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1);
908 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
898909 }
899910 }
900911
904915 int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
905916
906917 if (!Subtarget.isPPC64()) {
907 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
918 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
908919 .addImm(Offset).addReg(PPC::R1);
909920 } else {
910 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31)
921 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
911922 .addImm(Offset/4).addReg(PPC::X1);
912923 }
913924 }
1919
2020 namespace llvm {
2121 class PPCSubtarget;
22 class TargetInstrInfo;
2223 class Type;
2324
2425 class PPCRegisterInfo : public PPCGenRegisterInfo {
6363 if (TII->hasDelaySlot(I->getOpcode())) {
6464 MachineBasicBlock::iterator J = I;
6565 ++J;
66 BuildMI(MBB, J, SP::NOP, 0);
66 BuildMI(MBB, J, TII->get(SP::NOP));
6767 ++FilledSlots;
6868 Changed = true;
6969 }
1515 #include "llvm/CodeGen/MachineFunctionPass.h"
1616 #include "llvm/CodeGen/MachineInstrBuilder.h"
1717 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetInstrInfo.h"
1819 #include "llvm/ADT/Statistic.h"
1920 #include "llvm/Support/Debug.h"
2021 #include
108109 DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
109110 // Insert copy for the other half of the double.
110111 if (DestDReg != SrcDReg) {
111 MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
112 MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
113 .addReg(OddSrcReg);
112114 DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
113115 }
114116 ++NumFpDs;
872872 MachineBasicBlock *
873873 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
874874 MachineBasicBlock *BB) {
875 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
875876 unsigned BROpcode;
876877 unsigned CC;
877878 // Figure out the conditional branch opcode to use for this select_cc.
907908 MachineBasicBlock *thisMBB = BB;
908909 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
909910 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
910 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
911 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
911912 MachineFunction *F = BB->getParent();
912913 F->getBasicBlockList().insert(It, copy0MBB);
913914 F->getBasicBlockList().insert(It, sinkMBB);
935936 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
936937 // ...
937938 BB = sinkMBB;
938 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
939 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
939940 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
940941 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
941942
101101 const std::vector &Cond)const{
102102 // Can only insert uncond branches so far.
103103 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
104 BuildMI(&MBB, SP::BA, 1).addMBB(TBB);
104 BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
105105 }
1717 #include "llvm/CodeGen/MachineFunction.h"
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
1919 #include "llvm/CodeGen/MachineLocation.h"
20 #include "llvm/Target/TargetInstrInfo.h"
2021 #include "llvm/Type.h"
2122 #include "llvm/ADT/STLExtras.h"
2223 #include
3435 const TargetRegisterClass *RC) const {
3536 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
3637 if (RC == SP::IntRegsRegisterClass)
37 BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
38 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
39 .addReg(SrcReg);
3840 else if (RC == SP::FPRegsRegisterClass)
39 BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
41 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
42 .addReg(SrcReg);
4043 else if (RC == SP::DFPRegsRegisterClass)
41 BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
44 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
45 .addReg(SrcReg);
4246 else
4347 assert(0 && "Can't store this register to stack slot");
4448 }
4852 unsigned DestReg, int FI,
4953 const TargetRegisterClass *RC) const {
5054 if (RC == SP::IntRegsRegisterClass)
51 BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
55 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
5256 else if (RC == SP::FPRegsRegisterClass)
53 BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
57 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
5458 else if (RC == SP::DFPRegsRegisterClass)
55 BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
59 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
5660 else
5761 assert(0 && "Can't load this register from stack slot");
5862 }
6266 unsigned DestReg, unsigned SrcReg,
6367 const TargetRegisterClass *RC) const {
6468 if (RC == SP::IntRegsRegisterClass)
65 BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
69 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
6670 else if (RC == SP::FPRegsRegisterClass)
67 BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
71 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
6872 else if (RC == SP::DFPRegsRegisterClass)
69 BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
70 1, DestReg).addReg(SrcReg);
73 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
74 .addReg(SrcReg);
7175 else
7276 assert (0 && "Can't copy this register");
7377 }
8286 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
8387 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
8488 if (OpNum == 0) // COPY -> STORE
85 NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
89 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
8690 .addReg(MI->getOperand(2).getReg());
8791 else // COPY -> LOAD
88 NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
92 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
8993 .addFrameIndex(FI).addImm(0);
9094 }
9195 break;
9498 // FALLTHROUGH
9599 case SP::FMOVD:
96100 if (OpNum == 0) // COPY -> STORE
97 NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
101 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
98102 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
99103 else // COPY -> LOAD
100 NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
104 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
101105 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
102106 break;
103107 }
127131 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
128132 Size = -Size;
129133 if (Size)
130 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
134 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
131135 MBB.erase(I);
132136 }
133137
157161 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
158162 // scavenge a register here instead of reserving G1 all of the time.
159163 unsigned OffHi = (unsigned)Offset >> 10U;
160 BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
164 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
161165 // Emit G1 = G1 + I6
162 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
163 SP::G1).addReg(SP::G1).addReg(SP::I6);
166 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
167 .addReg(SP::I6);
164168 // Insert: G1+%lo(offset) into the user.
165169 MI.getOperand(i).ChangeToRegister(SP::G1, false);
166170 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
191195 NumBytes = -NumBytes;
192196
193197 if (NumBytes >= -4096) {
194 BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
198 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
195199 SP::O6).addImm(NumBytes).addReg(SP::O6);
196200 } else {
197201 MachineBasicBlock::iterator InsertPt = MBB.begin();
198202 // Emit this the hard way. This clobbers G1 which we always know is
199203 // available here.
200204 unsigned OffHi = (unsigned)NumBytes >> 10U;
201 BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
205 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
202206 // Emit G1 = G1 + I6
203 BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
207 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
204208 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
205 BuildMI(MBB, InsertPt, SP::SAVErr, 2,
206 SP::O6).addReg(SP::O6).addReg(SP::G1);
209 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
210 .addReg(SP::O6).addReg(SP::G1);
207211 }
208212 }
209213
212216 MachineBasicBlock::iterator MBBI = prior(MBB.end());
213217 assert(MBBI->getOpcode() == SP::RETL &&
214218 "Can only put epilog before 'retl' instruction!");
215 BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
219 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
220 .addReg(SP::G0);
216221 }
217222
218223 unsigned SparcRegisterInfo::getRARegister() const {
1919 namespace llvm {
2020
2121 class SparcSubtarget;
22 class TargetInstrInfo;
2223 class Type;
2324
2425 struct SparcRegisterInfo : public SparcGenRegisterInfo {
106106 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
107107 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
108108 if (!isAtTop(RegNo)) {
109 MachineFunction *MF = I->getParent()->getParent();
110 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
111
109112 unsigned STReg = getSTReg(RegNo);
110113 unsigned RegOnTop = getStackEntry(0);
111114
117120 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
118121
119122 // Emit an fxch to update the runtime processors version of the state
120 BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
123 BuildMI(*MBB, I, TII.get(X86::FXCH)).addReg(STReg);
121124 NumFXCH++;
122125 }
123126 }
124127
125128 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
129 MachineFunction *MF = I->getParent()->getParent();
130 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
126131 unsigned STReg = getSTReg(RegNo);
127132 pushReg(AsReg); // New register on top of stack
128133
129 BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
134 BuildMI(*MBB, I, TII.get(X86::FLDrr)).addReg(STReg);
130135 }
131136
132137 // popStackAfter - Pop the current value off of the top of the FP stack
434439 I->RemoveOperand(0);
435440
436441 } else { // Insert an explicit pop
437 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
442 MachineFunction *MF = I->getParent()->getParent();
443 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
444 I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(X86::ST0);
438445 }
439446 }
440447
458465 RegMap[TopReg] = OldSlot;
459466 RegMap[FPRegNo] = ~0;
460467 Stack[--StackTop] = ~0;
461 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
468 MachineFunction *MF = I->getParent()->getParent();
469 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
470 I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(STReg);
462471 }
463472
464473
696705
697706 // Replace the old instruction with a new instruction
698707 MBB->remove(I++);
699 I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
708 I = BuildMI(*MBB, I, TII.get(Opcode)).addReg(getSTReg(NotTOS));
700709
701710 // If both operands are killed, pop one off of the stack in addition to
702711 // overwriting the other one.
524524
525525 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
526526 if (ContainsFPCode) {
527 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
527 BuildMI(*BB, BB->getFirstTerminator(),
528 TM.getInstrInfo()->get(X86::FP_REG_KILL));
528529 ++NumFPKill;
529530 }
530531 }
534535 /// the main function.
535536 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
536537 MachineFrameInfo *MFI) {
538 const TargetInstrInfo *TII = TM.getInstrInfo();
537539 if (Subtarget->isTargetCygwin())
538 BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
540 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
539541
540542 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
541543 int CWFrameIdx = MFI->CreateStackObject(2, 2);
542 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
544 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
543545
544546 // Set the high part to be 64-bit precision.
545 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
547 addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)),
546548 CWFrameIdx, 1).addImm(2);
547549
548550 // Reload the modified control word now.
549 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
551 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
550552 }
551553
552554 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
942944 MachineBasicBlock &FirstMBB = BB->getParent()->front();
943945 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
944946 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
945 // FIXME: when we get to LP64, we will need to create the appropriate
946 // type of register here.
947947 GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
948 BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
949 BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
948 const TargetInstrInfo *TII = TM.getInstrInfo();
949 BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
950 BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg);
950951 }
951952 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
952953 }
50355035 MachineBasicBlock *
50365036 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
50375037 MachineBasicBlock *BB) {
5038 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
50385039 switch (MI->getOpcode()) {
50395040 default: assert(false && "Unexpected instr type to insert");
50405041 case X86::CMOV_FR32:
50615062 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
50625063 unsigned Opc =
50635064 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5064 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
5065 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
50655066 MachineFunction *F = BB->getParent();
50665067 F->getBasicBlockList().insert(It, copy0MBB);
50675068 F->getBasicBlockList().insert(It, sinkMBB);
50895090 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
50905091 // ...
50915092 BB = sinkMBB;
5092 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
5093 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
50935094 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
50945095 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
50955096
51045105 // mode when truncating to an integer value.
51055106 MachineFunction *F = BB->getParent();
51065107 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5107 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
5108 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
51085109
51095110 // Load the old value of the high byte of the control word...
51105111 unsigned OldCW =
51115112 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
5112 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
5113 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
51135114
51145115 // Set the high part to be round to zero...
5115 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
5116 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5117 .addImm(0xC7F);
51165118
51175119 // Reload the modified control word now...
5118 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
5120 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
51195121
51205122 // Restore the memory image of control word to original value
5121 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
5123 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5124 .addReg(OldCW);
51225125
51235126 // Get the X86 opcode to use.
51245127 unsigned Opc;
51505153 } else {
51515154 AM.Disp = Op.getImm();
51525155 }
5153 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
5156 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5157 .addReg(MI->getOperand(4).getReg());
51545158
51555159 // Reload the original control word now.
5156 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
5160 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
51575161
51585162 delete MI; // The pseudo instruction is gone now.
51595163 return BB;
138138 unsigned C = MI->getOperand(2).getReg();
139139 unsigned M = MI->getOperand(3).getImmedValue();
140140 if (!Subtarget->hasSSE2() || B != C) return 0;
141 NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
141 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
142142 NewMI->copyKillDeadInfo(MI);
143143 return NewMI;
144144 }
157157 case X86::INC32r:
158158 case X86::INC64_32r:
159159 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
160 NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
160 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
161161 break;
162162 case X86::INC16r:
163163 case X86::INC64_16r:
164164 if (DisableLEA16) return 0;
165165 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
166 NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
166 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
167167 break;
168168 case X86::DEC32r:
169169 case X86::DEC64_32r:
170170 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
171 NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
171 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
172172 break;
173173 case X86::DEC16r:
174174 case X86::DEC64_16r:
175175 if (DisableLEA16) return 0;
176176 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
177 NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
177 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
178178 break;
179179 case X86::ADD32rr:
180180 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
181 NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
181 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
182182 MI->getOperand(2).getReg());
183183 break;
184184 case X86::ADD16rr:
185185 if (DisableLEA16) return 0;
186186 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
187 NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
187 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
188188 MI->getOperand(2).getReg());
189189 break;
190190 case X86::ADD32ri:
191191 case X86::ADD32ri8:
192192 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
193193 if (MI->getOperand(2).isImmediate())
194 NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
194 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
195195 MI->getOperand(2).getImmedValue());
196196 break;
197197 case X86::ADD16ri:
199199 if (DisableLEA16) return 0;
200200 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
201201 if (MI->getOperand(2).isImmediate())
202 NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
202 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
203203 MI->getOperand(2).getImmedValue());
204204 break;
205205 case X86::SHL16ri:
213213 AM.Scale = 1 << ShAmt;
214214 AM.IndexReg = Src;
215215 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
216 NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
216 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
217217 }
218218 break;
219219 }
248248 unsigned C = MI->getOperand(2).getReg();
249249 bool BisKill = MI->getOperand(1).isKill();
250250 bool CisKill = MI->getOperand(2).isKill();
251 return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill)
251 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
252252 .addReg(B, false, false, BisKill).addImm(Size-Amt);
253253 }
254254 default:
415415 if (FBB == 0) { // One way branch.
416416 if (Cond.empty()) {
417417 // Unconditional branch?
418 BuildMI(&MBB, X86::JMP, 1).addMBB(TBB);
418 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
419419 } else {
420420 // Conditional branch.
421421 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
422 BuildMI(&MBB, Opc, 1).addMBB(TBB);
422 BuildMI(&MBB, get(Opc)).addMBB(TBB);
423423 }
424424 return;
425425 }
426426
427427 // Two-way Conditional branch.
428428 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
429 BuildMI(&MBB, Opc, 1).addMBB(TBB);
430 BuildMI(&MBB, X86::JMP, 1).addMBB(FBB);
429 BuildMI(&MBB, get(Opc)).addMBB(TBB);
430 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
431431 }
432432
433433 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
9292 assert(0 && "Unknown regclass");
9393 abort();
9494 }
95 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
95 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
9696 }
9797
9898 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
124124 assert(0 && "Unknown regclass");
125125 abort();
126126 }
127 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
127 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
128128 }
129129
130130 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
156156 assert(0 && "Unknown regclass");
157157 abort();
158158 }
159 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
159 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
160160 }
161161
162162 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
164164 const TargetInstrInfo &TII) {
165165 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
166166 // Create the base instruction with the memory operand as the first part.
167 MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps),
167 MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
168168 FrameIndex);
169169
170170 // Loop over the rest of the ri operands, converting them over.
187187 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
188188 unsigned FrameIndex, MachineInstr *MI,
189189 const TargetInstrInfo &TII) {
190 MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3);
190 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
191191
192192 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
193193 MachineOperand &MO = MI->getOperand(i);
211211 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
212212 unsigned Opcode, unsigned FrameIndex,
213213 MachineInstr *MI) {
214 return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0);
214 return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
215215 }
216216
217217
907907
908908 MachineInstr *New = 0;
909909 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
910 New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
910 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
911911 .addReg(StackPtr).addImm(Amount);
912912 } else {
913913 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
918918 unsigned Opc = (Amount < 128) ?
919919 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
920920 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
921 New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount);
921 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
922922 }
923923 }
924924
934934 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
935935 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
936936 MachineInstr *New =
937 BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
937 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
938938 MBB.insert(I, New);
939939 }
940940 }
10111011 // more than 4k bytes in one go. Touching the stack at 4K increments is
10121012 // necessary to ensure that the guard pages used by the OS virtual memory
10131013 // manager are allocated in correct sequence.
1014 MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
1014 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
10151015 MBB.insert(MBBI, MI);
1016 MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1016 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
10171017 MBB.insert(MBBI, MI);
10181018 } else {
10191019 unsigned Opc = (NumBytes < 128) ?
10201020 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
10211021 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1022 MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
1022 MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
10231023 MBB.insert(MBBI, MI);
10241024 }
10251025 }
10331033
10341034 // Save EBP into the appropriate stack slot...
10351035 // mov [ESP-], EBP
1036 MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
1036 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
10371037 StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
10381038 MBB.insert(MBBI, MI);
10391039
10401040 // Update EBP with the new base value...
10411041 if (NumBytes == SlotSize) // mov EBP, ESP
1042 MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
1042 MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
10431043 addReg(StackPtr);
10441044 else // lea EBP, [ESP+StackSize]
1045 MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r,
1046 5, FramePtr), StackPtr, NumBytes-SlotSize);
1045 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1046 FramePtr), StackPtr, NumBytes-SlotSize);
10471047
10481048 MBB.insert(MBBI, MI);
10491049 }
10511051 // If it's main() on Cygwin\Mingw32 we should align stack as well
10521052 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
10531053 Subtarget->isTargetCygwin()) {
1054 MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
1054 MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align);
10551055 MBB.insert(MBBI, MI);
10561056
10571057 // Probe the stack
1058 MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align);
1058 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
10591059 MBB.insert(MBBI, MI);
1060 MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1060 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
10611061 MBB.insert(MBBI, MI);
10621062 }
10631063 }
10791079
10801080 if (hasFP(MF)) {
10811081 // mov ESP, EBP
1082 BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
1082 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
10831083 addReg(FramePtr);
10841084
10851085 // pop EBP
1086 BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr);
1086 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
10871087 } else {
10881088 // Get the number of bytes allocated from the FrameInfo...
10891089 unsigned NumBytes = MFI->getStackSize();
11111111 unsigned Opc = (NumBytes < 128) ?
11121112 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
11131113 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1114 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes);
1114 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
11151115 } else if ((int)NumBytes < 0) {
11161116 unsigned Opc = (-NumBytes < 128) ?
11171117 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
11181118 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1119 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes);
1119 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes);
11201120 }
11211121 }
11221122 }