llvm.org GIT mirror llvm / c0eb209
MC: Remove unused entities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283691 91177308-0d34-0410-b5e6-96231b3b80d8 Peter Collingbourne 3 years ago
24 changed file(s) with 19 addition(s) and 246 deletion(s). Raw diff Collapse all Expand all
293293 /// \brief Return true if this instruction is a comparison.
294294 bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
295295
296 /// \brief Return true if this instruction is a move immediate
297 /// (including conditional moves) instruction.
298 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
299
300 /// \brief Return true if this instruction is a bitcast instruction.
301 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
302
303296 /// \brief Return true if this is a select instruction.
304297 bool isSelect() const { return Flags & (1ULL << MCID::Select); }
305
306 /// \brief Return true if this instruction cannot be safely
307 /// duplicated. For example, if the instruction has a unique labels attached
308 /// to it, duplicating it would cause multiple definition errors.
309 bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
310298
311299 /// \brief Returns true if the specified instruction has a delay slot which
312300 /// must be filled by the code generator.
313301 bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
314
315 /// \brief Return true for instructions that can be folded as memory operands
316 /// in other instructions. The most common use for this is instructions that
317 /// are simple loads from memory that don't modify the loaded value in any
318 /// way, but it can also be used for instructions that can be expressed as
319 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
320 /// folded when it is beneficial. This should only be set on instructions
321 /// that return a value in their only virtual register definition.
322 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
323
324 /// \brief Return true if this instruction behaves
325 /// the same way as the generic REG_SEQUENCE instructions.
326 /// E.g., on ARM,
327 /// dX VMOVDRR rY, rZ
328 /// is equivalent to
329 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
330 ///
331 /// Note that for the optimizers to be able to take advantage of
332 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
333 /// override accordingly.
334 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
335
336 /// \brief Return true if this instruction behaves
337 /// the same way as the generic EXTRACT_SUBREG instructions.
338 /// E.g., on ARM,
339 /// rX, rY VMOVRRD dZ
340 /// is equivalent to two EXTRACT_SUBREG:
341 /// rX = EXTRACT_SUBREG dZ, ssub_0
342 /// rY = EXTRACT_SUBREG dZ, ssub_1
343 ///
344 /// Note that for the optimizers to be able to take advantage of
345 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
346 /// override accordingly.
347 bool isExtractSubregLike() const {
348 return Flags & (1ULL << MCID::ExtractSubreg);
349 }
350
351 /// \brief Return true if this instruction behaves
352 /// the same way as the generic INSERT_SUBREG instructions.
353 /// E.g., on ARM,
354 /// dX = VSETLNi32 dY, rZ, Imm
355 /// is equivalent to a INSERT_SUBREG:
356 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
357 ///
358 /// Note that for the optimizers to be able to take advantage of
359 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
360 /// override accordingly.
361 bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
362
363
364 /// \brief Return true if this instruction is convergent.
365 ///
366 /// Convergent instructions may not be made control-dependent on any
367 /// additional values.
368 bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
369302
370303 //===--------------------------------------------------------------------===//
371304 // Side Effect Analysis
381314 /// instructions, they may store a modified value based on their operands, or
382315 /// may not actually modify anything, for example.
383316 bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
384
385 /// \brief Return true if this instruction has side
386 /// effects that are not modeled by other flags. This does not return true
387 /// for instructions whose effects are captured by:
388 ///
389 /// 1. Their operand list and implicit definition/use list. Register use/def
390 /// info is explicit for instructions.
391 /// 2. Memory accesses. Use mayLoad/mayStore.
392 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
393 ///
394 /// Examples of side effects would be modifying 'invisible' machine state like
395 /// a control register, flushing a cache, modifying a register invisible to
396 /// LLVM, etc.
397 bool hasUnmodeledSideEffects() const {
398 return Flags & (1ULL << MCID::UnmodeledSideEffects);
399 }
400317
401318 //===--------------------------------------------------------------------===//
402319 // Flags that indicate whether an instruction can be modified by a method.
414331 /// commute them.
415332 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
416333
417 /// \brief Return true if this is a 2-address instruction which can be changed
418 /// into a 3-address instruction if needed. Doing this transformation can be
419 /// profitable in the register allocator, because it means that the
420 /// instruction can use a 2-address form if possible, but degrade into a less
421 /// efficient form if the source and dest register cannot be assigned to the
422 /// same register. For example, this allows the x86 backend to turn a "shl
423 /// reg, 3" instruction into an LEA instruction, which is the same speed as
424 /// the shift but has bigger code size.
425 ///
426 /// If this returns true, then the target must implement the
427 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
428 /// is allowed to fail if the transformation isn't valid for this specific
429 /// instruction (e.g. shl reg, 4 on x86).
430 ///
431 bool isConvertibleTo3Addr() const {
432 return Flags & (1ULL << MCID::ConvertibleTo3Addr);
433 }
434
435 /// \brief Return true if this instruction requires custom insertion support
436 /// when the DAG scheduler is inserting it into a machine basic block. If
437 /// this is true for the instruction, it basically means that it is a pseudo
438 /// instruction used at SelectionDAG time that is expanded out into magic code
439 /// by the target when MachineInstrs are formed.
440 ///
441 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
442 /// is used to insert this into the MachineBasicBlock.
443 bool usesCustomInsertionHook() const {
444 return Flags & (1ULL << MCID::UsesCustomInserter);
445 }
446
447334 /// \brief Return true if this instruction requires *adjustment* after
448335 /// instruction selection by calling a target hook. For example, this can be
449336 /// used to fill in ARM 's' optional operand depending on whether the
458345 /// the instruction is really rematable.
459346 bool isRematerializable() const {
460347 return Flags & (1ULL << MCID::Rematerializable);
461 }
462
463 /// \brief Returns true if this instruction has the same cost (or less) than a
464 /// move instruction. This is useful during certain types of optimizations
465 /// (e.g., remat during two-address conversion or machine licm) where we would
466 /// like to remat or hoist the instruction, but not if it costs more than
467 /// moving the instruction into the appropriate register. Note, we are not
468 /// marking copies from and to the same register class with this flag.
469 ///
470 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
471 /// for different subtargets.
472 bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
473
474 /// \brief Returns true if this instruction source operands have special
475 /// register allocation requirements that are not captured by the operand
476 /// register classes. e.g. ARM::STRD's two source registers must be an even /
477 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
478 /// allocation passes should not attempt to change allocations for sources of
479 /// instructions with this flag.
480 bool hasExtraSrcRegAllocReq() const {
481 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
482 }
483
484 /// \brief Returns true if this instruction def operands have special register
485 /// allocation requirements that are not captured by the operand register
486 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
487 /// ARM::LDM registers have to be in ascending order. Post-register
488 /// allocation passes should not attempt to change allocations for definitions
489 /// of instructions with this flag.
490 bool hasExtraDefRegAllocReq() const {
491 return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
492348 }
493349
494350 /// \brief Return a list of registers that are potentially read by any
534390 }
535391
536392 /// \brief Return true if this instruction implicitly
537 /// uses the specified physical register.
538 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
539 if (const MCPhysReg *ImpUses = ImplicitUses)
540 for (; *ImpUses; ++ImpUses)
541 if (*ImpUses == Reg)
542 return true;
543 return false;
544 }
545
546 /// \brief Return true if this instruction implicitly
547393 /// defines the specified physical register.
548394 bool hasImplicitDefOfPhysReg(unsigned Reg,
549395 const MCRegisterInfo *MRI = nullptr) const;
2626 const unsigned Is64Bit : 1;
2727 const uint32_t CPUType;
2828 const uint32_t CPUSubtype;
29 unsigned LocalDifference_RIT;
3029
3130 protected:
3231 MCMachObjectTargetWriter(bool Is64Bit_, uint32_t CPUType_,
3332 uint32_t CPUSubtype_);
3433
35 void setLocalDifferenceRelocationType(unsigned Type) {
36 LocalDifference_RIT = Type;
37 }
38
3934 public:
4035 virtual ~MCMachObjectTargetWriter();
4136
5247 bool is64Bit() const { return Is64Bit; }
5348 uint32_t getCPUType() const { return CPUType; }
5449 uint32_t getCPUSubtype() const { return CPUSubtype; }
55 unsigned getLocalDifferenceRelocationType() const {
56 return LocalDifference_RIT;
57 }
5850
5951 /// @}
6052
6363
6464 /// getStartLoc - Get the location of the first token of this operand.
6565 virtual SMLoc getStartLoc() const = 0;
66 /// getEndLoc - Get the location of the last token of this operand.
67 virtual SMLoc getEndLoc() const = 0;
6866
6967 /// needAddressOf - Do we need to emit code to get the address of the
7068 /// variable/label? Only valid when parsing MS-style inline assembly.
7169 virtual bool needAddressOf() const { return false; }
72
73 /// isOffsetOf - Do we need to emit code to get the offset of the variable,
74 /// rather then the value of the variable? Only valid when parsing MS-style
75 /// inline assembly.
76 virtual bool isOffsetOf() const { return false; }
77
78 /// getOffsetOfLoc - Get the location of the offset operator.
79 virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
8070
8171 /// print - Print a debug representation of the operand to the given stream.
8272 virtual void print(raw_ostream &OS) const = 0;
208208 return Match_Success;
209209 }
210210
211 virtual void convertToMapAndConstraints(unsigned Kind,
212 const OperandVector &Operands) = 0;
213
214211 // Return whether this parser uses assignment statements with equals tokens
215212 virtual bool equalIsAsmAssignment() { return true; };
216213 // Return whether this start of statement identifier is a label
198198 return CurrentWinFrameInfo;
199199 }
200200
201 virtual void EmitWindowsUnwindTables();
202
203201 virtual void EmitRawTextImpl(StringRef String);
204202
205203 public:
276274 /// \brief Add explicit comment T. T is required to be a valid
277275 /// comment in the output and does not need to be escaped.
278276 virtual void addExplicitComment(const Twine &T);
279 /// \brief Emit added explicit comments.
280 virtual void emitExplicitComments();
281277
282278 /// AddBlankLine - Emit a blank line to a .s file to pretty it up.
283279 virtual void AddBlankLine() {}
5050 }
5151 };
5252
53 class UnwindEmitter : public WinEH::UnwindEmitter {
53 class UnwindEmitter {
5454 public:
55 void Emit(MCStreamer &Streamer) const override;
56 void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const override;
55 void Emit(MCStreamer &Streamer) const;
56 void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const;
5757 };
5858 }
5959 } // end namespace llvm
5151 : Begin(BeginFuncEHLabel), Function(Function),
5252 ChainedParent(ChainedParent) {}
5353 };
54
55 class UnwindEmitter {
56 public:
57 virtual ~UnwindEmitter();
58
59 /// This emits the unwind info sections (.pdata and .xdata in PE/COFF).
60 virtual void Emit(MCStreamer &Streamer) const = 0;
61 virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI) const = 0;
62 };
6354 }
6455 }
6556
4040 MCTargetOptions.cpp
4141 MCValue.cpp
4242 MCWin64EH.cpp
43 MCWinEH.cpp
4443 MachObjectWriter.cpp
4544 StringTableBuilder.cpp
4645 SubtargetFeature.cpp
116116 void emitRawComment(const Twine &T, bool TabPrefix = true) override;
117117
118118 void addExplicitComment(const Twine &T) override;
119 void emitExplicitComments() override;
119 void emitExplicitComments();
120120
121121 /// AddBlankLine - Emit a blank line to a .s file to pretty it up.
122122 void AddBlankLine() override {
7171 void MCStreamer::emitRawComment(const Twine &T, bool TabPrefix) {}
7272
7373 void MCStreamer::addExplicitComment(const Twine &T) {}
74 void MCStreamer::emitExplicitComments() {}
7574
7675 void MCStreamer::generateCompactUnwindEncodings(MCAsmBackend *MAB) {
7776 for (auto &FI : DwarfFrameInfos)
710709 void MCStreamer::EmitRawText(const Twine &T) {
711710 SmallString<128> Str;
712711 EmitRawTextImpl(T.toStringRef(Str));
713 }
714
715 void MCStreamer::EmitWindowsUnwindTables() {
716712 }
717713
718714 void MCStreamer::Finish() {
+0
-26
lib/MC/MCWinEH.cpp less more
None //===- lib/MC/MCWinEH.cpp - Windows EH implementation ---------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/ADT/StringRef.h"
10 #include "llvm/MC/MCContext.h"
11 #include "llvm/MC/MCObjectFileInfo.h"
12 #include "llvm/MC/MCSectionCOFF.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCSymbol.h"
15 #include "llvm/MC/MCWinEH.h"
16 #include "llvm/Support/COFF.h"
17
18 namespace llvm {
19 namespace WinEH {
20
21 UnwindEmitter::~UnwindEmitter() {}
22
23 }
24 }
25
325325 /// getStartLoc - Get the location of the first token of this operand.
326326 SMLoc getStartLoc() const override { return StartLoc; }
327327 /// getEndLoc - Get the location of the last token of this operand.
328 SMLoc getEndLoc() const override { return EndLoc; }
328 SMLoc getEndLoc() const { return EndLoc; }
329329
330330 StringRef getToken() const {
331331 assert(Kind == k_Token && "Invalid access!");
378378 return StartLoc;
379379 }
380380
381 SMLoc getEndLoc() const override {
381 SMLoc getEndLoc() const {
382382 return EndLoc;
383383 }
384384
751751 /// getStartLoc - Get the location of the first token of this operand.
752752 SMLoc getStartLoc() const override { return StartLoc; }
753753 /// getEndLoc - Get the location of the last token of this operand.
754 SMLoc getEndLoc() const override { return EndLoc; }
754 SMLoc getEndLoc() const { return EndLoc; }
755755 /// getLocRange - Get the range between the first and last token of this
756756 /// operand.
757757 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
221221 SMLoc getStartLoc() const { return StartLoc; }
222222
223223 /// getEndLoc - Get the location of the last token of this operand.
224 SMLoc getEndLoc() const { return EndLoc; }
224 SMLoc getEndLoc() { return EndLoc; }
225225
226226 unsigned getReg() const {
227227 assert(Kind == Register && "Invalid access!");
133133 SMLoc getStartLoc() const override { return StartLoc; }
134134
135135 // getEndLoc - Gets location of the last token of this operand
136 SMLoc getEndLoc() const override { return EndLoc; }
136 SMLoc getEndLoc() const { return EndLoc; }
137137
138138 unsigned getReg() const override {
139139 assert(isReg() && "Invalid type access!");
14731473 /// getStartLoc - Get the location of the first token of this operand.
14741474 SMLoc getStartLoc() const override { return StartLoc; }
14751475 /// getEndLoc - Get the location of the last token of this operand.
1476 SMLoc getEndLoc() const override { return EndLoc; }
1476 SMLoc getEndLoc() const { return EndLoc; }
14771477
14781478 virtual ~MipsOperand() {
14791479 switch (Kind) {
393393 SMLoc getStartLoc() const override { return StartLoc; }
394394
395395 /// getEndLoc - Get the location of the last token of this operand.
396 SMLoc getEndLoc() const override { return EndLoc; }
396 SMLoc getEndLoc() const { return EndLoc; }
397397
398398 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
399399 bool isPPC64() const { return IsPPC64; }
280280 return StartLoc;
281281 }
282282 /// getEndLoc - Get the location of the last token of this operand.
283 SMLoc getEndLoc() const override {
283 SMLoc getEndLoc() const {
284284 return EndLoc;
285285 }
286286
260260
261261 // Override MCParsedAsmOperand.
262262 SMLoc getStartLoc() const override { return StartLoc; }
263 SMLoc getEndLoc() const override { return EndLoc; }
263 SMLoc getEndLoc() const { return EndLoc; }
264264 void print(raw_ostream &OS) const override;
265265
266266 // Used by the TableGen code to add particular types of operand
16951695 unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
16961696
16971697 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1698 OffsetOfLoc, Identifier, Info.OpDecl);
1698 Identifier, Info.OpDecl);
16991699 }
17001700
17011701 enum IntelOperatorKind {
3030 } Kind;
3131
3232 SMLoc StartLoc, EndLoc;
33 SMLoc OffsetOfLoc;
3433 StringRef SymName;
3534 void *OpDecl;
3635 bool AddressOf;
7473 /// getStartLoc - Get the location of the first token of this operand.
7574 SMLoc getStartLoc() const override { return StartLoc; }
7675 /// getEndLoc - Get the location of the last token of this operand.
77 SMLoc getEndLoc() const override { return EndLoc; }
76 SMLoc getEndLoc() const { return EndLoc; }
7877 /// getLocRange - Get the range between the first and last token of this
7978 /// operand.
8079 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
81 /// getOffsetOfLoc - Get the location of the offset operator.
82 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
8380
8481 void print(raw_ostream &OS) const override {}
8582
194191 const MCConstantExpr *CE = dyn_cast(getImm());
195192 if (!CE) return false;
196193 return isImmUnsignedi8Value(CE->getValue());
197 }
198
199 bool isOffsetOf() const override {
200 return OffsetOfLoc.getPointer();
201194 }
202195
203196 bool needAddressOf() const override {
473466
474467 static std::unique_ptr
475468 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
476 bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
477 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
469 bool AddressOf = false, StringRef SymName = StringRef(),
470 void *OpDecl = nullptr) {
478471 auto Res = llvm::make_unique(Register, StartLoc, EndLoc);
479472 Res->Reg.RegNo = RegNo;
480473 Res->AddressOf = AddressOf;
481 Res->OffsetOfLoc = OffsetOfLoc;
482474 Res->SymName = SymName;
483475 Res->OpDecl = OpDecl;
484476 return Res;
2121 : MCWinCOFFStreamer(C, AB, *CE, OS) {}
2222
2323 void EmitWinEHHandlerData() override;
24 void EmitWindowsUnwindTables() override;
24 void EmitWindowsUnwindTables();
2525 void FinishImpl() override;
2626 };
2727
28922892 << " const OperandVector &Operands);\n";
28932893 }
28942894 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2895 OS << " const OperandVector &Operands) override;\n";
2895 OS << " const OperandVector &Operands);\n";
28962896 if (HasMnemonicFirst)
28972897 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
28982898 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"