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misched: Add computeInstrLatency to TargetSchedModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 7 years ago
2 changed file(s) with 32 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
7373 const MachineInstr *UseMI, unsigned UseOperIdx,
7474 bool FindMin) const;
7575
76 /// \brief Compute the instruction latency based on the available machine
77 /// model.
78 ///
79 /// Compute and return the expected latency of this instruction independent of
80 /// a particular use. computeOperandLatency is the prefered API, but this is
81 /// occasionally useful to help estimate instruction cost.
82 unsigned computeInstrLatency(const MachineInstr *MI) const;
83
7684 /// \brief Identify the processor corresponding to the current subtarget.
7785 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
7886
145145 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
146146
147147 // Expected latency is the max of the stage latency and itinerary props.
148 // Rather than directly querying InstrItins stage latency, we call a TII
149 // hook to allow subtargets to specialize latency. This hook is only
150 // applicable to the InstrItins model. InstrSchedModel should model all
151 // special cases without TII hooks.
148152 if (!FindMin)
149153 InstrLatency = std::max(InstrLatency,
150154 TII->defaultDefLatency(&SchedModel, DefMI));
184188 #endif
185189 return 1;
186190 }
191
192 unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
193 if (hasInstrItineraries()) {
194 // For the itinerary model, fall back to the old subtarget hook.
195 return TII->getInstrLatency(&InstrItins, MI);
196 }
197 if (hasInstrSchedModel()) {
198 unsigned Latency = 0;
199 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
200 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
201 DefIdx != DefEnd; ++DefIdx) {
202 // Lookup the definition's write latency in SubtargetInfo.
203 const MCWriteLatencyEntry *WLEntry =
204 STI->getWriteLatencyEntry(SCDesc, DefIdx);
205 Latency = std::max(Latency, WLEntry->Cycles);
206 }
207 return Latency;
208 }
209 return TII->defaultDefLatency(&SchedModel, MI);
210 }