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[AArch64] [Assembler] option to disable negative immediate conversions Summary: Similar to the ARM target in https://reviews.llvm.org/rL298380, this patch adds identical infrastructure for disabling negative immediate conversions, and converts the existing aliases to the new infrastucture. Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker Reviewed By: samparker Subscribers: samparker, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D31243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298908 91177308-0d34-0410-b5e6-96231b3b80d8 Sanne Wouda 3 years ago
6 changed file(s) with 60 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
117117 def FeatureUseRSqrt : SubtargetFeature<
118118 "use-reciprocal-square-root", "UseRSqrt", "true",
119119 "Use the reciprocal square root approximation">;
120
121 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
122 "NegativeImmediates", "false",
123 "Convert immediates and instructions "
124 "to their negated or complemented "
125 "equivalent when the immediate does "
126 "not fit in the encoding.">;
127
120128 //===----------------------------------------------------------------------===//
121129 // Architectures.
122130 //
3737 let Pattern = [];
3838 let Constraints = cstr;
3939 }
40
41 class InstSubst
42 : InstAlias, Requires<[UseNegativeImmediates]>;
4043
4144 // Pseudo instructions (don't have encoding information)
4245 class Pseudo pattern, string cstr = "">
17971800 }
17981801
17991802 // add Rd, Rb, -imm -> sub Rd, Rn, imm
1800 def : InstAlias
1803 def : InstSubst
18011804 (!cast(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
18021805 addsub_shifted_imm32_neg:$imm), 0>;
1803 def : InstAlias
1806 def : InstSubst
18041807 (!cast(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
18051808 addsub_shifted_imm64_neg:$imm), 0>;
18061809
18721875 } // Defs = [NZCV]
18731876
18741877 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
1875 def : InstAlias
1878 def : InstSubst
18761879 (!cast(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
18771880 addsub_shifted_imm32_neg:$imm), 0>;
1878 def : InstAlias
1881 def : InstSubst
18791882 (!cast(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
18801883 addsub_shifted_imm64_neg:$imm), 0>;
18811884
18961899 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
18971900
18981901 // Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
1899 def : InstAlias(NAME#"Wri")
1902 def : InstSubst(NAME#"Wri")
19001903 WZR, GPR32sp:$src, addsub_shifted_imm32_neg:$imm), 0>;
1901 def : InstAlias(NAME#"Xri")
1904 def : InstSubst(NAME#"Xri")
19021905 XZR, GPR64sp:$src, addsub_shifted_imm64_neg:$imm), 0>;
19031906
19041907 // Compare shorthands
21132116 let Inst{31} = 1;
21142117 }
21152118
2116 def : InstAlias
2119 def : InstSubst
21172120 (!cast(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
21182121 logical_imm32_not:$imm), 0>;
2119 def : InstAlias
2122 def : InstSubst
21202123 (!cast(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
21212124 logical_imm64_not:$imm), 0>;
21222125 }
21352138 }
21362139 } // end Defs = [NZCV]
21372140
2138 def : InstAlias
2141 def : InstSubst
21392142 (!cast(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
21402143 logical_imm32_not:$imm), 0>;
2141 def : InstAlias
2144 def : InstSubst
21422145 (!cast(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
21432146 logical_imm64_not:$imm), 0>;
21442147 }
4141 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
4242 def UseAlternateSExtLoadCVTF32
4343 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
44
45 def UseNegativeImmediates
46 : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",
47 "NegativeImmediates">;
48
4449
4550 //===----------------------------------------------------------------------===//
4651 // AArch64-specific DAG Nodes.
7777
7878 // StrictAlign - Disallow unaligned memory accesses.
7979 bool StrictAlign = false;
80
81 // NegativeImmediates - transform instructions with negative immediates
82 bool NegativeImmediates = true;
83
8084 bool UseAA = false;
8185 bool PredictableSelectIsExpensive = false;
8286 bool BalanceFPOps = false;
0 // RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s
1 // RUN: not llvm-mc -mattr=+no-neg-immediates -triple=aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEG-IMM
12
23 // CHECK: sub w0, w2, #2, lsl #12
34 // CHECK: sub w0, w2, #2, lsl #12
5 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
46 sub w0, w2, #2, lsl 12
57 add w0, w2, #-2, lsl 12
68 // CHECK: sub x1, x3, #2, lsl #12
79 // CHECK: sub x1, x3, #2, lsl #12
10 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
811 sub x1, x3, #2, lsl 12
912 add x1, x3, #-2, lsl 12
1013 // CHECK: sub x1, x3, #4
1114 // CHECK: sub x1, x3, #4
15 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
1216 sub x1, x3, #4
1317 add x1, x3, #-4
1418 // CHECK: sub x1, x3, #4095
1519 // CHECK: sub x1, x3, #4095
20 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
1621 sub x1, x3, #4095, lsl 0
1722 add x1, x3, #-4095, lsl 0
1823 // CHECK: sub x3, x4, #0
2025
2126 // CHECK: add w0, w2, #2, lsl #12
2227 // CHECK: add w0, w2, #2, lsl #12
28 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
2329 add w0, w2, #2, lsl 12
2430 sub w0, w2, #-2, lsl 12
2531 // CHECK: add x1, x3, #2, lsl #12
2632 // CHECK: add x1, x3, #2, lsl #12
33 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
2734 add x1, x3, #2, lsl 12
2835 sub x1, x3, #-2, lsl 12
2936 // CHECK: add x1, x3, #4
3037 // CHECK: add x1, x3, #4
38 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
3139 add x1, x3, #4
3240 sub x1, x3, #-4
3341 // CHECK: add x1, x3, #4095
3442 // CHECK: add x1, x3, #4095
43 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
3544 add x1, x3, #4095, lsl 0
3645 sub x1, x3, #-4095, lsl 0
3746 // CHECK: add x2, x5, #0
3948
4049 // CHECK: subs w0, w2, #2, lsl #12
4150 // CHECK: subs w0, w2, #2, lsl #12
51 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
4252 subs w0, w2, #2, lsl 12
4353 adds w0, w2, #-2, lsl 12
4454 // CHECK: subs x1, x3, #2, lsl #12
4555 // CHECK: subs x1, x3, #2, lsl #12
56 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
4657 subs x1, x3, #2, lsl 12
4758 adds x1, x3, #-2, lsl 12
4859 // CHECK: subs x1, x3, #4
4960 // CHECK: subs x1, x3, #4
61 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
5062 subs x1, x3, #4
5163 adds x1, x3, #-4
5264 // CHECK: subs x1, x3, #4095
5365 // CHECK: subs x1, x3, #4095
66 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
5467 subs x1, x3, #4095, lsl 0
5568 adds x1, x3, #-4095, lsl 0
5669 // CHECK: subs x3, x4, #0
5871
5972 // CHECK: adds w0, w2, #2, lsl #12
6073 // CHECK: adds w0, w2, #2, lsl #12
74 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
6175 adds w0, w2, #2, lsl 12
6276 subs w0, w2, #-2, lsl 12
6377 // CHECK: adds x1, x3, #2, lsl #12
6478 // CHECK: adds x1, x3, #2, lsl #12
79 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
6580 adds x1, x3, #2, lsl 12
6681 subs x1, x3, #-2, lsl 12
6782 // CHECK: adds x1, x3, #4
6883 // CHECK: adds x1, x3, #4
84 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
6985 adds x1, x3, #4
7086 subs x1, x3, #-4
7187 // CHECK: adds x1, x3, #4095
7288 // CHECK: adds x1, x3, #4095
89 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
7390 adds x1, x3, #4095, lsl 0
7491 subs x1, x3, #-4095, lsl 0
7592 // CHECK: adds x2, x5, #0
7794
7895 // CHECK: {{adds xzr,|cmn}} x5, #5
7996 // CHECK: {{adds xzr,|cmn}} x5, #5
97 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
8098 cmn x5, #5
8199 cmp x5, #-5
82100 // CHECK: {{subs xzr,|cmp}} x6, #4095
83101 // CHECK: {{subs xzr,|cmp}} x6, #4095
102 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
84103 cmp x6, #4095
85104 cmn x6, #-4095
86105 // CHECK: {{adds wzr,|cmn}} w7, #5
87106 // CHECK: {{adds wzr,|cmn}} w7, #5
107 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
88108 cmn w7, #5
89109 cmp w7, #-5
90110 // CHECK: {{subs wzr,|cmp}} w8, #4095
91111 // CHECK: {{subs wzr,|cmp}} w8, #4095
112 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
92113 cmp w8, #4095
93114 cmn w8, #-4095
0 // RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s
1 // RUN: not llvm-mc -mattr=+no-neg-immediates -triple=aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEG-IMM
12
23 // CHECK: and x0, x1, #0xfffffffffffffffd
34 // CHECK: and x0, x1, #0xfffffffffffffffd
5 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
46 and x0, x1, #~2
57 bic x0, x1, #2
68
79 // CHECK: and w0, w1, #0xfffffffd
810 // CHECK: and w0, w1, #0xfffffffd
11 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
912 and w0, w1, #~2
1013 bic w0, w1, #2
1114
1215 // CHECK: ands x0, x1, #0xfffffffffffffffd
1316 // CHECK: ands x0, x1, #0xfffffffffffffffd
17 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
1418 ands x0, x1, #~2
1519 bics x0, x1, #2
1620
1721 // CHECK: ands w0, w1, #0xfffffffd
1822 // CHECK: ands w0, w1, #0xfffffffd
23 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
1924 ands w0, w1, #~2
2025 bics w0, w1, #2
2126
2227 // CHECK: orr x0, x1, #0xfffffffffffffffd
2328 // CHECK: orr x0, x1, #0xfffffffffffffffd
29 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
2430 orr x0, x1, #~2
2531 orn x0, x1, #2
2632
2733 // CHECK: orr w2, w1, #0xfffffffc
2834 // CHECK: orr w2, w1, #0xfffffffc
35 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
2936 orr w2, w1, #~3
3037 orn w2, w1, #3
3138
3239 // CHECK: eor x0, x1, #0xfffffffffffffffd
3340 // CHECK: eor x0, x1, #0xfffffffffffffffd
41 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
3442 eor x0, x1, #~2
3543 eon x0, x1, #2
3644
3745 // CHECK: eor w2, w1, #0xfffffffc
3846 // CHECK: eor w2, w1, #0xfffffffc
47 // CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
3948 eor w2, w1, #~3
4049 eon w2, w1, #3