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ARM implement TargetInstrInfo::getNoopForMachoTarget() Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
9 changed file(s) with 66 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
30023002 // This will go before any implicit ops.
30033003 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
30043004 }
3005
3006 bool ARMBaseInstrInfo::hasNOP() const {
3007 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
3008 }
3434 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
3535
3636 public:
37 // Return whether the target has an explicit NOP encoding.
38 bool hasNOP() const;
39
3740 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3841 // if there is not such an opcode.
3942 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2222 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCInst.h"
2324 using namespace llvm;
2425
2526 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
2627 : ARMBaseInstrInfo(STI), RI(*this, STI) {
28 }
29
30 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
32 if (hasNOP()) {
33 NopInst.setOpcode(ARM::NOP);
34 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
35 NopInst.addOperand(MCOperand::CreateReg(0));
36 } else {
37 NopInst.setOpcode(ARM::MOVr);
38 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
39 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
42 NopInst.addOperand(MCOperand::CreateReg(0));
43 }
2744 }
2845
2946 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
2727 public:
2828 explicit ARMInstrInfo(const ARMSubtarget &STI);
2929
30 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31 void getNoopForMachoTarget(MCInst &NopInst) const;
32
3033 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3134 // if there is not such an opcode.
3235 unsigned getUnindexedOpcode(unsigned Opc) const;
1818 #include "llvm/CodeGen/MachineRegisterInfo.h"
1919 #include "llvm/CodeGen/MachineMemOperand.h"
2020 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
21 #include "llvm/MC/MCInst.h"
2222
2323 using namespace llvm;
2424
2525 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
2626 : ARMBaseInstrInfo(STI), RI(*this, STI) {
27 }
28
29 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
30 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
31 NopInst.setOpcode(ARM::tMOVr);
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
34 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
35 NopInst.addOperand(MCOperand::CreateReg(0));
2736 }
2837
2938 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
2525 Thumb1RegisterInfo RI;
2626 public:
2727 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
28
29 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
30 void getNoopForMachoTarget(MCInst &NopInst) const;
2831
2932 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3033 // if there is not such an opcode.
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/CodeGen/MachineMemOperand.h"
2222 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/MCInst.h"
2324 #include "llvm/Support/CommandLine.h"
2425
2526 using namespace llvm;
3132
3233 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
3334 : ARMBaseInstrInfo(STI), RI(*this, STI) {
35 }
36
37 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
38 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39 NopInst.setOpcode(ARM::tNOP);
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
3442 }
3543
3644 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
2626 Thumb2RegisterInfo RI;
2727 public:
2828 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
29
30 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31 void getNoopForMachoTarget(MCInst &NopInst) const;
2932
3033 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3134 // if there is not such an opcode.
0 ; RUN: llc < %s -filetype=obj -mtriple=thumbv6-apple-darwin -o - | macho-dump -dump-section-data | FileCheck -prefix=T1
1 ; RUN: llc < %s -filetype=obj -mtriple=thumbv7-apple-darwin -o - | macho-dump -dump-section-data | FileCheck -prefix=T2
2 ; RUN: llc < %s -filetype=obj -mtriple=armv6-apple-darwin -o - | macho-dump -dump-section-data | FileCheck -prefix=ARM
3 ; RUN: llc < %s -filetype=obj -mtriple=armv7-apple-darwin -o - | macho-dump -dump-section-data | FileCheck -prefix=ARMV7
4
5 ; Empty functions need a NOP in them for MachO to prevent DWARF FDEs from
6 ; getting all mucked up. See lib/CodeGen/AsmPrinter/AsmPrinter.cpp for
7 ; details.
8 define internal fastcc void @empty_function() {
9 unreachable
10 }
11 ; CHECK-T1: ('_section_data', 'c046')
12 ; CHECK-T2: ('_section_data', '00bf')
13 ; CHECK-ARM: ('_section_data', '0000a0e1')
14 ; CHECK-ARMV7: ('_section_data', '00f020e3')