llvm.org GIT mirror llvm / c004792
Replace dregsingle operand modifier with explicit escaped curly brackets. For other VLDn and VSTn operations, we need to list the multiple registers explicitly anyway, so there's no point in special-casing this one usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 11 years ago
2 changed file(s) with 2 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
141141 // VLD1 : Vector Load (multiple single elements)
142142 class VLD1D
143143 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
144 !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
144 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
145145 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
146146 class VLD1Q
147147 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
163163 // VST1 : Vector Store (multiple single elements)
164164 class VST1D
165165 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
166 !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
166 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
167167 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
168168 class VST1Q
169169 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
347347 O << '{'
348348 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
349349 << '}';
350 } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
351 O << '{' << TRI->getAsmName(Reg) << '}';
352350 } else {
353351 O << TRI->getAsmName(Reg);
354352 }