llvm.org GIT mirror llvm / bfea590
[ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293578 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
11 changed file(s) with 241 addition(s) and 129 deletion(s). Raw diff Collapse all Expand all
1616 #include "MCTargetDesc/ARMBaseInfo.h"
1717 #include "llvm/ADT/DenseMap.h"
1818 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineInstr.h"
1921 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/CodeGen.h"
22 #include "llvm/CodeGen/MachineOperand.h"
2123 #include "llvm/Target/TargetInstrInfo.h"
24 #include
25 #include
2226
2327 #define GET_INSTRINFO_HEADER
2428 #include "ARMGenInstrInfo.inc"
2529
2630 namespace llvm {
27 class ARMSubtarget;
28 class ARMBaseRegisterInfo;
31
32 class ARMBaseRegisterInfo;
33 class ARMSubtarget;
2934
3035 class ARMBaseInstrInfo : public ARMGenInstrInfo {
3136 const ARMSubtarget &Subtarget;
107112
108113 // Return the non-pre/post incrementing version of 'Opc'. Return 0
109114 // if there is not such an opcode.
110 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
115 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
111116
112117 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
113118 MachineInstr &MI,
408413 static inline std::array predOps(ARMCC::CondCodes Pred,
409414 unsigned PredReg = 0) {
410415 return {{MachineOperand::CreateImm(static_cast(Pred)),
411 MachineOperand::CreateReg(PredReg, 0)}};
416 MachineOperand::CreateReg(PredReg, false)}};
412417 }
413418
414419 /// Get the operand corresponding to the conditional code result. By default,
415420 /// this is 0 (no register).
416421 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
417 return MachineOperand::CreateReg(CCReg, 0);
422 return MachineOperand::CreateReg(CCReg, false);
418423 }
419424
420425 /// Get the operand corresponding to the conditional code result for Thumb1.
521526 unsigned FrameReg, int &Offset,
522527 const ARMBaseInstrInfo &TII);
523528
524 } // End llvm namespace
525
526 #endif
529 } // end namespace llvm
530
531 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "ARMBaseRegisterInfo.h"
1413 #include "ARM.h"
1514 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
1616 #include "ARMFrameLowering.h"
1717 #include "ARMMachineFunctionInfo.h"
1818 #include "ARMSubtarget.h"
1919 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "MCTargetDesc/ARMBaseInfo.h"
2021 #include "llvm/ADT/BitVector.h"
2122 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
2225 #include "llvm/CodeGen/MachineConstantPool.h"
2326 #include "llvm/CodeGen/MachineFrameInfo.h"
2427 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstr.h"
2529 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineOperand.h"
2631 #include "llvm/CodeGen/MachineRegisterInfo.h"
2732 #include "llvm/CodeGen/RegisterScavenging.h"
2833 #include "llvm/CodeGen/VirtRegMap.h"
34 #include "llvm/IR/Attributes.h"
2935 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/DebugLoc.h"
3137 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
38 #include "llvm/IR/Type.h"
39 #include "llvm/MC/MCInstrDesc.h"
3340 #include "llvm/Support/Debug.h"
3441 #include "llvm/Support/ErrorHandling.h"
3542 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
43 #include "llvm/Target/TargetInstrInfo.h"
3744 #include "llvm/Target/TargetMachine.h"
3845 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include
48 #include
3949
4050 #define DEBUG_TYPE "arm-register-info"
4151
4555 using namespace llvm;
4656
4757 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
58 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
4959
5060 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
5161 return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
138148 else
139149 return CSR_FPRegs_RegMask;
140150 }
141
142151
143152 const uint32_t *
144153 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
474483 Scale = 4;
475484 break;
476485 }
477 case ARMII::AddrMode2: {
486 case ARMII::AddrMode2:
478487 ImmIdx = Idx+2;
479488 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
480489 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
481490 InstrOffs = -InstrOffs;
482491 break;
483 }
484 case ARMII::AddrMode3: {
492 case ARMII::AddrMode3:
485493 ImmIdx = Idx+2;
486494 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
487495 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
488496 InstrOffs = -InstrOffs;
489497 break;
490 }
491 case ARMII::AddrModeT1_s: {
498 case ARMII::AddrModeT1_s:
492499 ImmIdx = Idx+1;
493500 InstrOffs = MI->getOperand(ImmIdx).getImm();
494501 Scale = 4;
495502 break;
496 }
497503 default:
498504 llvm_unreachable("Unsupported addressing mode!");
499505 }
636642 assert(AFI->isThumb2Function());
637643 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
638644 }
639 assert (Done && "Unable to resolve frame index!");
645 assert(Done && "Unable to resolve frame index!");
640646 (void)Done;
641647 }
642648
1414 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
1515
1616 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/IR/CallingConv.h"
20 #include "llvm/MC/MCRegisterInfo.h"
1721 #include "llvm/Target/TargetRegisterInfo.h"
22 #include
1823
1924 #define GET_REGINFO_HEADER
2025 #include "ARMGenRegisterInfo.inc"
2126
2227 namespace llvm {
28
2329 /// Register allocation hints.
2430 namespace ARMRI {
31
2532 enum {
2633 RegPairOdd = 1,
2734 RegPairEven = 2
2835 };
29 }
36
37 } // end namespace ARMRI
3038
3139 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
3240 /// or a stack/pc register that we should push/pop.
3341 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
3442 using namespace ARM;
43
3544 switch (Reg) {
3645 case R0: case R1: case R2: case R3:
3746 case R4: case R5: case R6: case R7:
4756
4857 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
4958 using namespace ARM;
59
5060 switch (Reg) {
5161 case R8: case R9: case R10: case R11: case R12:
5262 // iOS has this second area.
5868
5969 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
6070 using namespace ARM;
71
6172 switch (Reg) {
6273 case D15: case D14: case D13: case D12:
6374 case D11: case D10: case D9: case D8:
8697 /// BasePtr - ARM physical register used as a base ptr in complex stack
8798 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
8899 /// variable size stack objects.
89 unsigned BasePtr;
100 unsigned BasePtr = ARM::R6;
90101
91102 // Can be only subclassed.
92103 explicit ARMBaseRegisterInfo();
197208
198209 } // end namespace llvm
199210
200 #endif
211 #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
1617 #include "ARMBaseRegisterInfo.h"
1718 #include "ARMCallingConv.h"
1819 #include "ARMConstantPoolValue.h"
2021 #include "ARMMachineFunctionInfo.h"
2122 #include "ARMSubtarget.h"
2223 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMBaseInfo.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
2329 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
2431 #include "llvm/CodeGen/FastISel.h"
2532 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
2634 #include "llvm/CodeGen/MachineConstantPool.h"
2735 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstr.h"
2837 #include "llvm/CodeGen/MachineInstrBuilder.h"
2938 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
39 #include "llvm/CodeGen/MachineOperand.h"
3140 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/MachineValueType.h"
42 #include "llvm/CodeGen/RuntimeLibcalls.h"
43 #include "llvm/CodeGen/ValueTypes.h"
44 #include "llvm/IR/Argument.h"
45 #include "llvm/IR/Attributes.h"
3246 #include "llvm/IR/CallSite.h"
3347 #include "llvm/IR/CallingConv.h"
48 #include "llvm/IR/Constant.h"
49 #include "llvm/IR/Constants.h"
3450 #include "llvm/IR/DataLayout.h"
3551 #include "llvm/IR/DerivedTypes.h"
52 #include "llvm/IR/Function.h"
3653 #include "llvm/IR/GetElementPtrTypeIterator.h"
54 #include "llvm/IR/GlobalValue.h"
3755 #include "llvm/IR/GlobalVariable.h"
56 #include "llvm/IR/InstrTypes.h"
57 #include "llvm/IR/Instruction.h"
3858 #include "llvm/IR/Instructions.h"
3959 #include "llvm/IR/IntrinsicInst.h"
4060 #include "llvm/IR/Module.h"
4161 #include "llvm/IR/Operator.h"
62 #include "llvm/IR/Type.h"
63 #include "llvm/IR/User.h"
64 #include "llvm/IR/Value.h"
65 #include "llvm/MC/MCInstrDesc.h"
66 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Support/Casting.h"
68 #include "llvm/Support/Compiler.h"
4269 #include "llvm/Support/ErrorHandling.h"
70 #include "llvm/Support/MathExtras.h"
4371 #include "llvm/Target/TargetInstrInfo.h"
4472 #include "llvm/Target/TargetLowering.h"
4573 #include "llvm/Target/TargetMachine.h"
4674 #include "llvm/Target/TargetOptions.h"
75 #include
76 #include
77 #include
78
4779 using namespace llvm;
4880
4981 namespace {
5385 enum {
5486 RegBase,
5587 FrameIndexBase
56 } BaseType;
88 } BaseType = RegBase;
5789
5890 union {
5991 unsigned Reg;
6092 int FI;
6193 } Base;
6294
63 int Offset;
95 int Offset = 0;
6496
6597 // Innocuous defaults for our address.
66 Address()
67 : BaseType(RegBase), Offset(0) {
68 Base.Reg = 0;
69 }
98 Address() {
99 Base.Reg = 0;
100 }
70101 } Address;
71102
72103 class ARMFastISel final : public FastISel {
73
74104 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
75105 /// make the right decision when generating code for different targets.
76106 const ARMSubtarget *Subtarget;
98128 Context = &funcInfo.Fn->getContext();
99129 }
100130
131 private:
101132 // Code from FastISel.cpp.
102 private:
133
103134 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
104135 const TargetRegisterClass *RC,
105136 unsigned Op0, bool Op0IsKill);
116147 uint64_t Imm);
117148
118149 // Backend specific FastISel code.
119 private:
150
120151 bool fastSelectInstruction(const Instruction *I) override;
121152 unsigned fastMaterializeConstant(const Constant *C) override;
122153 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
123154 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
124155 const LoadInst *LI) override;
125156 bool fastLowerArguments() override;
126 private:
157
127158 #include "ARMGenFastISel.inc"
128159
129160 // Instruction selection routines.
130 private:
161
131162 bool SelectLoad(const Instruction *I);
132163 bool SelectStore(const Instruction *I);
133164 bool SelectBranch(const Instruction *I);
150181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
151182
152183 // Utility routines.
153 private:
184
154185 bool isPositionIndependent() const;
155186 bool isTypeLegal(Type *Ty, MVT &VT);
156187 bool isLoadTypeLegal(Type *Ty, MVT &VT);
178209 const TargetLowering *getTargetLowering() { return &TLI; }
179210
180211 // Call handling routines.
181 private:
212
182213 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
183214 bool Return,
184215 bool isVarArg);
197228 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
198229
199230 // OptionalDef handling routines.
200 private:
231
201232 bool isARMNEONPred(const MachineInstr *MI);
202233 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
203234 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
429460 }
430461
431462 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
432
433463 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
434464 return 0;
435465
734764 TmpOffset += SL->getElementOffset(Idx);
735765 } else {
736766 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
737 for (;;) {
767 while (true) {
738768 if (const ConstantInt *CI = dyn_cast(Op)) {
739769 // Constant-offset addressing.
740770 TmpOffset += CI->getSExtValue() * S;
966996 // Create the base instruction, then add the operands.
967997 if (allocReg)
968998 ResultReg = createResultReg(RC);
969 assert (ResultReg > 255 && "Expected an allocated virtual register.");
999 assert(ResultReg > 255 && "Expected an allocated virtual register.");
9701000 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
9711001 TII.get(Opc), ResultReg);
9721002 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
12111241 // behavior.
12121242 if (const CmpInst *CI = dyn_cast(BI->getCondition())) {
12131243 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1214
12151244 // Get the compare predicate.
12161245 // Try to take advantage of fallthrough opportunities.
12171246 CmpInst::Predicate Predicate = CI->getPredicate();
15911620 bool UseImm = false;
15921621 bool isNegativeImm = false;
15931622 if (const ConstantInt *ConstInt = dyn_cast(I->getOperand(2))) {
1594 assert (VT == MVT::i32 && "Expecting an i32.");
1623 assert(VT == MVT::i32 && "Expecting an i32.");
15951624 Imm = (int)ConstInt->getValue().getZExtValue();
15961625 if (Imm < 0) {
15971626 isNegativeImm = true;
19211950 case CCValAssign::SExt: {
19221951 MVT DestVT = VA.getLocVT();
19231952 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1924 assert (Arg != 0 && "Failed to emit a sext");
1953 assert(Arg != 0 && "Failed to emit a sext");
19251954 ArgVT = DestVT;
19261955 break;
19271956 }
19301959 case CCValAssign::ZExt: {
19311960 MVT DestVT = VA.getLocVT();
19321961 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1933 assert (Arg != 0 && "Failed to emit a zext");
1962 assert(Arg != 0 && "Failed to emit a zext");
19341963 ArgVT = DestVT;
19351964 break;
19361965 }
24132442 else if (Len >= 2)
24142443 VT = MVT::i16;
24152444 else {
2416 assert (Len == 1 && "Expected a length of 1!");
2445 assert(Len == 1 && "Expected a length of 1!");
24172446 VT = MVT::i8;
24182447 }
24192448 } else {
24282457 bool RV;
24292458 unsigned ResultReg;
24302459 RV = ARMEmitLoad(VT, ResultReg, Src);
2431 assert (RV == true && "Should be able to handle this load.");
2460 assert(RV && "Should be able to handle this load.");
24322461 RV = ARMEmitStore(VT, ResultReg, Dest);
2433 assert (RV == true && "Should be able to handle this store.");
2462 assert(RV && "Should be able to handle this store.");
24342463 (void)RV;
24352464
24362465 unsigned Size = VT.getSizeInBits()/8;
27762805
27772806 // TODO: SoftFP support.
27782807 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2779
27802808 switch (I->getOpcode()) {
27812809 case Instruction::Load:
27822810 return SelectLoad(I);
28462874 }
28472875
28482876 namespace {
2877
28492878 // This table describes sign- and zero-extend instructions which can be
28502879 // folded into a preceding load. All of these extends have an immediate
28512880 // (sometimes a mask and sometimes a shift) that's applied after
28622891 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
28632892 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
28642893 };
2865 }
2894
2895 } // end anonymous namespace
28662896
28672897 /// \brief The specified machine instr operand is a vreg, and that
28682898 /// vreg is being provided by the specified load instruction. If possible,
30063036 return false;
30073037 }
30083038 }
3009
30103039
30113040 static const MCPhysReg GPRArgRegs[] = {
30123041 ARM::R0, ARM::R1, ARM::R2, ARM::R3
30323061 }
30333062
30343063 namespace llvm {
3064
30353065 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
30363066 const TargetLibraryInfo *libInfo) {
30373067 if (funcInfo.MF->getSubtarget().useFastISel())
30393069
30403070 return nullptr;
30413071 }
3042 }
3072
3073 } // end namespace llvm
99 //
1010 //===----------------------------------------------------------------------===//
1111
12 #include "ARMTargetMachine.h"
1312 #include "ARM.h"
1413 #include "ARMCallLowering.h"
15 #include "ARMFrameLowering.h"
1614 #include "ARMInstructionSelector.h"
1715 #include "ARMLegalizerInfo.h"
1816 #include "ARMRegisterBankInfo.h"
17 #include "ARMSubtarget.h"
18 #include "ARMTargetMachine.h"
1919 #include "ARMTargetObjectFile.h"
2020 #include "ARMTargetTransformInfo.h"
21 #include "MCTargetDesc/ARMMCTargetDesc.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
2129 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
2230 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
2332 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
2434 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
2537 #include "llvm/CodeGen/Passes.h"
2638 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
2741 #include "llvm/IR/Function.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
3044 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/FormattedStream.h"
45 #include "llvm/Support/ErrorHandling.h"
3246 #include "llvm/Support/TargetParser.h"
3347 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
3449 #include "llvm/Target/TargetOptions.h"
3550 #include "llvm/Transforms/Scalar.h"
51 #include
52 #include
53 #include
54
3655 using namespace llvm;
3756
3857 static cl::opt
7190
7291 static std::unique_ptr createTLOF(const Triple &TT) {
7392 if (TT.isOSBinFormatMachO())
74 return make_unique();
93 return llvm::make_unique();
7594 if (TT.isOSWindows())
76 return make_unique();
77 return make_unique>();
95 return llvm::make_unique>();
96 return llvm::make_unique();
7897 }
7998
8099 static ARMBaseTargetMachine::ARMABI
93112 ARMBaseTargetMachine::ARMABI TargetABI =
94113 ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
95114
96 unsigned ArchKind = llvm::ARM::parseCPUArch(CPU);
97 StringRef ArchName = llvm::ARM::getArchName(ArchKind);
115 unsigned ArchKind = ARM::parseCPUArch(CPU);
116 StringRef ArchName = ARM::getArchName(ArchKind);
98117 // FIXME: This is duplicated code from the front end and should be unified.
99118 if (TT.isOSBinFormatMachO()) {
100 if (TT.getEnvironment() == llvm::Triple::EABI ||
101 (TT.getOS() == llvm::Triple::UnknownOS && TT.isOSBinFormatMachO()) ||
102 llvm::ARM::parseArchProfile(ArchName) == llvm::ARM::PK_M) {
119 if (TT.getEnvironment() == Triple::EABI ||
120 (TT.getOS() == Triple::UnknownOS && TT.isOSBinFormatMachO()) ||
121 ARM::parseArchProfile(ArchName) == ARM::PK_M) {
103122 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
104123 } else if (TT.isWatchABI()) {
105124 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS16;
112131 } else {
113132 // Select the default based on the platform.
114133 switch (TT.getEnvironment()) {
115 case llvm::Triple::Android:
116 case llvm::Triple::GNUEABI:
117 case llvm::Triple::GNUEABIHF:
118 case llvm::Triple::MuslEABI:
119 case llvm::Triple::MuslEABIHF:
120 case llvm::Triple::EABIHF:
121 case llvm::Triple::EABI:
134 case Triple::Android:
135 case Triple::GNUEABI:
136 case Triple::GNUEABIHF:
137 case Triple::MuslEABI:
138 case Triple::MuslEABIHF:
139 case Triple::EABIHF:
140 case Triple::EABI:
122141 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
123142 break;
124 case llvm::Triple::GNU:
143 case Triple::GNU:
125144 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
126145 break;
127146 default:
140159 const TargetOptions &Options,
141160 bool isLittle) {
142161 auto ABI = computeTargetABI(TT, CPU, Options);
143 std::string Ret = "";
162 std::string Ret;
144163
145164 if (isLittle)
146165 // Little endian.
237256 }
238257 }
239258
240 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
259 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
241260
242261 #ifdef LLVM_BUILD_GLOBAL_ISEL
243262 namespace {
263
244264 struct ARMGISelActualAccessor : public GISelAccessor {
245265 std::unique_ptr CallLoweringInfo;
246266 std::unique_ptr InstSelector;
247267 std::unique_ptr Legalizer;
248268 std::unique_ptr RegBankInfo;
269
249270 const CallLowering *getCallLowering() const override {
250271 return CallLoweringInfo.get();
251272 }
273
252274 const InstructionSelector *getInstructionSelector() const override {
253275 return InstSelector.get();
254276 }
277
255278 const LegalizerInfo *getLegalizerInfo() const override {
256279 return Legalizer.get();
257280 }
281
258282 const RegisterBankInfo *getRegBankInfo() const override {
259283 return RegBankInfo.get();
260284 }
261285 };
262 } // End anonymous namespace.
286
287 } // end anonymous namespace
263288 #endif
264289
265290 const ARMSubtarget *
389414 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
390415
391416 namespace {
417
392418 /// ARM Code Generator Pass Configuration Options.
393419 class ARMPassConfig : public TargetPassConfig {
394420 public:
412438 void addPreSched2() override;
413439 void addPreEmitPass() override;
414440 };
415 } // namespace
441
442 } // end anonymous namespace
416443
417444 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
418445 return new ARMPassConfig(this, PM);
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
1414 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
1515
16 #include "ARMInstrInfo.h"
1716 #include "ARMSubtarget.h"
18 #include "llvm/IR/DataLayout.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/StringMap.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/CodeGen.h"
1922 #include "llvm/Target/TargetMachine.h"
23 #include
2024
2125 namespace llvm {
2226
3135
3236 protected:
3337 std::unique_ptr TLOF;
34 ARMSubtarget Subtarget;
38 ARMSubtarget Subtarget;
3539 bool isLittle;
3640 mutable StringMap> SubtargetMap;
3741
6165 ///
6266 class ARMTargetMachine : public ARMBaseTargetMachine {
6367 virtual void anchor();
64 public:
68
69 public:
6570 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
6671 StringRef FS, const TargetOptions &Options,
6772 Optional RM, CodeModel::Model CM,
7277 ///
7378 class ARMLETargetMachine : public ARMTargetMachine {
7479 void anchor() override;
80
7581 public:
7682 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
7783 StringRef FS, const TargetOptions &Options,
8389 ///
8490 class ARMBETargetMachine : public ARMTargetMachine {
8591 void anchor() override;
92
8693 public:
8794 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
8895 StringRef FS, const TargetOptions &Options,
96103 ///
97104 class ThumbTargetMachine : public ARMBaseTargetMachine {
98105 virtual void anchor();
106
99107 public:
100108 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
101109 StringRef FS, const TargetOptions &Options,
107115 ///
108116 class ThumbLETargetMachine : public ThumbTargetMachine {
109117 void anchor() override;
118
110119 public:
111120 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
112121 StringRef FS, const TargetOptions &Options,
118127 ///
119128 class ThumbBETargetMachine : public ThumbTargetMachine {
120129 void anchor() override;
130
121131 public:
122132 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
123133 StringRef FS, const TargetOptions &Options,
127137
128138 } // end namespace llvm
129139
130 #endif
140 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
66 //
77 //===----------------------------------------------------------------------===//
88
9 #include "ARMSubtarget.h"
10 #include "ARMTargetMachine.h"
911 #include "ARMTargetObjectFile.h"
10 #include "ARMTargetMachine.h"
11 #include "llvm/ADT/StringExtras.h"
12 #include "llvm/IR/Mangler.h"
1312 #include "llvm/MC/MCAsmInfo.h"
1413 #include "llvm/MC/MCContext.h"
1514 #include "llvm/MC/MCExpr.h"
1615 #include "llvm/MC/MCSectionELF.h"
16 #include "llvm/MC/MCTargetOptions.h"
17 #include "llvm/MC/SectionKind.h"
1718 #include "llvm/Support/Dwarf.h"
1819 #include "llvm/Support/ELF.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include
22
2023 using namespace llvm;
2124 using namespace dwarf;
2225
1010 #define LLVM_LIB_TARGET_ARM_ARMTARGETOBJECTFILE_H
1111
1212 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
13 #include "llvm/MC/MCExpr.h"
1314
1415 namespace llvm {
1516
16 class MCContext;
17 class TargetMachine;
18
1917 class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
2018 mutable bool genExecuteOnly = false;
19
2120 protected:
22 const MCSection *AttributesSection;
21 const MCSection *AttributesSection = nullptr;
22
2323 public:
2424 ARMElfTargetObjectFile()
25 : TargetLoweringObjectFileELF(), AttributesSection(nullptr) {
25 : TargetLoweringObjectFileELF() {
2626 PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;
2727 }
2828
4646
4747 } // end namespace llvm
4848
49 #endif
49 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETOBJECTFILE_H
1313
1414 #include "ARMUnwindOpAsm.h"
1515 #include "llvm/Support/ARMEHABI.h"
16 #include "llvm/Support/ErrorHandling.h"
1716 #include "llvm/Support/LEB128.h"
17 #include "llvm/Support/MathExtras.h"
18 #include
1819
1920 using namespace llvm;
2021
2122 namespace {
23
2224 /// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
2325 /// with MSB to LSB per uint32_t ordering. For example, the first byte will
2426 /// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
2628 class UnwindOpcodeStreamer {
2729 private:
2830 SmallVectorImpl &Vec;
29 size_t Pos;
31 size_t Pos = 3;
3032
3133 public:
32 UnwindOpcodeStreamer(SmallVectorImpl &V) : Vec(V), Pos(3) {
33 }
34 UnwindOpcodeStreamer(SmallVectorImpl &V) : Vec(V) {}
3435
3536 /// Emit the byte in MSB to LSB per uint32_t order.
36 inline void EmitByte(uint8_t elem) {
37 void EmitByte(uint8_t elem) {
3738 Vec[Pos] = elem;
3839 Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
3940 }
4041
4142 /// Emit the size prefix.
42 inline void EmitSize(size_t Size) {
43 void EmitSize(size_t Size) {
4344 size_t SizeInWords = (Size + 3) / 4;
4445 assert(SizeInWords <= 0x100u &&
4546 "Only 256 additional words are allowed for unwind opcodes");
4748 }
4849
4950 /// Emit the personality index prefix.
50 inline void EmitPersonalityIndex(unsigned PI) {
51 void EmitPersonalityIndex(unsigned PI) {
5152 assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX &&
5253 "Invalid personality prefix");
5354 EmitByte(ARM::EHABI::EHT_COMPACT | PI);
5455 }
5556
5657 /// Fill the rest of bytes with FINISH opcode.
57 inline void FillFinishOpcode() {
58 void FillFinishOpcode() {
5859 while (Pos < Vec.size())
5960 EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH);
6061 }
6162 };
62 }
63
64 } // end anonymous namespace
6365
6466 void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
6567 if (RegSave == 0u)
152154
153155 void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
154156 SmallVectorImpl &Result) {
155
156157 UnwindOpcodeStreamer OpStreamer(Result);
157158
158159 if (HasPersonality) {
1515 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
1616
1717 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/Support/ARMEHABI.h"
19 #include "llvm/Support/DataTypes.h"
18 #include
19 #include
2020
2121 namespace llvm {
2222
2424
2525 class UnwindOpcodeAssembler {
2626 private:
27 llvm::SmallVector Ops;
28 llvm::SmallVector OpBegins;
29 bool HasPersonality;
27 SmallVector Ops;
28 SmallVector OpBegins;
29 bool HasPersonality = false;
3030
3131 public:
32 UnwindOpcodeAssembler()
33 : HasPersonality(0) {
32 UnwindOpcodeAssembler() {
3433 OpBegins.push_back(0);
3534 }
3635
3938 Ops.clear();
4039 OpBegins.clear();
4140 OpBegins.push_back(0);
42 HasPersonality = 0;
41 HasPersonality = false;
4342 }
4443
4544 /// Set the personality
4645 void setPersonality(const MCSymbol *Per) {
47 HasPersonality = 1;
46 HasPersonality = true;
4847 }
4948
5049 /// Emit unwind opcodes for .save directives
8786 }
8887 };
8988
90 } // namespace llvm
89 } // end namespace llvm
9190
92 #endif
91 #endif // LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
99 #include "ARM.h"
1010 #include "ARMBaseInstrInfo.h"
1111 #include "ARMSubtarget.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
1313 #include "Thumb2InstrInfo.h"
1414 #include "llvm/ADT/DenseMap.h"
1515 #include "llvm/ADT/PostOrderIterator.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
1618 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFunction.h"
1723 #include "llvm/CodeGen/MachineFunctionPass.h"
1824 #include "llvm/CodeGen/MachineInstr.h"
1925 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/IR/Function.h" // To access Function attributes
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCRegisterInfo.h"
2131 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
2233 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
2335 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include
38 #include
39 #include
40 #include
41 #include
2542 #include
43
2644 using namespace llvm;
2745
2846 #define DEBUG_TYPE "t2-reduce-size"
3957 cl::init(-1), cl::Hidden);
4058
4159 namespace {
60
4261 /// ReduceTable - A static table with information on mapping from wide
4362 /// opcodes to narrow
4463 struct ReduceEntry {
138157 class Thumb2SizeReduce : public MachineFunctionPass {
139158 public:
140159 static char ID;
141 Thumb2SizeReduce(std::function Ftor);
142160
143161 const Thumb2InstrInfo *TII;
144162 const ARMSubtarget *STI;
163
164 Thumb2SizeReduce(std::function Ftor);
145165
146166 bool runOnMachineFunction(MachineFunction &MF) override;
147167
200220
201221 struct MBBInfo {
202222 // The flags leaving this block have high latency.
203 bool HighLatencyCPSR;
223 bool HighLatencyCPSR = false;
204224 // Has this block been visited yet?
205 bool Visited;
206
207 MBBInfo() : HighLatencyCPSR(false), Visited(false) {}
225 bool Visited = false;
226
227 MBBInfo() = default;
208228 };
209229
210230 SmallVector BlockInfo;
211231
212232 std::function PredicateFtor;
213233 };
234
214235 char Thumb2SizeReduce::ID = 0;
215 }
236
237 } // end anonymous namespace
216238
217239 Thumb2SizeReduce::Thumb2SizeReduce(std::function Ftor)
218240 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
489511 isLdStMul = true;
490512 break;
491513 }
492 case ARM::t2STMIA: {
514 case ARM::t2STMIA:
493515 // If the base register is killed, we don't care what its value is after the
494516 // instruction, so we can use an updating STMIA.
495517 if (!MI->getOperand(0).isKill())
496518 return false;
497519
498520 break;
499 }
500521 case ARM::t2LDMIA_RET: {
501522 unsigned BaseReg = MI->getOperand(1).getReg();
502523 if (BaseReg != ARM::SP)
652673 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
653674 switch (Opc) {
654675 default: break;
655 case ARM::t2ADDSri: {
676 case ARM::t2ADDSri:
656677 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
657678 return true;
658679 LLVM_FALLTHROUGH;
659 }
660680 case ARM::t2ADDSrr:
661681 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
662682 }
698718 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
699719 const ReduceEntry &Entry,
700720 bool LiveCPSR, bool IsSelfLoop) {
701
702721 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
703722 return false;
704723