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Define multiclasses for FP-to-FP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 8 years ago
1 changed file(s) with 11 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
8888 def _D64 : FFR1;
8989 }
9090
91 multiclass FFR1_2 funct, string asmstr, SDNode FOp>
92 {
93 def _S32 : FFR1P;
94 def _D32 : FFR1P,
95 Requires<[NotFP64bit]>;
91 // FP-to-FP conversion instructions.
92 multiclass FFR1P_M funct, string opstr, SDNode OpNode> {
93 def _S : FFR1P;
94 def _D32 : FFR1P,
95 Requires<[NotFP64bit]>;
96 def _D64 : FFR1P,
97 Requires<[IsFP64bit]>;
9698 }
9799
98100 multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> {
140142 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
141143 }
142144
143 let ft = 0 in {
144 defm FABS : FFR1_2<0b000101, "abs", fabs>;
145 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
146 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
147 }
145 defm FABS : FFR1P_M<0x5, "abs", fabs>;
146 defm FNEG : FFR1P_M<0x7, "neg", fneg>;
147 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
148148
149149 // The odd-numbered registers are only referenced when doing loads,
150150 // stores, and moves between floating-point and integer registers.
332332 }]>;
333333
334334 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
335 def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
335 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
336336
337337 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
338338 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;