llvm.org GIT mirror llvm / bf8e0ff
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357341 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
4 changed file(s) with 40 addition(s) and 47 deletion(s). Raw diff Collapse all Expand all
632632 return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
633633
634634 SDLoc DL(N);
635
636 // It's cheaper to materialise two 32-bit integers than to load a double
637 // from the constant pool and transfer it to integer registers through the
638 // stack.
639 if (ConstantFPSDNode *C = dyn_cast(Op0)) {
640 APInt V = C->getValueAPF().bitcastToAPInt();
641 SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32);
642 SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32);
643 return DCI.CombineTo(N, Lo, Hi);
644 }
645
635646 // This is a target-specific version of a DAGCombine performed in
636647 // DAGCombiner::visitBITCAST. It performs the equivalent of:
637648 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3333 ; RV32IFD: # %bb.0:
3434 ; RV32IFD-NEXT: addi sp, sp, -16
3535 ; RV32IFD-NEXT: sw ra, 12(sp)
36 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
37 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
38 ; RV32IFD-NEXT: fld ft0, 0(a0)
39 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
40 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
41 ; RV32IFD-NEXT: fld ft1, 0(a0)
42 ; RV32IFD-NEXT: fsd ft1, 0(sp)
43 ; RV32IFD-NEXT: lw a0, 0(sp)
44 ; RV32IFD-NEXT: lw a1, 4(sp)
45 ; RV32IFD-NEXT: fsd ft0, 0(sp)
46 ; RV32IFD-NEXT: lw a2, 0(sp)
47 ; RV32IFD-NEXT: lw a3, 4(sp)
36 ; RV32IFD-NEXT: lui a0, 262236
37 ; RV32IFD-NEXT: addi a1, a0, 655
38 ; RV32IFD-NEXT: lui a0, 377487
39 ; RV32IFD-NEXT: addi a0, a0, 1475
40 ; RV32IFD-NEXT: lui a2, 262364
41 ; RV32IFD-NEXT: addi a3, a2, 655
42 ; RV32IFD-NEXT: mv a2, a0
4843 ; RV32IFD-NEXT: call callee_double_inreg
4944 ; RV32IFD-NEXT: lw ra, 12(sp)
5045 ; RV32IFD-NEXT: addi sp, sp, 16
7772 define double @caller_double_split_reg_stack() nounwind {
7873 ; RV32IFD-LABEL: caller_double_split_reg_stack:
7974 ; RV32IFD: # %bb.0:
80 ; RV32IFD-NEXT: addi sp, sp, -32
81 ; RV32IFD-NEXT: sw ra, 28(sp)
82 ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
83 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_0)
84 ; RV32IFD-NEXT: fld ft0, 0(a0)
85 ; RV32IFD-NEXT: fsd ft0, 16(sp)
86 ; RV32IFD-NEXT: lw a7, 16(sp)
87 ; RV32IFD-NEXT: lw a0, 20(sp)
75 ; RV32IFD-NEXT: addi sp, sp, -16
76 ; RV32IFD-NEXT: sw ra, 12(sp)
77 ; RV32IFD-NEXT: lui a0, 262510
78 ; RV32IFD-NEXT: addi a0, a0, 327
8879 ; RV32IFD-NEXT: sw a0, 0(sp)
89 ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_1)
90 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_1)
91 ; RV32IFD-NEXT: fld ft0, 0(a0)
92 ; RV32IFD-NEXT: fsd ft0, 16(sp)
93 ; RV32IFD-NEXT: lw a5, 16(sp)
94 ; RV32IFD-NEXT: lw a6, 20(sp)
80 ; RV32IFD-NEXT: lui a0, 262446
81 ; RV32IFD-NEXT: addi a6, a0, 327
82 ; RV32IFD-NEXT: lui a0, 713032
83 ; RV32IFD-NEXT: addi a5, a0, -1311
9584 ; RV32IFD-NEXT: addi a0, zero, 1
9685 ; RV32IFD-NEXT: addi a1, zero, 2
9786 ; RV32IFD-NEXT: mv a2, zero
9887 ; RV32IFD-NEXT: addi a3, zero, 3
9988 ; RV32IFD-NEXT: mv a4, zero
89 ; RV32IFD-NEXT: mv a7, a5
10090 ; RV32IFD-NEXT: call callee_double_split_reg_stack
101 ; RV32IFD-NEXT: lw ra, 28(sp)
102 ; RV32IFD-NEXT: addi sp, sp, 32
91 ; RV32IFD-NEXT: lw ra, 12(sp)
92 ; RV32IFD-NEXT: addi sp, sp, 16
10393 ; RV32IFD-NEXT: ret
10494 %1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
10595 ret double %1
99 ;
1010 ; RV32IFD-LABEL: double_imm:
1111 ; RV32IFD: # %bb.0:
12 ; RV32IFD-NEXT: addi sp, sp, -16
13 ; RV32IFD-NEXT: lui a0, %hi(.LCPI0_0)
14 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI0_0)
15 ; RV32IFD-NEXT: fld ft0, 0(a0)
16 ; RV32IFD-NEXT: fsd ft0, 8(sp)
17 ; RV32IFD-NEXT: lw a0, 8(sp)
18 ; RV32IFD-NEXT: lw a1, 12(sp)
19 ; RV32IFD-NEXT: addi sp, sp, 16
12 ; RV32IFD-NEXT: lui a0, 345155
13 ; RV32IFD-NEXT: addi a0, a0, -744
14 ; RV32IFD-NEXT: lui a1, 262290
15 ; RV32IFD-NEXT: addi a1, a1, 507
2016 ; RV32IFD-NEXT: ret
2117 ;
2218 ; RV64IFD-LABEL: double_imm:
1616 ; RV32IFD: # %bb.0: # %entry
1717 ; RV32IFD-NEXT: addi sp, sp, -16
1818 ; RV32IFD-NEXT: sw ra, 12(sp)
19 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
20 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
21 ; RV32IFD-NEXT: fld ft0, 0(a0)
22 ; RV32IFD-NEXT: fsd ft0, 0(sp)
23 ; RV32IFD-NEXT: lw a0, 0(sp)
24 ; RV32IFD-NEXT: lw a1, 4(sp)
19 ; RV32IFD-NEXT: mv a0, zero
20 ; RV32IFD-NEXT: lui a1, 262144
2521 ; RV32IFD-NEXT: call test
26 ; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1)
27 ; RV32IFD-NEXT: addi a2, a2, %lo(.LCPI1_1)
28 ; RV32IFD-NEXT: fld ft1, 0(a2)
2922 ; RV32IFD-NEXT: sw a0, 0(sp)
3023 ; RV32IFD-NEXT: sw a1, 4(sp)
3124 ; RV32IFD-NEXT: fld ft0, 0(sp)
25 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
26 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
27 ; RV32IFD-NEXT: fld ft1, 0(a0)
3228 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
3329 ; RV32IFD-NEXT: bnez a0, .LBB1_3
3430 ; RV32IFD-NEXT: # %bb.1: # %entry
35 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_2)
36 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_2)
31 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
32 ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
3733 ; RV32IFD-NEXT: fld ft1, 0(a0)
3834 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
3935 ; RV32IFD-NEXT: xori a0, a0, 1