llvm.org GIT mirror llvm / bf2c8b3
Added MRegisterInfo hook to re-materialize an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
13 changed file(s) with 106 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
373373 unsigned DestReg, unsigned SrcReg,
374374 const TargetRegisterClass *RC) const = 0;
375375
376 /// reMaterialize - Re-issue the specified 'original' instruction at the
377 /// specific location targeting a new destination register.
378 virtual void reMaterialize(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MI,
380 unsigned DestReg,
381 const MachineInstr *Orig) const = 0;
382
376383 /// foldMemoryOperand - Attempt to fold a load or store of the
377384 /// specified stack slot into the specified machine instruction for
378385 /// the specified operand. If this is possible, a new instruction
194194 abort();
195195 }
196196
197 /// emitLoadConstPool - Emits a load from constpool to materialize the
198 /// specified immediate.
199 static void emitLoadConstPool(MachineBasicBlock &MBB,
200 MachineBasicBlock::iterator &MBBI,
201 unsigned DestReg, int Val,
202 const TargetInstrInfo &TII, bool isThumb) {
203 MachineFunction &MF = *MBB.getParent();
204 MachineConstantPool *ConstantPool = MF.getConstantPool();
205 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
206 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
207 if (isThumb)
208 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
209 else
210 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
211 .addReg(0).addImm(0);
212 }
213
214 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator I,
216 unsigned DestReg,
217 const MachineInstr *Orig) const {
218 if (Orig->getOpcode() == ARM::MOVi2pieces) {
219 emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(),
220 TII, false);
221 return;
222 }
223
224 MachineInstr *MI = Orig->clone();
225 MI->getOperand(0).setReg(DestReg);
226 MBB.insert(I, MI);
227 }
228
197229 /// isLowRegister - Returns true if the register is low register r0-r7.
198230 ///
199231 static bool isLowRegister(unsigned Reg) {
407439 if (ExtraOpc)
408440 NumMIs++;
409441 return NumMIs;
410 }
411
412 /// emitLoadConstPool - Emits a load from constpool to materialize NumBytes
413 /// immediate.
414 static void emitLoadConstPool(MachineBasicBlock &MBB,
415 MachineBasicBlock::iterator &MBBI,
416 unsigned DestReg, int NumBytes,
417 const TargetInstrInfo &TII) {
418 MachineFunction &MF = *MBB.getParent();
419 MachineConstantPool *ConstantPool = MF.getConstantPool();
420 Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
421 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
422 BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
423442 }
424443
425444 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
458477 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
459478 .addReg(LdReg, false, false, true);
460479 } else
461 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
480 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true);
462481
463482 // Emit add / sub.
464483 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
884903 if (FrameReg == ARM::SP)
885904 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
886905 else {
887 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
906 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
888907 UseRR = true;
889908 }
890909 } else
919938 if (FrameReg == ARM::SP)
920939 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
921940 else {
922 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
941 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
923942 UseRR = true;
924943 }
925944 } else
5959 unsigned DestReg, unsigned SrcReg,
6060 const TargetRegisterClass *RC) const;
6161
62 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
63 unsigned DestReg, const MachineInstr *Orig) const;
64
6265 MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
6366 int FrameIndex) const;
6467
154154 }
155155 }
156156
157 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
159 unsigned DestReg,
160 const MachineInstr *Orig) const {
161 MachineInstr *MI = Orig->clone();
162 MI->getOperand(0).setReg(DestReg);
163 MBB.insert(I, MI);
164 }
165
157166 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
158167 static const unsigned CalleeSavedRegs[] = {
159168 Alpha::R9, Alpha::R10,
4444 unsigned DestReg, unsigned SrcReg,
4545 const TargetRegisterClass *RC) const;
4646
47 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
48 unsigned DestReg, const MachineInstr *Orig) const;
49
4750 const unsigned *getCalleeSavedRegs() const;
4851
4952 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
9090 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
9191 else // otherwise, MOV works (for both gen. regs and FP regs)
9292 BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
93 }
94
95 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator I,
97 unsigned DestReg,
98 const MachineInstr *Orig) const {
99 MachineInstr *MI = Orig->clone();
100 MI->getOperand(0).setReg(DestReg);
101 MBB.insert(I, MI);
93102 }
94103
95104 const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
4343 unsigned DestReg, unsigned SrcReg,
4444 const TargetRegisterClass *RC) const;
4545
46 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
47 unsigned DestReg, const MachineInstr *Orig) const;
48
4649 const unsigned *getCalleeSavedRegs() const;
4750
4851 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
238238 }
239239 }
240240
241 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
242 MachineBasicBlock::iterator I,
243 unsigned DestReg,
244 const MachineInstr *Orig) const {
245 MachineInstr *MI = Orig->clone();
246 MI->getOperand(0).setReg(DestReg);
247 MBB.insert(I, MI);
248 }
249
241250 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
242251 // 32-bit Darwin calling convention.
243252 static const unsigned Darwin32_CalleeSavedRegs[] = {
4747 void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
4848 unsigned DestReg, unsigned SrcReg,
4949 const TargetRegisterClass *RC) const;
50
51 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
52 unsigned DestReg, const MachineInstr *Orig) const;
5053
5154 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
5255 /// copy instructions, turning them into load/store instructions.
7474 .addReg(SrcReg);
7575 else
7676 assert (0 && "Can't copy this register");
77 }
78
79 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator I,
81 unsigned DestReg,
82 const MachineInstr *Orig) const {
83 MachineInstr *MI = Orig->clone();
84 MI->getOperand(0).setReg(DestReg);
85 MBB.insert(I, MI);
7786 }
7887
7988 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
4343 unsigned DestReg, unsigned SrcReg,
4444 const TargetRegisterClass *RC) const;
4545
46 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
47 unsigned DestReg, const MachineInstr *Orig) const;
48
4649 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
4750 unsigned OpNum,
4851 int FrameIndex) const;
164164 abort();
165165 }
166166 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
167 }
168
169
170 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
171 MachineBasicBlock::iterator I,
172 unsigned DestReg,
173 const MachineInstr *Orig) const {
174 MachineInstr *MI = Orig->clone();
175 MI->getOperand(0).setReg(DestReg);
176 MBB.insert(I, MI);
167177 }
168178
169179 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
5757 MachineBasicBlock::iterator MI,
5858 unsigned DestReg, unsigned SrcReg,
5959 const TargetRegisterClass *RC) const;
60
61 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
62 unsigned DestReg, const MachineInstr *Orig) const;
6063
6164 /// foldMemoryOperand - If this target supports it, fold a load or store of
6265 /// the specified stack slot into the specified machine instruction for the