llvm.org GIT mirror llvm / bed2946
Removed tabs everywhere except autogenerated & external files. Add make target for tabs checking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 13 years ago
41 changed file(s) with 392 addition(s) and 378 deletion(s). Raw diff Collapse all Expand all
17251725 endif
17261726
17271727 check-line-length:
1728 @egrep '.{81}' $(Sources)
1729
1728 @egrep -n '.{81}' $(Sources)
1729
1730 check-for-tabs:
1731 @egrep -n ' ' $(Sources)
17301732 #------------------------------------------------------------------------
17311733 # Print out the directories used for building
17321734 #------------------------------------------------------------------------
127127 int find_first() const {
128128 for (unsigned i = 0; i < NumBitWords(size()); ++i)
129129 if (Bits[i] != 0) {
130 if (sizeof(BitWord) == 4)
131 return i * BITS_PER_WORD + CountTrailingZeros_32(Bits[i]);
132 else if (sizeof(BitWord) == 8)
133 return i * BITS_PER_WORD + CountTrailingZeros_64(Bits[i]);
134 else
135 assert(0 && "Unsupported!");
130 if (sizeof(BitWord) == 4)
131 return i * BITS_PER_WORD + CountTrailingZeros_32(Bits[i]);
132 else if (sizeof(BitWord) == 8)
133 return i * BITS_PER_WORD + CountTrailingZeros_64(Bits[i]);
134 else
135 assert(0 && "Unsupported!");
136136 }
137137 return -1;
138138 }
152152
153153 if (Copy != 0) {
154154 if (sizeof(BitWord) == 4)
155 return WordPos * BITS_PER_WORD + CountTrailingZeros_32(Copy);
155 return WordPos * BITS_PER_WORD + CountTrailingZeros_32(Copy);
156156 else if (sizeof(BitWord) == 8)
157 return WordPos * BITS_PER_WORD + CountTrailingZeros_64(Copy);
157 return WordPos * BITS_PER_WORD + CountTrailingZeros_64(Copy);
158158 else
159 assert(0 && "Unsupported!");
159 assert(0 && "Unsupported!");
160160 }
161161
162162 // Check subsequent words.
163163 for (unsigned i = WordPos+1; i < NumBitWords(size()); ++i)
164164 if (Bits[i] != 0) {
165 if (sizeof(BitWord) == 4)
166 return i * BITS_PER_WORD + CountTrailingZeros_32(Bits[i]);
167 else if (sizeof(BitWord) == 8)
168 return i * BITS_PER_WORD + CountTrailingZeros_64(Bits[i]);
169 else
170 assert(0 && "Unsupported!");
165 if (sizeof(BitWord) == 4)
166 return i * BITS_PER_WORD + CountTrailingZeros_32(Bits[i]);
167 else if (sizeof(BitWord) == 8)
168 return i * BITS_PER_WORD + CountTrailingZeros_64(Bits[i]);
169 else
170 assert(0 && "Unsupported!");
171171 }
172172 return -1;
173173 }
8383 /*
8484 template struct hash {
8585 unsigned int operator()(const unsigned int& x) const {
86 return x;
86 return x;
8787 }
8888 };
8989 */
5454
5555 /// Assign pass manager to manager this pass
5656 virtual void assignPassManager(PMStack &PMS,
57 PassManagerType PMT = PMT_LoopPassManager);
57 PassManagerType PMT = PMT_LoopPassManager);
5858
5959 };
6060
5151
5252 /// Assign pass manager to manager this pass
5353 virtual void assignPassManager(PMStack &PMS,
54 PassManagerType PMT = PMT_CallGraphPassManager);
54 PassManagerType PMT = PMT_CallGraphPassManager);
5555
5656 /// getAnalysisUsage - For this class, we declare that we require and preserve
5757 /// the call graph. If the derived class implements this method, it should
122122 /// Each pass is responsible for assigning a pass manager to itself.
123123 /// PMS is the stack of available pass manager.
124124 virtual void assignPassManager(PMStack &PMS,
125 PassManagerType T = PMT_Unknown) {}
125 PassManagerType T = PMT_Unknown) {}
126126 /// Check if available pass managers are suitable for this pass or not.
127127 virtual void preparePassManager(PMStack &PMS) {}
128128
214214 virtual bool runPass(BasicBlock&) { return false; }
215215
216216 virtual void assignPassManager(PMStack &PMS,
217 PassManagerType T = PMT_ModulePassManager);
217 PassManagerType T = PMT_ModulePassManager);
218218 // Force out-of-line virtual method.
219219 virtual ~ModulePass();
220220 };
281281 bool run(Function &F);
282282
283283 virtual void assignPassManager(PMStack &PMS,
284 PassManagerType T = PMT_FunctionPassManager);
284 PassManagerType T = PMT_FunctionPassManager);
285285 };
286286
287287
336336 virtual bool runPass(BasicBlock &BB);
337337
338338 virtual void assignPassManager(PMStack &PMS,
339 PassManagerType T = PMT_BasicBlockPassManager);
339 PassManagerType T = PMT_BasicBlockPassManager);
340340 };
341341
342342 /// PMStack
136136 ///
137137 const PassInfo *getPassInfo() const { return &PIObj; }
138138
139 typedef Pass* (*NormalCtor_t)();
140
139141 RegisterPassBase(const char *Name, const char *Arg, const std::type_info &TI,
140 Pass *(*NormalCtor)() = 0, bool CFGOnly = false)
142 NormalCtor_t NormalCtor = 0, bool CFGOnly = false)
141143 : PIObj(Name, Arg, TI, NormalCtor, CFGOnly) {
142144 registerPass();
143145 }
163165 // Register Pass using default constructor...
164166 RegisterPass(const char *PassArg, const char *Name, bool CFGOnly = false)
165167 : RegisterPassBase(Name, PassArg, typeid(PassName),
166 callDefaultCtor, CFGOnly) {
168 (RegisterPassBase::NormalCtor_t)callDefaultCtor, CFGOnly) {
167169 }
168170 };
169171
4343 DW_TAG_user_base = 0x1000, // Recommended base for user tags.
4444
4545 DW_CIE_VERSION = 1, // Common frame information version.
46 DW_CIE_ID = 0xffffffff // Common frame information mark.
46 DW_CIE_ID = 0xffffffff // Common frame information mark.
4747 };
4848
4949 enum dwarf_constants {
108108 /// 32-bit argument, Value.
109109 inline uint32_t ByteSwap_32(uint32_t Value) {
110110 #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
111 return __builtin_bswap32(Value);
111 return __builtin_bswap32(Value);
112112 #elif defined(_MSC_VER) && !defined(_DEBUG)
113113 return _byteswap_ulong(Value);
114114 #else
124124 /// 64-bit argument, Value.
125125 inline uint64_t ByteSwap_64(uint64_t Value) {
126126 #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
127 return __builtin_bswap64(Value);
127 return __builtin_bswap64(Value);
128128 #elif defined(_MSC_VER) && !defined(_DEBUG)
129129 return _byteswap_uint64(Value);
130130 #else
883883 // Div utility functions
884884 //
885885 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
886 std::vector* Created) const;
886 std::vector* Created) const;
887887 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
888 std::vector* Created) const;
888 std::vector* Created) const;
889889
890890
891891 //===--------------------------------------------------------------------===//
8181 I != E; ++I) {
8282
8383 // Run all passes on current SCC
84 for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
85
84 for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
8685 Pass *P = getContainedPass(Index);
8786 AnalysisUsage AnUsage;
8887 P->getAnalysisUsage(AnUsage);
9493
9594 StartPassTimer(P);
9695 if (CallGraphSCCPass *CGSP = dynamic_cast(P))
97 Changed |= CGSP->runOnSCC(*I); // TODO : What if CG is changed ?
96 Changed |= CGSP->runOnSCC(*I); // TODO : What if CG is changed ?
9897 else {
99 FPPassManager *FPP = dynamic_cast(P);
100 assert (FPP && "Invalid CGPassManager member");
98 FPPassManager *FPP = dynamic_cast(P);
99 assert (FPP && "Invalid CGPassManager member");
101100
102 // Run pass P on all functions current SCC
103 std::vector &SCC = *I;
104 for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
105 Function *F = SCC[i]->getFunction();
106 if (F) {
101 // Run pass P on all functions current SCC
102 std::vector &SCC = *I;
103 for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
104 Function *F = SCC[i]->getFunction();
105 if (F) {
107106 dumpPassInfo(P, EXECUTION_MSG, ON_FUNCTION_MSG, F->getName());
108107 Changed |= FPP->runOnFunction(*F);
109108 }
110 }
109 }
111110 }
112111 StopPassTimer(P);
113112
148147
149148 /// Assign pass manager to manage this pass.
150149 void CallGraphSCCPass::assignPassManager(PMStack &PMS,
151 PassManagerType PreferredType) {
150 PassManagerType PreferredType) {
152151 // Find CGPassManager
153152 while (!PMS.empty()) {
154153 if (PMS.top()->getPassManagerType() > PMT_CallGraphPassManager)
253253 // The following constants are getting pulled in by one of the
254254 // system headers, which creates a neat clash with the enum.
255255 #if !defined(VM_PROT_NONE)
256 #define VM_PROT_NONE 0x00
256 #define VM_PROT_NONE 0x00
257257 #endif
258258 #if !defined(VM_PROT_READ)
259 #define VM_PROT_READ 0x01
259 #define VM_PROT_READ 0x01
260260 #endif
261261 #if !defined(VM_PROT_WRITE)
262 #define VM_PROT_WRITE 0x02
262 #define VM_PROT_WRITE 0x02
263263 #endif
264264 #if !defined(VM_PROT_EXECUTE)
265 #define VM_PROT_EXECUTE 0x04
265 #define VM_PROT_EXECUTE 0x04
266266 #endif
267267 #if !defined(VM_PROT_ALL)
268 #define VM_PROT_ALL 0x07
268 #define VM_PROT_ALL 0x07
269269 #endif
270270
271271 // Constants for the vm protection fields
11
22 Common register allocation / spilling problem:
33
4 mul lr, r4, lr
5 str lr, [sp, #+52]
6 ldr lr, [r1, #+32]
7 sxth r3, r3
8 ldr r4, [sp, #+52]
9 mla r4, r3, lr, r4
4 mul lr, r4, lr
5 str lr, [sp, #+52]
6 ldr lr, [r1, #+32]
7 sxth r3, r3
8 ldr r4, [sp, #+52]
9 mla r4, r3, lr, r4
1010
1111 can be:
1212
13 mul lr, r4, lr
13 mul lr, r4, lr
1414 mov r4, lr
15 str lr, [sp, #+52]
16 ldr lr, [r1, #+32]
17 sxth r3, r3
18 mla r4, r3, lr, r4
15 str lr, [sp, #+52]
16 ldr lr, [r1, #+32]
17 sxth r3, r3
18 mla r4, r3, lr, r4
1919
2020 and then "merge" mul and mov:
2121
22 mul r4, r4, lr
23 str lr, [sp, #+52]
24 ldr lr, [r1, #+32]
25 sxth r3, r3
26 mla r4, r3, lr, r4
22 mul r4, r4, lr
23 str lr, [sp, #+52]
24 ldr lr, [r1, #+32]
25 sxth r3, r3
26 mla r4, r3, lr, r4
2727
2828 It also increase the likelyhood the store may become dead.
2929
6969
7070 bb27 ...
7171 ...
72 %reg1037 = ADDri %reg1039, 1
73 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
72 %reg1037 = ADDri %reg1039, 1
73 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
7474 Successors according to CFG: 0x8b03bf0 (#5)
7575
7676 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
7777 Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
78 %reg1039 = PHI %reg1070, mbb, %reg1037, mbb
78 %reg1039 = PHI %reg1070, mbb, %reg1037, mbb
7979
8080 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
8181 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
287287 // Tally iterator
288288
289289 /// SlotsAvailable - Returns true if all units are available.
290 ///
290 ///
291291 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
292 unsigned &Resource) {
292 unsigned &Resource) {
293293 assert(N && "Must check availability with N != 0");
294294 // Determine end of interval
295295 Iter End = Begin + N;
317317 Resource = 0;
318318 return false;
319319 }
320
321 /// RetrySlot - Finds a good candidate slot to retry search.
320
321 /// RetrySlot - Finds a good candidate slot to retry search.
322322 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
323323 assert(N && "Must check availability with N != 0");
324324 // Determine end of interval
325325 Iter End = Begin + N;
326326 assert(End <= Tally.end() && "Tally is not large enough for schedule");
327
328 while (Begin != End--) {
329 // Clear units in use
330 ResourceSet &= ~*End;
331 // If no units left then we should go no further
332 if (!ResourceSet) return End + 1;
333 }
334 // Made it all the way through
335 return Begin;
336 }
327
328 while (Begin != End--) {
329 // Clear units in use
330 ResourceSet &= ~*End;
331 // If no units left then we should go no further
332 if (!ResourceSet) return End + 1;
333 }
334 // Made it all the way through
335 return Begin;
336 }
337337
338338 /// FindAndReserveStages - Return true if the stages can be completed. If
339339 /// so mark as busy.
390390 // FindAndReserve - Locate an ideal slot for the specified stages and mark
391391 // as busy.
392392 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
393 InstrStage *StageEnd) {
394 // Where to begin
395 Iter Begin = Tally.begin() + Slot;
396 // Find a free slot
397 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
398 // Distance is slot number
399 unsigned Final = Where - Tally.begin();
393 InstrStage *StageEnd) {
394 // Where to begin
395 Iter Begin = Tally.begin() + Slot;
396 // Find a free slot
397 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
398 // Distance is slot number
399 unsigned Final = Where - Tally.begin();
400400 return Final;
401401 }
402402
21492149 /// multiplying by a magic number. See:
21502150 ///
21512151 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2152 std::vector* Created) const {
2152 std::vector* Created) const {
21532153 MVT::ValueType VT = N->getValueType(0);
21542154
21552155 // Check to see if we can do this.
21972197 /// multiplying by a magic number. See:
21982198 ///
21992199 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2200 std::vector* Created) const {
2200 std::vector* Created) const {
22012201 MVT::ValueType VT = N->getValueType(0);
22022202
22032203 // Check to see if we can do this.
5252 case ARM::MOVr:
5353 case ARM::tMOVr:
5454 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
55 MI.getOperand(1).isRegister() &&
56 "Invalid ARM MOV instruction");
55 MI.getOperand(1).isRegister() &&
56 "Invalid ARM MOV instruction");
5757 SrcReg = MI.getOperand(1).getReg();
5858 DstReg = MI.getOperand(0).getReg();
5959 return true;
13711371 }
13721372
13731373 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1374 MachineBasicBlock &MBB) const {
1374 MachineBasicBlock &MBB) const {
13751375 MachineBasicBlock::iterator MBBI = prior(MBB.end());
13761376 assert((MBBI->getOpcode() == ARM::BX_RET ||
13771377 MBBI->getOpcode() == ARM::tBX_RET ||
5252 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
5353 unsigned AsmVariant, const char *ExtraCode);
5454 bool PrintAsmMemoryOperand(const MachineInstr *MI,
55 unsigned OpNo,
56 unsigned AsmVariant,
57 const char *ExtraCode);
55 unsigned OpNo,
56 unsigned AsmVariant,
57 const char *ExtraCode);
5858 };
5959 } // end of anonymous namespace
6060
277277 /// PrintAsmOperand - Print out an operand for an inline asm expression.
278278 ///
279279 bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
280 unsigned AsmVariant,
281 const char *ExtraCode) {
280 unsigned AsmVariant,
281 const char *ExtraCode) {
282282 printOperand(MI, OpNo);
283283 return false;
284284 }
285285
286286 bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
287 unsigned OpNo,
288 unsigned AsmVariant,
289 const char *ExtraCode) {
287 unsigned OpNo,
288 unsigned AsmVariant,
289 const char *ExtraCode) {
290290 if (ExtraCode && ExtraCode[0])
291291 return true; // Unknown modifier.
292292 O << "0(";
4949 static int64_t get_ldah16(int64_t x) {
5050 int64_t y = x / IMM_MULT;
5151 if (x % IMM_MULT > IMM_HIGH)
52 ++y;
52 ++y;
5353 return y;
5454 }
5555
144144 public:
145145 AlphaDAGToDAGISel(TargetMachine &TM)
146146 : SelectionDAGISel(AlphaLowering),
147 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
147 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
148148 {}
149149
150150 /// getI64Imm - Return a target constant with the specified value, of type
176176 default: return true;
177177 case 'm': // memory
178178 Op0 = Op;
179 AddToISelQueue(Op0);
179 AddToISelQueue(Op0);
180180 break;
181181 }
182182
202202 MachineFunction* MF = BB->getParent();
203203 unsigned GP = 0;
204204 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
205 ee = MF->livein_end(); ii != ee; ++ii)
205 ee = MF->livein_end(); ii != ee; ++ii)
206206 if (ii->first == Alpha::R29) {
207207 GP = ii->second;
208208 break;
218218 MachineFunction* MF = BB->getParent();
219219 unsigned RA = 0;
220220 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
221 ee = MF->livein_end(); ii != ee; ++ii)
221 ee = MF->livein_end(); ii != ee; ++ii)
222222 if (ii->first == Alpha::R26) {
223223 RA = ii->second;
224224 break;
282282 AddToISelQueue(N1);
283283 AddToISelQueue(N2);
284284 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
285 SDOperand(0,0));
285 SDOperand(0,0));
286286 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
287 Chain.getValue(1));
287 Chain.getValue(1));
288288 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
289 Chain.getValue(1));
289 Chain.getValue(1));
290290 SDNode *CNode =
291291 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
292292 Chain, Chain.getValue(1));
293293 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
294 SDOperand(CNode, 1));
294 SDOperand(CNode, 1));
295295 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
296296 }
297297
315315 int64_t val = (int64_t)uval;
316316 int32_t val32 = (int32_t)val;
317317 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
318 val >= IMM_LOW + IMM_LOW * IMM_MULT)
318 val >= IMM_LOW + IMM_LOW * IMM_MULT)
319319 break; //(LDAH (LDA))
320320 if ((uval >> 32) == 0 && //empty upper bits
321 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
322 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
321 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
322 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
323323 break; //(zext (LDAH (LDA)))
324324 //Else use the constant pool
325325 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
327327 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
328328 getGlobalBaseReg());
329329 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
330 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
330 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
331331 }
332332 case ISD::TargetConstantFP: {
333333 ConstantFPSDNode *CN = cast(N);
357357 switch(CC) {
358358 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
359359 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
360 Opc = Alpha::CMPTEQ; break;
360 Opc = Alpha::CMPTEQ; break;
361361 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
362 Opc = Alpha::CMPTLT; break;
362 Opc = Alpha::CMPTLT; break;
363363 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
364 Opc = Alpha::CMPTLE; break;
364 Opc = Alpha::CMPTLE; break;
365365 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
366 Opc = Alpha::CMPTLT; rev = true; break;
366 Opc = Alpha::CMPTLT; rev = true; break;
367367 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
368 Opc = Alpha::CMPTLE; rev = true; break;
368 Opc = Alpha::CMPTLE; rev = true; break;
369369 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
370 Opc = Alpha::CMPTEQ; inv = true; break;
370 Opc = Alpha::CMPTEQ; inv = true; break;
371371 case ISD::SETO:
372 Opc = Alpha::CMPTUN; inv = true; break;
372 Opc = Alpha::CMPTUN; inv = true; break;
373373 case ISD::SETUO:
374 Opc = Alpha::CMPTUN; break;
374 Opc = Alpha::CMPTUN; break;
375375 };
376376 SDOperand tmp1 = N->getOperand(rev?1:0);
377377 SDOperand tmp2 = N->getOperand(rev?0:1);
384384 switch(CC) {
385385 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
386386 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
387 {
388 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1, tmp2);
389 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
390 SDOperand(cmp2, 0), SDOperand(cmp, 0));
391 break;
392 }
387 {
388 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
389 tmp1, tmp2);
390 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
391 SDOperand(cmp2, 0), SDOperand(cmp, 0));
392 break;
393 }
393394 default: break;
394395 }
395396
402403
403404 case ISD::SELECT:
404405 if (MVT::isFloatingPoint(N->getValueType(0)) &&
405 (N->getOperand(0).getOpcode() != ISD::SETCC ||
406 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
406 (N->getOperand(0).getOpcode() != ISD::SETCC ||
407 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
407408 //This should be the condition not covered by the Patterns
408409 //FIXME: Don't have SelectCode die, but rather return something testable
409410 // so that things like this can be caught in fall though code
426427 ConstantSDNode* SC = NULL;
427428 ConstantSDNode* MC = NULL;
428429 if (N->getOperand(0).getOpcode() == ISD::SRL &&
429 (MC = dyn_cast(N->getOperand(1))) &&
430 (SC = dyn_cast(N->getOperand(0).getOperand(1))))
431 {
432 uint64_t sval = SC->getValue();
433 uint64_t mval = MC->getValue();
434 // If the result is a zap, let the autogened stuff handle it.
435 if (get_zapImm(N->getOperand(0), mval))
436 break;
437 // given mask X, and shift S, we want to see if there is any zap in the
438 // mask if we play around with the botton S bits
439 uint64_t dontcare = (~0ULL) >> (64 - sval);
440 uint64_t mask = mval << sval;
441
442 if (get_zapImm(mask | dontcare))
443 mask = mask | dontcare;
444
445 if (get_zapImm(mask)) {
446 AddToISelQueue(N->getOperand(0).getOperand(0));
447 SDOperand Z =
448 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
449 N->getOperand(0).getOperand(0),
450 getI64Imm(get_zapImm(mask))), 0);
451 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
452 getI64Imm(sval));
453 }
430 (MC = dyn_cast(N->getOperand(1))) &&
431 (SC = dyn_cast(N->getOperand(0).getOperand(1)))) {
432 uint64_t sval = SC->getValue();
433 uint64_t mval = MC->getValue();
434 // If the result is a zap, let the autogened stuff handle it.
435 if (get_zapImm(N->getOperand(0), mval))
436 break;
437 // given mask X, and shift S, we want to see if there is any zap in the
438 // mask if we play around with the botton S bits
439 uint64_t dontcare = (~0ULL) >> (64 - sval);
440 uint64_t mask = mval << sval;
441
442 if (get_zapImm(mask | dontcare))
443 mask = mask | dontcare;
444
445 if (get_zapImm(mask)) {
446 AddToISelQueue(N->getOperand(0).getOperand(0));
447 SDOperand Z =
448 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
449 N->getOperand(0).getOperand(0),
450 getI64Imm(get_zapImm(mask))), 0);
451 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
452 getI64Imm(sval));
454453 }
454 }
455455 break;
456456 }
457457
171171 SDOperand Zero = DAG.getConstant(0, PtrVT);
172172
173173 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
174 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
174 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
175175 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
176176 return Lo;
177177 }
196196 // //#define SP $30
197197
198198 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
199 int &VarArgsBase,
200 int &VarArgsOffset) {
199 int &VarArgsBase,
200 int &VarArgsOffset) {
201201 MachineFunction &MF = DAG.getMachineFunction();
202202 MachineFrameInfo *MFI = MF.getFrameInfo();
203203 std::vector ArgValues;
223223 abort();
224224 case MVT::f64:
225225 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
226 &Alpha::F8RCRegClass);
226 &Alpha::F8RCRegClass);
227227 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
228228 break;
229229 case MVT::f32:
230230 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
231 &Alpha::F4RCRegClass);
231 &Alpha::F4RCRegClass);
232232 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
233233 break;
234234 case MVT::i64:
235235 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
236 &Alpha::GPRCRegClass);
236 &Alpha::GPRCRegClass);
237237 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
238238 break;
239239 }
285285
286286 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
287287 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
288 DAG.getNode(AlphaISD::GlobalRetAddr,
289 MVT::i64),
290 SDOperand());
288 DAG.getNode(AlphaISD::GlobalRetAddr,
289 MVT::i64),
290 SDOperand());
291291 switch (Op.getNumOperands()) {
292292 default:
293293 assert(0 && "Do not know how to return this many arguments!");
305305 ArgReg = Alpha::F0;
306306 }
307307 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
308 if(DAG.getMachineFunction().liveout_empty())
308 if (DAG.getMachineFunction().liveout_empty())
309309 DAG.getMachineFunction().addLiveOut(ArgReg);
310310 break;
311311 }
386386 switch (Op.getOpcode()) {
387387 default: assert(0 && "Wasn't expecting to be able to lower this!");
388388 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
389 VarArgsBase,
390 VarArgsOffset);
389 VarArgsBase,
390 VarArgsOffset);
391391
392392 case ISD::RET: return LowerRET(Op,DAG);
393393 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
419419 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
420420
421421 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
422 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
422 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
423423 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
424424 return Lo;
425425 }
431431 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
432432 if (GV->hasInternalLinkage()) {
433433 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
434 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
434 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
435435 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
436436 return Lo;
437437 } else
438438 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
439 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
439 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
440440 }
441441 case ISD::ExternalSymbol: {
442442 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
443 DAG.getTargetExternalSymbol(cast(Op)
444 ->getSymbol(), MVT::i64),
445 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
443 DAG.getTargetExternalSymbol(cast(Op)
444 ->getSymbol(), MVT::i64),
445 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
446446 }
447447
448448 case ISD::UREM:
451451 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
452452 MVT::ValueType VT = Op.Val->getValueType(0);
453453 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
454 BuildUDIV(Op.Val, DAG, NULL) :
455 BuildSDIV(Op.Val, DAG, NULL);
454 BuildUDIV(Op.Val, DAG, NULL) :
455 BuildSDIV(Op.Val, DAG, NULL);
456456 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
457457 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
458458 return Tmp1;
462462 case ISD::UDIV:
463463 if (MVT::isInteger(Op.getValueType())) {
464464 if (Op.getOperand(1).getOpcode() == ISD::Constant)
465 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
466 : BuildUDIV(Op.Val, DAG, NULL);
465 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
466 : BuildUDIV(Op.Val, DAG, NULL);
467467 const char* opstr = 0;
468 switch(Op.getOpcode()) {
468 switch (Op.getOpcode()) {
469469 case ISD::UREM: opstr = "__remqu"; break;
470470 case ISD::SREM: opstr = "__remq"; break;
471471 case ISD::UDIV: opstr = "__divqu"; break;
590590 default: break; // Unknown constriant letter
591591 case 'f':
592592 return make_vector(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
593 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
594 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
595 Alpha::F9 , Alpha::F10, Alpha::F11,
593 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
594 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
595 Alpha::F9 , Alpha::F10, Alpha::F11,
596596 Alpha::F12, Alpha::F13, Alpha::F14,
597 Alpha::F15, Alpha::F16, Alpha::F17,
598 Alpha::F18, Alpha::F19, Alpha::F20,
599 Alpha::F21, Alpha::F22, Alpha::F23,
597 Alpha::F15, Alpha::F16, Alpha::F17,
598 Alpha::F18, Alpha::F19, Alpha::F20,
599 Alpha::F21, Alpha::F22, Alpha::F23,
600600 Alpha::F24, Alpha::F25, Alpha::F26,
601 Alpha::F27, Alpha::F28, Alpha::F29,
602 Alpha::F30, Alpha::F31, 0);
601 Alpha::F27, Alpha::F28, Alpha::F29,
602 Alpha::F30, Alpha::F31, 0);
603603 case 'r':
604604 return make_vector(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
605 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
606 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
607 Alpha::R9 , Alpha::R10, Alpha::R11,
605 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
606 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
607 Alpha::R9 , Alpha::R10, Alpha::R11,
608608 Alpha::R12, Alpha::R13, Alpha::R14,
609 Alpha::R15, Alpha::R16, Alpha::R17,
610 Alpha::R18, Alpha::R19, Alpha::R20,
611 Alpha::R21, Alpha::R22, Alpha::R23,
609 Alpha::R15, Alpha::R16, Alpha::R17,
610 Alpha::R18, Alpha::R19, Alpha::R20,
611 Alpha::R21, Alpha::R22, Alpha::R23,
612612 Alpha::R24, Alpha::R25, Alpha::R26,
613 Alpha::R27, Alpha::R28, Alpha::R29,
614 Alpha::R30, Alpha::R31, 0);
615
613 Alpha::R27, Alpha::R28, Alpha::R29,
614 Alpha::R30, Alpha::R31, 0);
616615 }
617616 }
618617
4949 unsigned count = 0;
5050 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
5151 FI != FE; ++FI) {
52 MachineBasicBlock& MBB = *FI;
53 bool ub = false;
54 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
55 if (count%4 == 0)
56 prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
57 ++count;
58 MachineInstr *MI = I++;
59 switch (MI->getOpcode()) {
60 case Alpha::LDQ: case Alpha::LDL:
61 case Alpha::LDWU: case Alpha::LDBU:
62 case Alpha::LDT: case Alpha::LDS:
63 case Alpha::STQ: case Alpha::STL:
64 case Alpha::STW: case Alpha::STB:
65 case Alpha::STT: case Alpha::STS:
66 if (MI->getOperand(2).getReg() == Alpha::R30) {
67 if (prev[0]
68 && prev[0]->getOperand(2).getReg() ==
69 MI->getOperand(2).getReg()
70 && prev[0]->getOperand(1).getImmedValue() ==
71 MI->getOperand(1).getImmedValue()) {
72 prev[0] = prev[1];
73 prev[1] = prev[2];
74 prev[2] = 0;
75 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
76 .addReg(Alpha::R31);
77 Changed = true; nopintro += 1;
78 count += 1;
79 } else if (prev[1]
80 && prev[1]->getOperand(2).getReg() ==
81 MI->getOperand(2).getReg()
82 && prev[1]->getOperand(1).getImmedValue() ==
83 MI->getOperand(1).getImmedValue()) {
84 prev[0] = prev[2];
85 prev[1] = prev[2] = 0;
86 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
87 .addReg(Alpha::R31);
88 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
89 .addReg(Alpha::R31);
90 Changed = true; nopintro += 2;
91 count += 2;
92 } else if (prev[2]
93 && prev[2]->getOperand(2).getReg() ==
94 MI->getOperand(2).getReg()
95 && prev[2]->getOperand(1).getImmedValue() ==
96 MI->getOperand(1).getImmedValue()) {
97 prev[0] = prev[1] = prev[2] = 0;
98 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
99 .addReg(Alpha::R31);
100 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
101 .addReg(Alpha::R31);
102 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
103 .addReg(Alpha::R31);
104 Changed = true; nopintro += 3;
105 count += 3;
106 }
107 prev[0] = prev[1];
108 prev[1] = prev[2];
109 prev[2] = MI;
110 break;
111 }
112 prev[0] = prev[1];
113 prev[1] = prev[2];
114 prev[2] = 0;
115 break;
116 case Alpha::ALTENT:
117 case Alpha::MEMLABEL:
118 case Alpha::PCLABEL:
119 case Alpha::IDEF_I:
120 case Alpha::IDEF_F32:
121 case Alpha::IDEF_F64:
122 --count;
123 break;
124 case Alpha::BR:
125 case Alpha::JMP:
126 ub = true;
127 //fall through
128 default:
129 prev[0] = prev[1];
130 prev[1] = prev[2];
131 prev[2] = 0;
132 break;
133 }
52 MachineBasicBlock& MBB = *FI;
53 bool ub = false;
54 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
55 if (count%4 == 0)
56 prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
57 ++count;
58 MachineInstr *MI = I++;
59 switch (MI->getOpcode()) {
60 case Alpha::LDQ: case Alpha::LDL:
61 case Alpha::LDWU: case Alpha::LDBU:
62 case Alpha::LDT: case Alpha::LDS:
63 case Alpha::STQ: case Alpha::STL:
64 case Alpha::STW: case Alpha::STB:
65 case Alpha::STT: case Alpha::STS:
66 if (MI->getOperand(2).getReg() == Alpha::R30) {
67 if (prev[0]
68 && prev[0]->getOperand(2).getReg() ==
69 MI->getOperand(2).getReg()
70 && prev[0]->getOperand(1).getImmedValue() ==
71 MI->getOperand(1).getImmedValue()) {
72 prev[0] = prev[1];
73 prev[1] = prev[2];
74 prev[2] = 0;
75 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
76 .addReg(Alpha::R31)
77 .addReg(Alpha::R31);
78 Changed = true; nopintro += 1;
79 count += 1;
80 } else if (prev[1]
81 && prev[1]->getOperand(2).getReg() ==
82 MI->getOperand(2).getReg()
83 && prev[1]->getOperand(1).getImmedValue() ==
84 MI->getOperand(1).getImmedValue()) {
85 prev[0] = prev[2];
86 prev[1] = prev[2] = 0;
87 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
88 .addReg(Alpha::R31)
89 .addReg(Alpha::R31);
90 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
91 .addReg(Alpha::R31)
92 .addReg(Alpha::R31);
93 Changed = true; nopintro += 2;
94 count += 2;
95 } else if (prev[2]
96 && prev[2]->getOperand(2).getReg() ==
97 MI->getOperand(2).getReg()
98 && prev[2]->getOperand(1).getImmedValue() ==
99 MI->getOperand(1).getImmedValue()) {
100 prev[0] = prev[1] = prev[2] = 0;
101 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
102 .addReg(Alpha::R31);
103 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
104 .addReg(Alpha::R31);
105 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
106 .addReg(Alpha::R31);
107 Changed = true; nopintro += 3;
108 count += 3;
109 }
110 prev[0] = prev[1];
111 prev[1] = prev[2];
112 prev[2] = MI;
113 break;
114 }
115 prev[0] = prev[1];
116 prev[1] = prev[2];
117 prev[2] = 0;
118 break;
119 case Alpha::ALTENT:
120 case Alpha::MEMLABEL:
121 case Alpha::PCLABEL:
122 case Alpha::IDEF_I:
123 case Alpha::IDEF_F32:
124 case Alpha::IDEF_F64:
125 --count;
126 break;
127 case Alpha::BR:
128 case Alpha::JMP:
129 ub = true;
130 //fall through
131 default:
132 prev[0] = prev[1];
133 prev[1] = prev[2];
134 prev[2] = 0;
135 break;
134136 }
135 if (ub || AlignAll) {
136 //we can align stuff for free at this point
137 while (count % 4) {
138 BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
139 .addReg(Alpha::R31).addReg(Alpha::R31);
140 ++count;
141 ++nopalign;
142 prev[0] = prev[1];
143 prev[1] = prev[2];
144 prev[2] = 0;
145 }
137 }
138 if (ub || AlignAll) {
139 //we can align stuff for free at this point
140 while (count % 4) {
141 BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
142 .addReg(Alpha::R31).addReg(Alpha::R31);
143 ++count;
144 ++nopalign;
145 prev[0] = prev[1];
146 prev[1] = prev[2];
147 prev[2] = 0;
146148 }
149 }
147150 }
148151 return Changed;
149152 }
116116 case Alpha::CPYST:
117117 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
118118 if (OpNum == 0) { // move -> store
119 unsigned InReg = MI->getOperand(1).getReg();
120 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
121 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
122 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
123 .addReg(Alpha::F31);
119 unsigned InReg = MI->getOperand(1).getReg();
120 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
121 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
122 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
123 .addReg(Alpha::F31);
124124 } else { // load -> move
125 unsigned OutReg = MI->getOperand(0).getReg();
126 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
127 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
128 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
129 .addReg(Alpha::F31);
125 unsigned OutReg = MI->getOperand(0).getReg();
126 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
127 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
128 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
129 .addReg(Alpha::F31);
130130 }
131131 }
132132 break;
5555 return Changed;
5656 }
5757
58 std::set PendingRegWrites; // XXX: ugly global, but
59 // pending writes can cross basic blocks. Note that
60 // taken branches end instruction groups. So we
61 // only need to worry about 'fallthrough' code
58 // XXX: ugly global, but pending writes can cross basic blocks. Note that
59 // taken branches end instruction groups. So we only need to worry about
60 // 'fallthrough' code
61 std::set PendingRegWrites;
6262 };
6363 } // end of anonymous namespace
6464
351351 Chain = targetEntryPoint.getValue(1);
352352 SDOperand targetGPAddr=
353353 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
354 FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
354 FnDescriptor,
355 CurDAG->getConstant(8, MVT::i64)), 0);
355356 Chain = targetGPAddr.getValue(1);
356 SDOperand targetGP=
357 SDOperand targetGP =
357358 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
358359 Chain = targetGP.getValue(1);
359360
417418 int FI = cast(N)->getIndex();
418419 if (N->hasOneUse())
419420 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
420 CurDAG->getTargetFrameIndex(FI, MVT::i64));
421 CurDAG->getTargetFrameIndex(FI, MVT::i64));
421422 else
422423 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
423424 CurDAG->getTargetFrameIndex(FI, MVT::i64));
424425 }
425426
426427 case ISD::ConstantPool: { // TODO: nuke the constant pool
427 // (ia64 doesn't need one)
428 // (ia64 doesn't need one)
428429 ConstantPoolSDNode *CP = cast(N);
429430 Constant *C = CP->getConstVal();
430431 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
436437 case ISD::GlobalAddress: {
437438 GlobalValue *GV = cast(N)->getGlobal();
438439 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
439 SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
440 CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
440 SDOperand Tmp =
441 SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
442 CurDAG->getRegister(IA64::r1,
443 MVT::i64), GA), 0);
441444 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
442445 }
443446
444 /* XXX case ISD::ExternalSymbol: {
445 SDOperand EA = CurDAG->getTargetExternalSymbol(cast(N)->getSymbol(),
446 MVT::i64);
447 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
448 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
449 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
450 }
447 /* XXX
448 case ISD::ExternalSymbol: {
449 SDOperand EA = CurDAG->getTargetExternalSymbol(
450 cast(N)->getSymbol(),
451 MVT::i64);
452 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
453 CurDAG->getRegister(IA64::r1,
454 MVT::i64),
455 EA);
456 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
457 }
451458 */
452459
453460 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
503510 default: assert(0 && "unknown type in store");
504511 case MVT::i1: { // this is a bool
505512 Opc = IA64::ST1; // we store either 0 or 1 as a byte
506 // first load zero!
507 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
508 Chain = Initial.getValue(1);
509 // then load 1 into the same reg iff the predicate to store is 1
513 // first load zero!
514 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
515 Chain = Initial.getValue(1);
516 // then load 1 into the same reg iff the predicate to store is 1
510517 SDOperand Tmp = ST->getValue();
511518 AddToISelQueue(Tmp);
512 Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
513 CurDAG->getTargetConstant(1, MVT::i64),
514 Tmp), 0);
519 Tmp =
520 SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
521 CurDAG->getTargetConstant(1, MVT::i64),
522 Tmp), 0);
515523 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
516524 }
517525 case MVT::i64: Opc = IA64::ST8; break;
550558 case ISD::CALLSEQ_END: {
551559 int64_t Amt = cast(N->getOperand(1))->getValue();
552560 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
553 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
561 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
554562 SDOperand N0 = N->getOperand(0);
555563 AddToISelQueue(N0);
556564 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
557565 }
558566
559567 case ISD::BR:
560 // FIXME: we don't need long branches all the time!
568 // FIXME: we don't need long branches all the time!
561569 SDOperand N0 = N->getOperand(0);
562570 AddToISelQueue(N0);
563571 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
365365 ValToStore = Val;
366366 } else {
367367 RegValuesToPass.push_back(Val);
368 if(1 /* TODO: if(calling external or varadic function)*/ ) {
369 ValToConvert = Val; // additionally pass this FP value as an int
370 }
368 if(1 /* TODO: if(calling external or varadic function)*/ ) {
369 ValToConvert = Val; // additionally pass this FP value as an int
370 }
371371 }
372372 break;
373373 }
383383 }
384384
385385 if(ValToConvert.Val) {
386 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
386 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
387387 }
388388 }
389389
491491 Chain = boolInR8.getValue(1);
492492 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
493493 InFlag = zeroReg.getValue(2);
494 Chain = zeroReg.getValue(1);
494 Chain = zeroReg.getValue(1);
495495
496496 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
497497 break;
0 //===-- MSILWriter.cpp - Library for converting LLVM code to MSIL ---------===//
11 //
2 // The LLVM Compiler Infrastructure
2 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by Roman Samoilov and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
13321332 }
13331333
13341334 //===----------------------------------------------------------------------===//
1335 // External Interface declaration
1335 // External Interface declaration
13361336 //===----------------------------------------------------------------------===//
13371337
13381338 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, std::ostream &o,
0 //===-- MSILWriter.h - TargetMachine for the MSIL ---------------*- C++ -*-===//
11 //
2 // The LLVM Compiler Infrastructure
2 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by Roman Samoilov and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
486486 for (unsigned e = NumOps; i != e; ++i) {
487487 const MachineOperand& MO = MI.getOperand(i);
488488 if (MO.isRegister()) {
489 unsigned Reg = MO.getReg();
490 // Trunc to byte are actually movb. The real source operand is the low
491 // byte of the register.
492 if (isTrunc8 && i == 1)
493 Reg = getX86SubSuperRegister(Reg, MVT::i8);
494 if (isX86_64NonExtLowByteReg(Reg))
495 REX |= 0x40;
489 unsigned Reg = MO.getReg();
490 // Trunc to byte are actually movb. The real source operand is the low
491 // byte of the register.
492 if (isTrunc8 && i == 1)
493 Reg = getX86SubSuperRegister(Reg, MVT::i8);
494 if (isX86_64NonExtLowByteReg(Reg))
495 REX |= 0x40;
496496 }
497497 }
498498
13441344 // We should use extra load for direct calls to dllimported functions in
13451345 // non-JIT mode.
13461346 if (getTargetMachine().getCodeModel() != CodeModel::Large
1347 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1348 getTargetMachine(), true))
1347 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1348 getTargetMachine(), true))
13491349 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
13501350 } else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
13511351 if (getTargetMachine().getCodeModel() != CodeModel::Large)
4848 assert(F->isDeclaration() && "free not external?");
4949 if (!F->use_empty()) {
5050 Function* FN = new Function(F->getFunctionType(),
51 GlobalValue::LinkOnceLinkage,
52 "free_llvm_bounce", &M);
51 GlobalValue::LinkOnceLinkage,
52 "free_llvm_bounce", &M);
5353 BasicBlock* bb = new BasicBlock("entry",FN);
5454 Instruction* R = new ReturnInst(bb);
5555 new FreeInst(FN->arg_begin(), R);
6363 assert(F->isDeclaration() && "malloc not external?");
6464 if (!F->use_empty()) {
6565 Function* FN = new Function(F->getFunctionType(),
66 GlobalValue::LinkOnceLinkage,
67 "malloc_llvm_bounce", &M);
66 GlobalValue::LinkOnceLinkage,
67 "malloc_llvm_bounce", &M);
6868 BasicBlock* bb = new BasicBlock("entry",FN);
6969 Instruction* c = CastInst::createIntegerCast(
7070 FN->arg_begin(), Type::Int32Ty, false, "c", bb);
6767 InternalizePass::InternalizePass(const std::vector&exportList)
6868 : DontInternalize(false){
6969 for(std::vector::const_iterator itr = exportList.begin();
70 itr != exportList.end(); itr++) {
70 itr != exportList.end(); itr++) {
7171 ExternalNames.insert(*itr);
7272 }
7373 }
5959 cl::values(
6060 clEnumValN(GBV, "global", "global counter"),
6161 clEnumValN(GBVO, "ra_global",
62 "register allocated global counter"),
62 "register allocated global counter"),
6363 clEnumValN(HOSTCC, "rdcc", "cycle counter"),
6464 clEnumValEnd));
6565
8181
8282 static RegisterAnalysisGroup A("Profiling passes");
8383 static RegisterPass NP("insert-null-profiling-rs",
84 "Measure profiling framework overhead");
84 "Measure profiling framework overhead");
8585 static RegisterAnalysisGroup NPT(NP);
8686
8787 /// Chooser - Something that chooses when to make a sample of the profiled code
154154 };
155155
156156 RegisterPass X("insert-rs-profiling-framework",
157 "Insert random sampling instrumentation framework");
157 "Insert random sampling instrumentation framework");
158158 }
159159
160160 //Local utilities
201201 "countercc", t);
202202
203203 Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
204 "counternew", t);
204 "counternew", t);
205205 new StoreInst(nv, Counter, t);
206206 t->setCondition(s);
207207
208208 //reset counter
209209 BasicBlock* oldnext = t->getSuccessor(0);
210210 BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(),
211 oldnext);
211 oldnext);
212212 TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
213213 t->setSuccessor(0, resetblock);
214214 new StoreInst(ResetValue, Counter, t2);
274274 "countercc", t);
275275
276276 Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
277 "counternew", t);
277 "counternew", t);
278278 new StoreInst(nv, AI, t);
279279 t->setCondition(s);
280280
281281 //reset counter
282282 BasicBlock* oldnext = t->getSuccessor(0);
283283 BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(),
284 oldnext);
284 oldnext);
285285 TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
286286 t->setSuccessor(0, resetblock);
287287 new StoreInst(ResetValue, AI, t2);
303303 CallInst* c = new CallInst(F, "rdcc", t);
304304 BinaryOperator* b =
305305 BinaryOperator::createAnd(c, ConstantInt::get(Type::Int64Ty, rm),
306 "mrdcc", t);
306 "mrdcc", t);
307307
308308 ICmpInst *s = new ICmpInst(ICmpInst::ICMP_EQ, b,
309309 ConstantInt::get(Type::Int64Ty, 0),
341341 Value *OldVal = new LoadInst(ElementPtr, "OldCounter", InsertPos);
342342 profcode.insert(OldVal);
343343 Value *NewVal = BinaryOperator::createAdd(OldVal,
344 ConstantInt::get(Type::Int32Ty, 1),
345 "NewCounter", InsertPos);
344 ConstantInt::get(Type::Int32Ty, 1),
345 "NewCounter", InsertPos);
346346 profcode.insert(NewVal);
347347 profcode.insert(new StoreInst(NewVal, ElementPtr, InsertPos));
348348 }
365365 TransCache[bb] = bb; //don't translate entry block
366366 else
367367 TransCache[bb] = new BasicBlock("dup_" + bb->getName(), bb->getParent(),
368 NULL);
368 NULL);
369369 return TransCache[bb];
370370 } else if (Instruction* i = dyn_cast(v)) {
371371 //we have already translated this
461461 //b:
462462 new BranchInst(cast(Translate(dst)), bbC);
463463 new BranchInst(dst, cast(Translate(dst)),
464 ConstantInt::get(Type::Int1Ty, true), bbCp);
464 ConstantInt::get(Type::Int1Ty, true), bbCp);
465465 //c:
466466 {
467467 TerminatorInst* iB = src->getTerminator();
483483 CollapsePhi(dst, bbC);
484484 //f:
485485 ReplacePhiPred(cast(Translate(dst)),
486 cast(Translate(src)),bbCp);
486 cast(Translate(src)),bbCp);
487487 CollapsePhi(cast(Translate(dst)), bbCp);
488488 //g:
489489 for(BasicBlock::iterator ib = dst->begin(), ie = dst->end(); ib != ie;
493493 if(bbC == phi->getIncomingBlock(x)) {
494494 phi->addIncoming(Translate(phi->getIncomingValue(x)), bbCp);
495495 cast(Translate(phi))->addIncoming(phi->getIncomingValue(x),
496 bbC);
496 bbC);
497497 }
498498 phi->removeIncomingValue(bbC);
499499 }
509509 //assume that stuff worked. now connect the duplicated basic blocks
510510 //with the originals in such a way as to preserve ssa. yuk!
511511 for (std::set >::iterator
512 ib = BackEdges.begin(), ie = BackEdges.end(); ib != ie; ++ib)
512 ib = BackEdges.begin(), ie = BackEdges.end(); ib != ie; ++ib)
513513 ProcessBackEdge(ib->first, ib->second, F);
514514
515515 //oh, and add the edge from the reg2mem created entry node to the
516516 //duplicated second node
517517 TerminatorInst* T = F.getEntryBlock().getTerminator();
518518 ReplaceInstWithInst(T, new BranchInst(T->getSuccessor(0),
519 cast(Translate(T->getSuccessor(0))),
520 ConstantInt::get(Type::Int1Ty, true)));
519 cast(
520 Translate(T->getSuccessor(0))),
521 ConstantInt::get(Type::Int1Ty, true)));
521522
522523 //do whatever is needed now that the function is duplicated
523524 c->PrepFunction(&F);
526527 ChoicePoints.insert(&F.getEntryBlock());
527528
528529 for (std::set::iterator
529 ii = ChoicePoints.begin(), ie = ChoicePoints.end(); ii != ie; ++ii)
530 ii = ChoicePoints.begin(), ie = ChoicePoints.end(); ii != ie; ++ii)
530531 c->ProcessChoicePoint(*ii);
531532
532533 ChoicePoints.clear();
378378 new AllocaInst(PTy->getElementType(),
379379 ConstantInt::get(Type::Int32Ty, PTy->getNumElements()),
380380 EI.getName() + ".alloca",
381 EI.getParent()->getParent()->getEntryBlock().begin());
381 EI.getParent()->getParent()->getEntryBlock().begin());
382382 for (unsigned i = 0; i < PTy->getNumElements(); ++i) {
383383 GetElementPtrInst *GEP =
384384 new GetElementPtrInst(alloca, ConstantInt::get(Type::Int32Ty, i),
4343 for(Value::use_iterator ii = i->use_begin(), ie = i->use_end();
4444 ii != ie; ++ii)
4545 if (cast(*ii)->getParent() != bb ||
46 isa(*ii))
46 isa(*ii))
4747 return true;
4848 return false;
4949 }
5151 virtual bool runOnFunction(Function &F) {
5252 if (!F.isDeclaration()) {
5353 //give us a clean block
54 BasicBlock* bbold = &F.getEntryBlock();
55 BasicBlock* bbnew = new BasicBlock("allocablock", &F, &F.getEntryBlock());
56 new BranchInst(bbold, bbnew);
54 BasicBlock* bbold = &F.getEntryBlock();
55 BasicBlock* bbnew = new BasicBlock("allocablock", &F, &F.getEntryBlock());
56 new BranchInst(bbold, bbnew);
5757
5858 //find the instructions
5959 std::list worklist;
150150 for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I)
151151 if (DT->getNode(I)->getIDom()->getBlock() == OldPred) {
152152 DT->changeImmediateDominator(DT->getNode(I), DT->getNode(NewBB));
153 EF->setImmediateDominator(I, NewBB);
153 EF->setImmediateDominator(I, NewBB);
154154 }
155155 }
156156
4242 AU.addRequired();
4343 AU.setPreservesCFG();
4444
45 // This is a cluster of orthogonal Transforms:
45 // This is a cluster of orthogonal Transforms:
4646 AU.addPreserved();
4747 AU.addPreservedID(PromoteMemoryToRegisterID);
4848 AU.addPreservedID(LowerSelectID);
7979 bool runOnFunction(Function &F);
8080
8181 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
82 // This is a cluster of orthogonal Transforms
82 // This is a cluster of orthogonal Transforms
8383 AU.addPreservedID(PromoteMemoryToRegisterID);
8484 AU.addPreservedID(LowerSelectID);
8585 AU.addPreservedID(LowerSwitchID);
3636
3737 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3838 // This certainly destroys the CFG.
39 // This is a cluster of orthogonal Transforms:
39 // This is a cluster of orthogonal Transforms:
4040 AU.addPreserved();
4141 AU.addPreservedID(PromoteMemoryToRegisterID);
4242 AU.addPreservedID(LowerSwitchID);
3232 virtual bool runOnFunction(Function &F);
3333
3434 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
35 // This is a cluster of orthogonal Transforms
35 // This is a cluster of orthogonal Transforms
3636 AU.addPreserved();
3737 AU.addPreservedID(PromoteMemoryToRegisterID);
3838 AU.addPreservedID(LowerSelectID);
3939 AU.addRequired();
4040 AU.addRequired();
4141 AU.setPreservesCFG();
42 // This is a cluster of orthogonal Transforms
42 // This is a cluster of orthogonal Transforms
4343 AU.addPreserved();
4444 AU.addPreservedID(LowerSelectID);
4545 AU.addPreservedID(LowerSwitchID);
12921292 /// Find appropriate Module Pass Manager in the PM Stack and
12931293 /// add self into that manager.
12941294 void ModulePass::assignPassManager(PMStack &PMS,
1295 PassManagerType PreferredType) {
1295 PassManagerType PreferredType) {
12961296
12971297 // Find Module Pass Manager
12981298 while(!PMS.empty()) {
13111311 /// Find appropriate Function Pass Manager or Call Graph Pass Manager
13121312 /// in the PM Stack and add self into that manager.
13131313 void FunctionPass::assignPassManager(PMStack &PMS,
1314 PassManagerType PreferredType) {
1314 PassManagerType PreferredType) {
13151315
13161316 // Find Module Pass Manager (TODO : Or Call Graph Pass Manager)
13171317 while(!PMS.empty()) {
13561356 /// Find appropriate Basic Pass Manager or Call Graph Pass Manager
13571357 /// in the PM Stack and add self into that manager.
13581358 void BasicBlockPass::assignPassManager(PMStack &PMS,
1359 PassManagerType PreferredType) {
1359 PassManagerType PreferredType) {
13601360
13611361 BBPassManager *BBP = NULL;
13621362