llvm.org GIT mirror llvm / be36798
80 col. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 6 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
417417 }
418418
419419 // Almost all ARM instructions are predicable.
420 class I opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
421 Format f, string opc, string asm, string cstr, list pattern>
420 class I opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
421 IndexMode im, Format f, string opc, string asm, string cstr,
422 list pattern>
422423 : InstARM {
423424 let OutOperandList = oops;
424425 let InOperandList = !con(iops, (ops pred:$p));
430431 // Same as I except it can optionally modify CPSR. Note it's modeled as
431432 // an input operand since by default it's a zero register. It will
432433 // become an implicit def once it's "flipped".
433 class sI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
434 Format f, string opc, string asm, string cstr, list pattern>
434 class sI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
435 IndexMode im, Format f, string opc, string asm, string cstr,
436 list pattern>
435437 : InstARM {
436438 let OutOperandList = oops;
437439 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));