llvm.org GIT mirror llvm / be2119e
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8 Cameron Zwarich 9 years ago
14 changed file(s) with 64 addition(s) and 66 deletion(s). Raw diff Collapse all Expand all
189189 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
190190 }
191191
192 /// getRegPressureLimit - Return the register pressure "high water mark" for
193 /// the specific register class. The scheduler is in high register pressure
194 /// mode (for the specific register class) if it goes over the limit.
195 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
196 MachineFunction &MF) const {
197 return 0;
198 }
199
200192 /// isTypeLegal - Return true if the target has native support for the
201193 /// specified value type. This means that it has a register that directly
202194 /// holds it without promotions or expansions.
594594 return NULL;
595595 }
596596
597 /// getRegPressureLimit - Return the register pressure "high water mark" for
598 /// the specific register class. The scheduler is in high register pressure
599 /// mode (for the specific register class) if it goes over the limit.
600 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
601 MachineFunction &MF) const {
602 return 0;
603 }
604
597605 /// getAllocationOrder - Returns the register allocation order for a specified
598606 /// register class in the form of a pair of TargetRegisterClass iterators.
599607 virtual std::pair
293293 RegLimit.resize(NumRC);
294294 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
295295 E = TRI->regclass_end(); I != E; ++I)
296 RegLimit[(*I)->getID()] = TLI->getRegPressureLimit(*I, MF);
296 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
297297 }
298298
299299 // Get our Loop information...
14571457 std::fill(RegPressure.begin(), RegPressure.end(), 0);
14581458 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
14591459 E = TRI->regclass_end(); I != E; ++I)
1460 RegLimit[(*I)->getID()] = tli->getRegPressureLimit(*I, MF);
1460 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
14611461 }
14621462 }
14631463
347347 return ARM::GPRRegisterClass;
348348 }
349349
350 unsigned
351 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
352 MachineFunction &MF) const {
353 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
354
355 switch (RC->getID()) {
356 default:
357 return 0;
358 case ARM::tGPRRegClassID:
359 return TFI->hasFP(MF) ? 4 : 5;
360 case ARM::GPRRegClassID: {
361 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
362 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
363 }
364 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
365 case ARM::DPRRegClassID:
366 return 32 - 10;
367 }
368 }
369
350370 /// getAllocationOrder - Returns the register allocation order for a specified
351371 /// register class in the form of a pair of TargetRegisterClass iterators.
352372 std::pair
126126 unsigned &NewSubIdx) const;
127127
128128 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
129
130 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
131 MachineFunction &MF) const;
129132
130133 std::pair
131134 getAllocationOrder(const TargetRegisterClass *RC,
944944 return Sched::RegPressure;
945945 }
946946
947 // FIXME: Move to RegInfo
948 unsigned
949 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
950 MachineFunction &MF) const {
951 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
952
953 switch (RC->getID()) {
954 default:
955 return 0;
956 case ARM::tGPRRegClassID:
957 return TFI->hasFP(MF) ? 4 : 5;
958 case ARM::GPRRegClassID: {
959 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
960 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
961 }
962 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
963 case ARM::DPRRegClassID:
964 return 32 - 10;
965 }
966 }
967
968947 //===----------------------------------------------------------------------===//
969948 // Lowering Code
970949 //===----------------------------------------------------------------------===//
327327 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
328328
329329 Sched::Preference getSchedulingPreference(SDNode *N) const;
330
331 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
332 MachineFunction &MF) const;
333330
334331 bool isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const;
335332 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
182182
183183 virtual bool isLegalAddressingMode(const AddrMode &AM,
184184 const Type *Ty) const;
185
186 /// After allocating this many registers, the allocator should feel
187 /// register pressure. The value is a somewhat random guess, based on the
188 /// number of non callee saved registers in the C calling convention.
189 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
190 MachineFunction &MF) const{
191 return 50;
192 }
193185 };
194186 }
195187
4444 /// This is used for addressing modes.
4545 virtual const TargetRegisterClass *
4646 getPointerRegClass(unsigned Kind = 0) const;
47
48 /// After allocating this many registers, the allocator should feel
49 /// register pressure. The value is a somewhat random guess, based on the
50 /// number of non callee saved registers in the C calling convention.
51 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
52 MachineFunction &MF) const{
53 return 50;
54 }
4755
4856 //! Return the array of callee-saved registers
4957 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
12681268 break;
12691269 }
12701270 return std::make_pair(RRC, Cost);
1271 }
1272
1273 // FIXME: Why this routine is here? Move to RegInfo!
1274 unsigned
1275 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1276 MachineFunction &MF) const {
1277 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1278
1279 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1280 switch (RC->getID()) {
1281 default:
1282 return 0;
1283 case X86::GR32RegClassID:
1284 return 4 - FPDiff;
1285 case X86::GR64RegClassID:
1286 return 12 - FPDiff;
1287 case X86::VR128RegClassID:
1288 return Subtarget->is64Bit() ? 10 : 4;
1289 case X86::VR64RegClassID:
1290 return 4;
1291 }
12921271 }
12931272
12941273 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
675675
676676 /// getFunctionAlignment - Return the Log2 alignment of this function.
677677 virtual unsigned getFunctionAlignment(const Function *F) const;
678
679 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
680 MachineFunction &MF) const;
681678
682679 /// getStackCookieLocation - Return true if the target stores stack
683680 /// protector cookies at a fixed offset in some non-standard address
337337 return &X86::GR32RegClass;
338338 }
339339 return NULL;
340 }
341
342 unsigned
343 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
344 MachineFunction &MF) const {
345 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
346
347 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
348 switch (RC->getID()) {
349 default:
350 return 0;
351 case X86::GR32RegClassID:
352 return 4 - FPDiff;
353 case X86::GR64RegClassID:
354 return 12 - FPDiff;
355 case X86::VR128RegClassID:
356 return TM.getSubtarget().is64Bit() ? 10 : 4;
357 case X86::VR64RegClassID:
358 return 4;
359 }
340360 }
341361
342362 const unsigned *
100100 const TargetRegisterClass *
101101 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
102102
103 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
104 MachineFunction &MF) const;
105
103106 /// getCalleeSavedRegs - Return a null-terminated list of all of the
104107 /// callee-save registers on this target.
105108 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;