llvm.org GIT mirror llvm / be09f2a
[ARM] Tidy up and organise better ARM.td. NFC. This patch tidies up and organises ARM.td so that it is easier to understandand and extend in the future. Reviewed by: @hahn, @rovka Differential Revision: https://reviews.llvm.org/D35248 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307897 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
1 changed file(s) with 261 addition(s) and 196 deletion(s). Raw diff Collapse all Expand all
1616 include "llvm/Target/Target.td"
1717
1818 //===----------------------------------------------------------------------===//
19 // ARM Helper classes.
20 //
21
22 class ProcNoItin Features>
23 : Processor;
24
25 class Architecture features >
26 : SubtargetFeature
27 !strconcat(aname, " architecture"), features>;
28
29 //===----------------------------------------------------------------------===//
3019 // ARM Subtarget state.
3120 //
3221
33 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
34 "Thumb mode">;
35
36 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
37 "Use software floating point features.">;
22 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode",
23 "true", "Thumb mode">;
24
25 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
26 "true", "Use software floating "
27 "point features.">;
28
3829
3930 //===----------------------------------------------------------------------===//
4031 // ARM Subtarget features.
4132 //
4233
43 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
44 "Enable VFP2 instructions">;
45 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
46 "Enable VFP3 instructions",
47 [FeatureVFP2]>;
48 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
49 "Enable NEON instructions",
50 [FeatureVFP3]>;
51 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
52 "Enable Thumb2 instructions">;
53 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
54 "Does not support ARM mode execution",
55 [ModeThumb]>;
56 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
57 "Enable half-precision floating point">;
58 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
59 "Enable VFP4 instructions",
60 [FeatureVFP3, FeatureFP16]>;
61 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
62 "true", "Enable ARMv8 FP",
63 [FeatureVFP4]>;
64 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
65 "Enable full half-precision floating point",
66 [FeatureFPARMv8]>;
67 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
68 "Restrict FP to 16 double registers">;
69 def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
70 "true",
71 "Enable divide instructions in Thumb">;
72 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
75 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
76 "Has data barrier (dmb / dsb) instructions">;
77 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
78 "Has v7 clrex instruction">;
34 // Floating Point, HW Division and Neon Support
35 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
36 "Enable VFP2 instructions">;
37
38 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
39 "Enable VFP3 instructions",
40 [FeatureVFP2]>;
41
42 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
43 "Enable NEON instructions",
44 [FeatureVFP3]>;
45
46 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
47 "Enable half-precision "
48 "floating point">;
49
50 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
51 "Enable VFP4 instructions",
52 [FeatureVFP3, FeatureFP16]>;
53
54 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
55 "true", "Enable ARMv8 FP",
56 [FeatureVFP4]>;
57
58 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
59 "Enable full half-precision "
60 "floating point",
61 [FeatureFPARMv8]>;
62
63 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
64 "Floating point unit supports "
65 "single precision only">;
66
67 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
68 "Restrict FP to 16 double registers">;
69
70 def FeatureHWDivThumb : SubtargetFeature<"hwdiv",
71 "HasHardwareDivideInThumb", "true",
72 "Enable divide instructions in Thumb">;
73
74 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
75 "HasHardwareDivideInARM", "true",
76 "Enable divide instructions in ARM mode">;
77
78 // Atomic Support
79 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
80 "Has data barrier (dmb/dsb) instructions">;
81
82 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
83 "Has v7 clrex instruction">;
84
7985 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
8086 "HasAcquireRelease", "true",
81 "Has v8 acquire/release (lda/ldaex etc) instructions">;
82 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
83 "FP compare + branch is slow">;
84 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
85 "Floating point unit supports single precision only">;
86 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
87 "Enable support for Performance Monitor extensions">;
88 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
89 "Enable support for TrustZone security extensions">;
90 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
91 "Enable support for ARMv8-M Security Extensions">;
92 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
93 "Enable support for Cryptography extensions",
94 [FeatureNEON]>;
95 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
96 "Enable support for CRC instructions">;
87 "Has v8 acquire/release (lda/ldaex "
88 " etc) instructions">;
89
90
91 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
92 "FP compare + branch is slow">;
93
94 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
95 "Enable support for Performance "
96 "Monitor extensions">;
97
98
99 // TrustZone Security Extensions
100 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
101 "Enable support for TrustZone "
102 "security extensions">;
103
104 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
105 "Enable support for ARMv8-M "
106 "Security Extensions">;
107
108 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
109 "Enable support for "
110 "Cryptography extensions",
111 [FeatureNEON]>;
112
113 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
114 "Enable support for CRC instructions">;
115
116
97117 // Not to be confused with FeatureHasRetAddrStack (return address stack)
98 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
99 "Enable Reliability, Availability and Serviceability extensions">;
100 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
101 "Enable fast computation of positive address offsets">;
102 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
103 "CPU fuses AES crypto operations">;
104
105 // Cyclone has preferred instructions for zeroing VFP registers, which can
106 // execute in 0 cycles.
107 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
108 "Has zero-cycle zeroing instructions">;
109
110 // Whether or not it may be profitable to unpredicate certain instructions
111 // during if conversion.
118 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
119 "Enable Reliability, Availability "
120 "and Serviceability extensions">;
121
122 // Fast computation of non-negative address offsets
123 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
124 "Enable fast computation of "
125 "positive address offsets">;
126
127 // Fast execution of AES crypto operations
128 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
129 "CPU fuses AES crypto operations">;
130
131 // Cyclone can zero VFP registers in 0 cycles.
132 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
133 "Has zero-cycle zeroing instructions">;
134
135 // Whether it is profitable to unpredicate certain instructions during if-conversion
112136 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
113 "IsProfitableToUnpredicate",
114 "true",
137 "IsProfitableToUnpredicate", "true",
115138 "Is profitable to unpredicate">;
116139
117140 // Some targets (e.g. Swift) have microcoded VGETLNi32.
118 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
119 "HasSlowVGETLNi32", "true",
120 "Has slow VGETLNi32 - prefer VMOV">;
141 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
142 "HasSlowVGETLNi32", "true",
143 "Has slow VGETLNi32 - prefer VMOV">;
121144
122145 // Some targets (e.g. Swift) have microcoded VDUP32.
123 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
124 "Has slow VDUP32 - prefer VMOV">;
146 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
147 "true",
148 "Has slow VDUP32 - prefer VMOV">;
125149
126150 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
127151 // for scalar FP, as this allows more effective execution domain optimization.
128 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
129 "true", "Prefer VMOVSR">;
152 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
153 "true", "Prefer VMOVSR">;
130154
131155 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
132156 // than ISH
133157 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
134 "true", "Prefer ISHST barriers">;
158 "true", "Prefer ISHST barriers">;
135159
136160 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
137 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
138 "Has muxed AGU and NEON/FPU">;
139
140 // On some targets, a VLDM/VSTM starting with an odd register number needs more
141 // microops than single VLDRS.
161 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits",
162 "true",
163 "Has muxed AGU and NEON/FPU">;
164
165 // Whether VLDM/VSTM starting with odd register number need more microops
166 // than single VLDRS
142167 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
143 "true", "VLDM/VSTM starting with an odd register is slow">;
168 "true", "VLDM/VSTM starting "
169 "with an odd register is slow">;
144170
145171 // Some targets have a renaming dependency when loading into D subregisters.
146172 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
147173 "SlowLoadDSubregister", "true",
148174 "Loading into D subregs is slow">;
175
149176 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
150177 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
151178 "DontWidenVMOVS", "true",
152179 "Don't widen VMOVS to VMOVD">;
153180
154181 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
155 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
156 "Expand VFP/NEON MLA/MLS instructions">;
182 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",
183 "ExpandMLx", "true",
184 "Expand VFP/NEON MLA/MLS instructions">;
157185
158186 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
159187 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
161189
162190 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
163191 // VFP to NEON, as an execution domain optimization.
164 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
165 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
192 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",
193 "UseNEONForFPMovs", "true",
194 "Convert VMOVSR, VMOVRS, "
195 "VMOVS to NEON">;
166196
167197 // Some processors benefit from using NEON instructions for scalar
168198 // single-precision FP operations. This affects instruction selection and should
169199 // only be enabled if the handling of denormals is not important.
170 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
171 "true",
172 "Use NEON for single precision FP">;
200 def FeatureNEONForFP : SubtargetFeature<"neonfp",
201 "UseNEONForSinglePrecisionFP",
202 "true",
203 "Use NEON for single precision FP">;
173204
174205 // On some processors, VLDn instructions that access unaligned data take one
175206 // extra cycle. Take that into account when computing operand latencies.
180211 // Some processors have a nonpipelined VFP coprocessor.
181212 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
182213 "NonpipelinedVFP", "true",
183 "VFP instructions are not pipelined">;
214 "VFP instructions are not pipelined">;
184215
185216 // Some processors have FP multiply-accumulate instructions that don't
186217 // play nicely with other VFP / NEON instructions, and it's generally better
187218 // to just not use them.
188 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
189 "Disable VFP / NEON MAC instructions">;
219 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
220 "Disable VFP / NEON MAC instructions">;
190221
191222 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
192223 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
193 "HasVMLxForwarding", "true",
194 "Has multiplier accumulator forwarding">;
224 "HasVMLxForwarding", "true",
225 "Has multiplier accumulator forwarding">;
195226
196227 // Disable 32-bit to 16-bit narrowing for experimentation.
197228 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
212243 "true",
213244 "Disable +1 predication cost for instructions updating CPSR">;
214245
215 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
216 "AvoidMOVsShifterOperand", "true",
217 "Avoid movs instructions with shifter operand">;
246 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
247 "AvoidMOVsShifterOperand", "true",
248 "Avoid movs instructions with "
249 "shifter operand">;
218250
219251 // Some processors perform return stack prediction. CodeGen should avoid issue
220252 // "normal" call instructions to callees which do not return.
221 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
222 "Has return address stack">;
253 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
254 "HasRetAddrStack", "true",
255 "Has return address stack">;
223256
224257 // Some processors have no branch predictor, which changes the expected cost of
225258 // taking a branch which affects the choice of whether to use predicated
229262 "Has no branch predictor">;
230263
231264 /// DSP extension.
232 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
233 "Supports DSP instructions in ARM and/or Thumb2">;
265 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
266 "Supports DSP instructions in "
267 "ARM and/or Thumb2">;
234268
235269 // Multiprocessing extension.
236 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
237 "Supports Multiprocessing extension">;
270 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
271 "Supports Multiprocessing extension">;
238272
239273 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
240274 def FeatureVirtualization : SubtargetFeature<"virtualization",
241 "HasVirtualization", "true",
242 "Supports Virtualization extension",
243 [FeatureHWDivThumb, FeatureHWDivARM]>;
275 "HasVirtualization", "true",
276 "Supports Virtualization extension",
277 [FeatureHWDivThumb, FeatureHWDivARM]>;
278
279 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
280 // See ARMInstrInfo.td for details.
281 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
282 "NaCl trap">;
283
284 def FeatureStrictAlign : SubtargetFeature<"strict-align",
285 "StrictAlign", "true",
286 "Disallow all unaligned memory "
287 "access">;
288
289 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
290 "Generate calls via indirect call "
291 "instructions">;
292
293 def FeatureExecuteOnly : SubtargetFeature<"execute-only",
294 "GenExecuteOnly", "true",
295 "Enable the generation of "
296 "execute only code.">;
297
298 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
299 "Reserve R9, making it unavailable"
300 " as GPR">;
301
302 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
303 "Don't use movt/movw pairs for "
304 "32-bit imms">;
305
306 def FeatureNoNegativeImmediates
307 : SubtargetFeature<"no-neg-immediates",
308 "NegativeImmediates", "false",
309 "Convert immediates and instructions "
310 "to their negated or complemented "
311 "equivalent when the immediate does "
312 "not fit in the encoding.">;
313
314
315 //===----------------------------------------------------------------------===//
316 // ARM architecture class
317 //
318
319 // A-series ISA
320 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
321 "Is application profile ('A' series)">;
322
323 // R-series ISA
324 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
325 "Is realtime profile ('R' series)">;
244326
245327 // M-series ISA
246328 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
247329 "Is microcontroller profile ('M' series)">;
248330
249 // R-series ISA
250 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
251 "Is realtime profile ('R' series)">;
252
253 // A-series ISA
254 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
255 "Is application profile ('A' series)">;
256
257 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
258 // See ARMInstrInfo.td for details.
259 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
260 "NaCl trap">;
261
262 def FeatureStrictAlign : SubtargetFeature<"strict-align",
263 "StrictAlign", "true",
264 "Disallow all unaligned memory "
265 "access">;
266
267 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
268 "Generate calls via indirect call "
269 "instructions">;
270
271 def FeatureExecuteOnly
272 : SubtargetFeature<"execute-only", "GenExecuteOnly", "true",
273 "Enable the generation of execute only code.">;
274
275 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
276 "Reserve R9, making it unavailable as "
277 "GPR">;
278
279 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
280 "Don't use movt/movw pairs for 32-bit "
281 "imms">;
282
283 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
284 "NegativeImmediates", "false",
285 "Convert immediates and instructions "
286 "to their negated or complemented "
287 "equivalent when the immediate does "
288 "not fit in the encoding.">;
331
332 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
333 "Enable Thumb2 instructions">;
334
335 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
336 "Does not support ARM mode execution",
337 [ModeThumb]>;
338
289339
290340 //===----------------------------------------------------------------------===//
291341 // ARM ISAa.
293343
294344 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
295345 "Support ARM v4T instructions">;
346
296347 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
297348 "Support ARM v5T instructions",
298349 [HasV4TOps]>;
350
299351 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
300 "Support ARM v5TE, v5TEj, and v5TExp instructions",
352 "Support ARM v5TE, v5TEj, and "
353 "v5TExp instructions",
301354 [HasV5TOps]>;
355
302356 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
303357 "Support ARM v6 instructions",
304358 [HasV5TEOps]>;
359
305360 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
306361 "Support ARM v6M instructions",
307362 [HasV6Ops]>;
363
308364 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
309365 "Support ARM v8M Baseline instructions",
310366 [HasV6MOps]>;
367
311368 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
312369 "Support ARM v6k instructions",
313370 [HasV6Ops]>;
371
314372 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
315373 "Support ARM v6t2 instructions",
316374 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
375
317376 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
318377 "Support ARM v7 instructions",
319378 [HasV6T2Ops, FeaturePerfMon,
320379 FeatureV7Clrex]>;
380
381 def HasV8MMainlineOps :
382 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
383 "Support ARM v8M Mainline instructions",
384 [HasV7Ops]>;
385
321386 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
322387 "Support ARM v8 instructions",
323388 [HasV7Ops, FeatureAcquireRelease]>;
389
324390 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
325391 "Support ARM v8.1a instructions",
326392 [HasV8Ops]>;
327 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
393
394 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
328395 "Support ARM v8.2a instructions",
329396 [HasV8_1aOps]>;
330 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
331 "Support ARM v8M Mainline instructions",
332 [HasV7Ops]>;
333397
334398
335399 //===----------------------------------------------------------------------===//
385449 def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
386450 "Cortex-M3 ARM processors", []>;
387451
388 //===----------------------------------------------------------------------===//
389 // ARM schedules.
390 //
391
392 include "ARMSchedule.td"
452
453 //===----------------------------------------------------------------------===//
454 // ARM Helper classes.
455 //
456
457 class Architecture features>
458 : SubtargetFeature
459 !strconcat(aname, " architecture"), features>;
460
461 class ProcNoItin Features>
462 : Processor;
393463
394464
395465 //===----------------------------------------------------------------------===//
546616
547617
548618 //===----------------------------------------------------------------------===//
619 // ARM schedules.
620 //===----------------------------------------------------------------------===//
621 //
622 include "ARMSchedule.td"
623
624 //===----------------------------------------------------------------------===//
549625 // ARM processors
550626 //
551627
552628 // Dummy CPU, used to target architectures
553629 def : ProcessorModel<"generic", CortexA8Model, []>;
630
631 // FIXME: Several processors below are not using their own scheduler
632 // model, but one of similar/previous processor. These should be fixed.
554633
555634 def : ProcNoItin<"arm8", [ARMv4]>;
556635 def : ProcNoItin<"arm810", [ARMv4]>;
611690 FeatureVFP2,
612691 FeatureHasSlowFPVMLx]>;
613692
614 // FIXME: A5 has currently the same Schedule model as A8
615693 def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
616694 FeatureHasRetAddrStack,
617695 FeatureTrustZone,
655733 FeatureCheckVLDnAlign,
656734 FeatureMP]>;
657735
658 // FIXME: A12 has currently the same Schedule model as A9
659736 def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
660737 FeatureHasRetAddrStack,
661738 FeatureTrustZone,
665742 FeatureVirtualization,
666743 FeatureMP]>;
667744
668 // FIXME: A15 has currently the same Schedule model as A9.
669745 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
670746 FeatureDontWidenVMOVS,
671747 FeatureHasRetAddrStack,
677753 FeatureAvoidPartialCPSR,
678754 FeatureVirtualization]>;
679755
680 // FIXME: A17 has currently the same Schedule model as A9
681756 def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
682757 FeatureHasRetAddrStack,
683758 FeatureTrustZone,
687762 FeatureAvoidPartialCPSR,
688763 FeatureVirtualization]>;
689764
690 // FIXME: krait has currently the same Schedule model as A9
691 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
692 // division features.
765 // FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv
693766 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
694767 FeatureHasRetAddrStack,
695768 FeatureMuxedUnits,
719792 FeatureSlowVGETLNi32,
720793 FeatureSlowVDUP32]>;
721794
722 // FIXME: R4 has currently the same ProcessorModel as A8.
723795 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
724796 FeatureHasRetAddrStack,
725797 FeatureAvoidPartialCPSR]>;
726798
727 // FIXME: R4F has currently the same ProcessorModel as A8.
728799 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
729800 FeatureHasRetAddrStack,
730801 FeatureSlowFPBrcc,
733804 FeatureD16,
734805 FeatureAvoidPartialCPSR]>;
735806
736 // FIXME: R5 has currently the same ProcessorModel as A8.
737807 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
738808 FeatureHasRetAddrStack,
739809 FeatureVFP3,
743813 FeatureHasSlowFPVMLx,
744814 FeatureAvoidPartialCPSR]>;
745815
746 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
747816 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
748817 FeatureHasRetAddrStack,
749818 FeatureVFP3,
813882 FeatureCRC,
814883 FeatureFPAO]>;
815884
816 def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
817 FeatureHWDivThumb,
818 FeatureHWDivARM,
819 FeatureCrypto,
820 FeatureCRC,
821 FeatureFPAO,
822 FeatureAvoidPartialCPSR,
823 FeatureCheapPredicableCPSR]>;
885 def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
886 FeatureHWDivThumb,
887 FeatureHWDivARM,
888 FeatureCrypto,
889 FeatureCRC,
890 FeatureFPAO,
891 FeatureAvoidPartialCPSR,
892 FeatureCheapPredicableCPSR]>;
824893
825894 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
826895 FeatureHWDivThumb,
834903 FeatureCrypto,
835904 FeatureCRC]>;
836905
837 // Cyclone is very similar to swift
838906 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
839907 FeatureHasRetAddrStack,
840908 FeatureNEONForFP,
880948 //===----------------------------------------------------------------------===//
881949
882950 include "ARMRegisterInfo.td"
883
884951 include "ARMRegisterBanks.td"
885
886952 include "ARMCallingConv.td"
887953
888954 //===----------------------------------------------------------------------===//
890956 //===----------------------------------------------------------------------===//
891957
892958 include "ARMInstrInfo.td"
893
894959 def ARMInstrInfo : InstrInfo;
895960
896961 //===----------------------------------------------------------------------===//
911976 }
912977
913978 def ARM : Target {
914 // Pull in Instruction Info:
979 // Pull in Instruction Info.
915980 let InstructionSet = ARMInstrInfo;
916981 let AssemblyWriters = [ARMAsmWriter];
917982 let AssemblyParserVariants = [ARMAsmParserVariant];