llvm.org GIT mirror llvm / bdf370d
[Target] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291641 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
5 changed file(s) with 147 addition(s) and 114 deletion(s). Raw diff Collapse all Expand all
2222 #ifndef LLVM_TARGET_TARGETLOWERING_H
2323 #define LLVM_TARGET_TARGETLOWERING_H
2424
25 #include "llvm/ADT/ArrayRef.h"
2526 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/StringRef.h"
2630 #include "llvm/CodeGen/DAGCombine.h"
31 #include "llvm/CodeGen/ISDOpcodes.h"
32 #include "llvm/CodeGen/MachineValueType.h"
2733 #include "llvm/CodeGen/RuntimeLibcalls.h"
2834 #include "llvm/CodeGen/SelectionDAGNodes.h"
35 #include "llvm/CodeGen/ValueTypes.h"
2936 #include "llvm/IR/Attributes.h"
3037 #include "llvm/IR/CallSite.h"
3138 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DerivedTypes.h"
3241 #include "llvm/IR/IRBuilder.h"
3342 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/Instruction.h"
3444 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Type.h"
3546 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Support/AtomicOrdering.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/ErrorHandling.h"
3650 #include "llvm/Target/TargetCallingConv.h"
3751 #include "llvm/Target/TargetMachine.h"
52 #include
53 #include
3854 #include
55 #include
56 #include
3957 #include
58 #include
59 #include
4060 #include
4161
4262 namespace llvm {
43 class BranchProbability;
44 class CallInst;
45 class CCState;
46 class CCValAssign;
47 class FastISel;
48 class FunctionLoweringInfo;
49 class ImmutableCallSite;
50 class IntrinsicInst;
51 class MachineBasicBlock;
52 class MachineFunction;
53 class MachineInstr;
54 class MachineJumpTableInfo;
55 class MachineLoop;
56 class MachineRegisterInfo;
57 class Mangler;
58 class MCContext;
59 class MCExpr;
60 class MCSymbol;
61 template class SmallVectorImpl;
62 class DataLayout;
63 class TargetRegisterClass;
64 class TargetLibraryInfo;
65 class TargetLoweringObjectFile;
66 class Value;
67
68 namespace Sched {
69 enum Preference {
70 None, // No preference
71 Source, // Follow source order.
72 RegPressure, // Scheduling for lowest register pressure.
73 Hybrid, // Scheduling for both latency and register pressure.
74 ILP, // Scheduling for ILP in low register pressure mode.
75 VLIW // Scheduling for VLIW targets.
76 };
77 }
63
64 class BranchProbability;
65 class CCState;
66 class CCValAssign;
67 class FastISel;
68 class FunctionLoweringInfo;
69 class IntrinsicInst;
70 class MachineBasicBlock;
71 class MachineFunction;
72 class MachineInstr;
73 class MachineJumpTableInfo;
74 class MachineLoop;
75 class MachineRegisterInfo;
76 class MCContext;
77 class MCExpr;
78 class TargetRegisterClass;
79 class TargetLibraryInfo;
80 class TargetRegisterInfo;
81 class Value;
82
83 namespace Sched {
84
85 enum Preference {
86 None, // No preference
87 Source, // Follow source order.
88 RegPressure, // Scheduling for lowest register pressure.
89 Hybrid, // Scheduling for both latency and register pressure.
90 ILP, // Scheduling for ILP in low register pressure mode.
91 VLIW // Scheduling for VLIW targets.
92 };
93
94 } // end namespace Sched
7895
7996 /// This base class for TargetLowering contains the SelectionDAG-independent
8097 /// parts that can be used from the rest of CodeGen.
8198 class TargetLoweringBase {
82 TargetLoweringBase(const TargetLoweringBase&) = delete;
83 void operator=(const TargetLoweringBase&) = delete;
84
8599 public:
86100 /// This enum indicates whether operations are valid for a target, and if not,
87101 /// what action should be used to make them valid.
165179
166180 /// NOTE: The TargetMachine owns TLOF.
167181 explicit TargetLoweringBase(const TargetMachine &TM);
168 virtual ~TargetLoweringBase() {}
182 TargetLoweringBase(const TargetLoweringBase&) = delete;
183 void operator=(const TargetLoweringBase&) = delete;
184 virtual ~TargetLoweringBase() = default;
169185
170186 protected:
171187 /// \brief Initialize all of the actions to default values.
598614 MVT &RegisterVT) const;
599615
600616 struct IntrinsicInfo {
601 unsigned opc; // target opcode
602 EVT memVT; // memory VT
603 const Value* ptrVal; // value representing memory location
604 int offset; // offset off of ptrVal
605 unsigned size; // the size of the memory location
606 // (taken from memVT if zero)
607 unsigned align; // alignment
608 bool vol; // is volatile?
609 bool readMem; // reads memory?
610 bool writeMem; // writes memory?
611
612 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
613 vol(false), readMem(false), writeMem(false) {}
617 unsigned opc = 0; // target opcode
618 EVT memVT; // memory VT
619 const Value* ptrVal = nullptr; // value representing memory location
620 int offset = 0; // offset off of ptrVal
621 unsigned size = 0; // the size of the memory location
622 // (taken from memVT if zero)
623 unsigned align = 1; // alignment
624 bool vol = false; // is volatile?
625 bool readMem = false; // reads memory?
626 bool writeMem = false; // writes memory?
627
628 IntrinsicInfo() = default;
614629 };
615630
616631 /// Given an intrinsic, checks if on the target the intrinsic will need to map
821836 getCondCodeAction(CC, VT) == Legal ||
822837 getCondCodeAction(CC, VT) == Custom;
823838 }
824
825839
826840 /// If the action for this operation is to promote, this method returns the
827841 /// ValueType to promote to.
16421656 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
16431657 /// no scale.
16441658 struct AddrMode {
1645 GlobalValue *BaseGV;
1646 int64_t BaseOffs;
1647 bool HasBaseReg;
1648 int64_t Scale;
1649 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1659 GlobalValue *BaseGV = nullptr;
1660 int64_t BaseOffs = 0;
1661 bool HasBaseReg = false;
1662 int64_t Scale = 0;
1663 AddrMode() = default;
16501664 };
16511665
16521666 /// Return true if the addressing mode represented by AM is legal for this
20922106 private:
20932107 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
20942108
2095 private:
2096
20972109 /// Targets can specify ISD nodes that they would like PerformDAGCombine
20982110 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
20992111 /// array.
21912203 /// \see enableExtLdPromotion.
21922204 bool EnableExtLdPromotion;
21932205
2194 protected:
21952206 /// Return true if the value types that can be represented by the specified
21962207 /// register class are all legal.
21972208 bool isLegalRC(const TargetRegisterClass *RC) const;
22082219 /// This class also defines callbacks that targets must implement to lower
22092220 /// target-specific constructs to SelectionDAG operators.
22102221 class TargetLowering : public TargetLoweringBase {
2222 public:
2223 struct DAGCombinerInfo;
2224
22112225 TargetLowering(const TargetLowering&) = delete;
22122226 void operator=(const TargetLowering&) = delete;
2213
2214 public:
2215 struct DAGCombinerInfo;
22162227
22172228 /// NOTE: The TargetMachine owns TLOF.
22182229 explicit TargetLowering(const TargetMachine &TM);
23752386 void *DC; // The DAG Combiner object.
23762387 CombineLevel Level;
23772388 bool CalledByLegalizer;
2389
23782390 public:
23792391 SelectionDAG &DAG;
23802392
25412553 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
25422554 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
25432555 isReturned(false), isSwiftSelf(false), isSwiftError(false),
2544 Alignment(0) { }
2556 Alignment(0) {}
25452557
25462558 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
25472559 };
26802692 ArgListTy &getArgs() {
26812693 return Args;
26822694 }
2683
26842695 };
26852696
26862697 /// This function lowers an abstract call to a function into an actual call.
31753186 SmallVectorImpl &Outs,
31763187 const TargetLowering &TLI, const DataLayout &DL);
31773188
3178 } // end llvm namespace
3179
3180 #endif
3189 } // end namespace llvm
3190
3191 #endif // LLVM_TARGET_TARGETLOWERING_H
1919 #include "llvm/Pass.h"
2020 #include "llvm/Support/CodeGen.h"
2121 #include "llvm/Target/TargetOptions.h"
22 #include
2322 #include
2423
2524 namespace llvm {
2625
27 class InstrItineraryData;
2826 class GlobalValue;
27 class MachineFunctionInitializer;
2928 class Mangler;
30 class MachineFunctionInitializer;
31 class MachineModuleInfo;
3229 class MCAsmInfo;
3330 class MCContext;
3431 class MCInstrInfo;
3532 class MCRegisterInfo;
3633 class MCSubtargetInfo;
3734 class MCSymbol;
35 class raw_pwrite_stream;
3836 class Target;
39 class TargetLibraryInfo;
40 class TargetFrameLowering;
37 class TargetIntrinsicInfo;
4138 class TargetIRAnalysis;
42 class TargetIntrinsicInfo;
43 class TargetLowering;
39 class TargetLoweringObjectFile;
4440 class TargetPassConfig;
45 class TargetRegisterInfo;
4641 class TargetSubtargetInfo;
47 class TargetTransformInfo;
48 class formatted_raw_ostream;
49 class raw_ostream;
50 class raw_pwrite_stream;
51 class TargetLoweringObjectFile;
5242
5343 // The old pass manager infrastructure is hidden in a legacy namespace now.
5444 namespace legacy {
6353 /// interface.
6454 ///
6555 class TargetMachine {
66 TargetMachine(const TargetMachine &) = delete;
67 void operator=(const TargetMachine &) = delete;
6856 protected: // Can only create subclasses.
6957 TargetMachine(const Target &T, StringRef DataLayoutString,
7058 const Triple &TargetTriple, StringRef CPU, StringRef FS,
10593 const TargetOptions DefaultOptions;
10694 mutable TargetOptions Options;
10795
96 TargetMachine(const TargetMachine &) = delete;
97 void operator=(const TargetMachine &) = delete;
10898 virtual ~TargetMachine();
10999
110100 const Target &getTarget() const { return TheTarget; }
310300 bool DisableVerify = true) override;
311301 };
312302
313 } // End llvm namespace
314
315 #endif
303 } // end namespace llvm
304
305 #endif // LLVM_TARGET_TARGETMACHINE_H
1313 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
1414 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
1515
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
1619 #include "llvm/CodeGen/PBQPRAConstraint.h"
1720 #include "llvm/CodeGen/SchedulerRegistry.h"
1821 #include "llvm/CodeGen/ScheduleDAGMutation.h"
1922 #include "llvm/MC/MCSubtargetInfo.h"
2023 #include "llvm/Support/CodeGen.h"
24 #include
2125 #include
2226
2327 namespace llvm {
2428
2529 class CallLowering;
26 class DataLayout;
2730 class InstructionSelector;
2831 class LegalizerInfo;
29 class MachineFunction;
3032 class MachineInstr;
3133 class RegisterBankInfo;
3234 class SDep;
35 class SelectionDAGTargetInfo;
3336 class SUnit;
3437 class TargetFrameLowering;
3538 class TargetInstrInfo;
3740 class TargetRegisterClass;
3841 class TargetRegisterInfo;
3942 class TargetSchedModel;
40 class SelectionDAGTargetInfo;
4143 struct MachineSchedPolicy;
42 template class SmallVectorImpl;
4344
4445 //===----------------------------------------------------------------------===//
4546 ///
4849 /// be exposed through a TargetSubtargetInfo-derived class.
4950 ///
5051 class TargetSubtargetInfo : public MCSubtargetInfo {
51 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
52 void operator=(const TargetSubtargetInfo &) = delete;
53 TargetSubtargetInfo() = delete;
54
5552 protected: // Can only create subclasses...
5653 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
5754 ArrayRef PF,
6865 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
6966 typedef SmallVectorImpl RegClassVector;
7067
68 TargetSubtargetInfo() = delete;
69 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
70 void operator=(const TargetSubtargetInfo &) = delete;
7171 virtual ~TargetSubtargetInfo();
7272
7373 virtual bool isXRaySupported() const { return false; }
228228 virtual bool enableSubRegLiveness() const { return false; }
229229 };
230230
231 } // End llvm namespace
232
233 #endif
231 } // end namespace llvm
232
233 #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
1414 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
1515 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
1616
17 #include "llvm/CodeGen/ISDOpcodes.h"
1718 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineValueType.h"
1820 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/Support/Casting.h"
23 #include
24 #include
25 #include
1926
2027 namespace llvm {
28
29 class InstrItineraryData;
30
2131 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
2232 ///
2333 /// Edges between SUnits are initially based on edges in the SelectionDAG,
4353
4454 explicit ScheduleDAGSDNodes(MachineFunction &mf);
4555
46 ~ScheduleDAGSDNodes() override {}
56 ~ScheduleDAGSDNodes() override = default;
4757
4858 /// Run - perform scheduling.
4959 ///
130140 unsigned DefIdx;
131141 unsigned NodeNumDefs;
132142 MVT ValueType;
143
133144 public:
134145 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
135146
149160 }
150161
151162 void Advance();
163
152164 private:
153165 void InitNodeNumDefs();
154166 };
174186 void EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap,
175187 MachineBasicBlock::iterator InsertPos);
176188 };
177 }
178189
179 #endif
190 } // end namespace llvm
191
192 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
1515 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
1616
1717 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
1820 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineValueType.h"
1923 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/IRBuilder.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/Support/CodeGen.h"
2030 #include "llvm/Target/TargetLowering.h"
21 #include <vector>
31 #include <utility>
2232
2333 namespace llvm {
24 class ARMConstantPoolValue;
25 class ARMSubtarget;
34
35 class ARMSubtarget;
36 class InstrItineraryData;
2637
2738 namespace ARMISD {
39
2840 // ARM Specific DAG Nodes
2941 enum NodeType : unsigned {
3042 // Start the numbering where the builtin ops and target ops leave off.
216228 VST3LN_UPD,
217229 VST4LN_UPD
218230 };
219 }
231
232 } // end namespace ARMISD
220233
221234 /// Define some predicates that are used for node matching.
222235 namespace ARM {
236
223237 bool isBitFieldInvertedMask(unsigned v);
224 }
238
239 } // end namespace ARM
225240
226241 //===--------------------------------------------------------------------===//
227242 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
530545 std::pair getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
531546
532547 typedef SmallVector, 8> RegsToPassVector;
548
533549 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
534550 SDValue &Arg, RegsToPassVector &RegsToPass,
535551 CCValAssign &VA, CCValAssign &NextVA,
622638 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
623639 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
624640 }
641
625642 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
626643 void insertCopiesSplitCSR(
627644 MachineBasicBlock *Entry,
643660 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
644661 bool ForceMutable = false) const;
645662
646 SDValue
647 LowerCall(TargetLowering::CallLoweringInfo &CLI,
648 SmallVectorImpl &InVals) const override;
663 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
664 SmallVectorImpl &InVals) const override;
649665
650666 /// HandleByVal - Target-specific cleanup for ByVal support.
651667 void HandleByVal(CCState *, unsigned &, unsigned) const override;
711727 };
712728
713729 namespace ARM {
730
714731 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
715732 const TargetLibraryInfo *libInfo);
716 }
717 }
718
719 #endif // ARMISELLOWERING_H
733
734 } // end namespace ARM
735
736 } // end namespace llvm
737
738 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H