llvm.org GIT mirror llvm / bd01df2
Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
15 changed file(s) with 27 addition(s) and 48 deletion(s). Raw diff Collapse all Expand all
1212
1313 #include "llvm/Support/Compiler.h"
1414 #include "llvm/Support/DataStream.h"
15 #include "llvm/Support/ErrorHandling.h"
1516 #include "llvm/Support/MemoryObject.h"
1617 #include
1718 #include
114115 // requiring that the bitcode size be known, or otherwise ensuring that
115116 // the memory doesn't go away/get reallocated, but it's
116117 // not currently necessary. Users that need the pointer don't stream.
117 assert(0 && "getPointer in streaming memory objects not allowed");
118 llvm_unreachable("getPointer in streaming memory objects not allowed");
118119 return nullptr;
119120 }
120121 bool isValidAddress(uint64_t address) const override;
153154 kChunkSize);
154155 BytesRead += bytes;
155156 if (bytes < kChunkSize) {
156 if (ObjectSize && BytesRead < Pos)
157 assert(0 && "Unexpected short read fetching bitcode");
157 assert((!ObjectSize || BytesRead >= Pos) &&
158 "Unexpected short read fetching bitcode");
158159 if (BytesRead <= Pos) { // reached EOF/ran out of bytes
159160 ObjectSize = BytesRead;
160161 EOFReached = true;
15731573 break;
15741574
15751575 default:
1576 assert(0 && "FIXME: sh_type value not supported!");
1577 break;
1576 llvm_unreachable("FIXME: sh_type value not supported!");
15781577 }
15791578
15801579 if (TargetObjectWriter->getEMachine() == ELF::EM_ARM &&
810810 }
811811 case HEAD: {
812812 if (ListInit *LHSl = dyn_cast(LHS)) {
813 if (LHSl->getSize() == 0) {
814 assert(0 && "Empty list in car");
815 return nullptr;
816 }
813 assert(LHSl->getSize() != 0 && "Empty list in car");
817814 return LHSl->getElement(0);
818815 }
819816 break;
820817 }
821818 case TAIL: {
822819 if (ListInit *LHSl = dyn_cast(LHS)) {
823 if (LHSl->getSize() == 0) {
824 assert(0 && "Empty list in cdr");
825 return nullptr;
826 }
820 assert(LHSl->getSize() != 0 && "Empty list in cdr");
827821 // Note the +1. We can't just pass the result of getValues()
828822 // directly.
829823 ArrayRef::iterator begin = LHSl->getValues().begin()+1;
822822 #ifndef NDEBUG
823823 MI->dump();
824824 #endif
825 assert(0 && "Unexpected instruction for custom inserter!");
826 break;
825 llvm_unreachable("Unexpected instruction for custom inserter!");
827826
828827 case AArch64::F128CSEL:
829828 return EmitF128CSEL(MI, BB);
832831 case TargetOpcode::PATCHPOINT:
833832 return emitPatchPoint(MI, BB);
834833 }
835 llvm_unreachable("Unexpected instruction for custom inserter!");
836834 }
837835
838836 //===----------------------------------------------------------------------===//
34463446 case Match_MnemonicFail:
34473447 return Error(Loc, "unrecognized instruction mnemonic");
34483448 default:
3449 assert(0 && "unexpected error code!");
3450 return Error(Loc, "invalid instruction format");
3449 llvm_unreachable("unexpected error code!");
34513450 }
34523451 }
34533452
3636 case LLVMDisassembler_VariantKind_ARM64_TLVP:
3737 case LLVMDisassembler_VariantKind_ARM64_TLVOFF:
3838 default:
39 assert(0 && "bad LLVMDisassembler_VariantKind");
40 return MCSymbolRefExpr::VK_None;
39 llvm_unreachable("bad LLVMDisassembler_VariantKind");
4140 }
4241 }
4342
217217 const MCSubtargetInfo &STI) const {
218218 if (MO.isReg())
219219 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
220 else {
221 assert(MO.isImm() && "did not expect relocated expression");
222 return static_cast(MO.getImm());
223 }
224
225 assert(0 && "Unable to encode MCOperand!");
226 return 0;
220
221 assert(MO.isImm() && "did not expect relocated expression");
222 return static_cast(MO.getImm());
227223 }
228224
229225 template uint32_t
320320 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
321321 }
322322
323 assert(0 && "Unhandled update pattern!");
324 return 0;
323 llvm_unreachable("Unhandled update pattern!");
325324 }
326325
327326 // Return true if this MachineInstr inserts a scalar (SPR) value into
10461046 // we have a movt or a movw, but that led to misleadingly results.
10471047 // This is now disallowed in the the AsmParser in validateInstruction()
10481048 // so this should never happen.
1049 assert(0 && "expression without :upper16: or :lower16:");
1050 return 0;
1049 llvm_unreachable("expression without :upper16: or :lower16:");
10511050 }
10521051
10531052 uint32_t ARMMCCodeEmitter::
15371537 int NewOp = opc;
15381538 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
15391539 NewOp = Hexagon::getPredOldOpcode(NewOp);
1540 if (NewOp < 0)
1541 assert(0 && "Couldn't change predicate new instruction to its old form.");
1540 assert(NewOp >= 0 &&
1541 "Couldn't change predicate new instruction to its old form.");
15421542 }
15431543
15441544 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
15451545 NewOp = Hexagon::getNonNVStore(NewOp);
1546 if (NewOp < 0)
1547 assert(0 && "Couldn't change new-value store to its old form.");
1546 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
15481547 }
15491548 return NewOp;
15501549 }
6464 const MCRelaxableFragment *DF,
6565 const MCAsmLayout &Layout) const override {
6666 // FIXME.
67 assert(0 && "RelaxInstruction() unimplemented");
67 llvm_unreachable("RelaxInstruction() unimplemented");
6868 return false;
6969 }
7070
171171 SmallVectorImpl &Fixup,
172172 const MCSubtargetInfo &STI) const {
173173 if (MO.isReg()) {
174 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
174 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
175175 return MRI.getEncodingValue(MO.getReg());
176 } else {
177 return getHWReg(MO.getReg());
178 }
179 } else if (MO.isImm()) {
180 return MO.getImm();
181 } else {
182 assert(0);
183 return 0;
176 return getHWReg(MO.getReg());
184177 }
178
179 assert(MO.isImm());
180 return MO.getImm();
185181 }
186182
187183 #include "AMDGPUGenMCCodeEmitter.inc"
172172 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
173173 raw_ostream &O)
174174 {
175 assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");
175 llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
176176 return true;
177177 }
195195 const MCRelaxableFragment *DF,
196196 const MCAsmLayout &Layout) const override {
197197 // FIXME.
198 assert(0 && "fixupNeedsRelaxation() unimplemented");
198 llvm_unreachable("fixupNeedsRelaxation() unimplemented");
199199 return false;
200200 }
201201 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
132132 if (Expr->EvaluateAsAbsolute(Res))
133133 return Res;
134134
135 assert(0 && "Unhandled expression!");
135 llvm_unreachable("Unhandled expression!");
136136 return 0;
137137 }
138138