llvm.org GIT mirror llvm / bcecf33
Support for read / write from explicit registers with FlagVT type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
3 changed file(s) with 112 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
4444 case MVT::f64: return "f64";
4545 case MVT::f80: return "f80";
4646 case MVT::f128: return "f128";
47 case MVT::Flag: return "Flag";
4748 case MVT::isVoid:return "void";
4849 case MVT::v16i8: return "v16i8";
4950 case MVT::v8i16: return "v8i16";
6869 case MVT::f64: return "f64";
6970 case MVT::f80: return "f80";
7071 case MVT::f128: return "f128";
72 case MVT::Flag: return "Flag";
7173 case MVT::isVoid:return "isVoid";
7274 case MVT::v16i8: return "v16i8";
7375 case MVT::v8i16: return "v8i16";
295295
296296 if (isLeaf()) {
297297 dump();
298 std::cerr << " ";
298299 TP.error("Type inference contradiction found in node!");
299300 } else {
300301 TP.error("Type inference contradiction found in node " +
950951 /// HandleUse - Given "Pat" a leaf in the pattern, check to see if it is an
951952 /// instruction input. Return true if this is a real use.
952953 static bool HandleUse(TreePattern *I, TreePatternNode *Pat,
953 std::map &InstInputs) {
954 std::map &InstInputs,
955 std::vector &InstImpInputs) {
954956 // No name -> not interesting.
955957 if (Pat->getName().empty()) {
956958 if (Pat->isLeaf()) {
957959 DefInit *DI = dynamic_cast(Pat->getLeafValue());
958960 if (DI && DI->getDef()->isSubClassOf("RegisterClass"))
959961 I->error("Input " + DI->getDef()->getName() + " must be named!");
960
962 else if (DI && DI->getDef()->isSubClassOf("Register")) {
963 InstImpInputs.push_back(DI->getDef());
964 }
961965 }
962966 return false;
963967 }
10031007 void DAGISelEmitter::
10041008 FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat,
10051009 std::map &InstInputs,
1006 std::map &InstResults) {
1010 std::map &InstResults,
1011 std::vector &InstImpInputs,
1012 std::vector &InstImpResults) {
10071013 if (Pat->isLeaf()) {
1008 bool isUse = HandleUse(I, Pat, InstInputs);
1014 bool isUse = HandleUse(I, Pat, InstInputs, InstImpInputs);
10091015 if (!isUse && Pat->getTransformFn())
10101016 I->error("Cannot specify a transform function for a non-input value!");
10111017 return;
10151021 for (unsigned i = 0, e = Pat->getNumChildren(); i != e; ++i) {
10161022 if (Pat->getChild(i)->getExtType() == MVT::isVoid)
10171023 I->error("Cannot have void nodes inside of patterns!");
1018 FindPatternInputsAndOutputs(I, Pat->getChild(i), InstInputs, InstResults);
1024 FindPatternInputsAndOutputs(I, Pat->getChild(i), InstInputs, InstResults,
1025 InstImpInputs, InstImpResults);
10191026 }
10201027
10211028 // If this is a non-leaf node with no children, treat it basically as if
10221029 // it were a leaf. This handles nodes like (imm).
10231030 bool isUse = false;
10241031 if (Pat->getNumChildren() == 0)
1025 isUse = HandleUse(I, Pat, InstInputs);
1032 isUse = HandleUse(I, Pat, InstInputs, InstImpInputs);
10261033
10271034 if (!isUse && Pat->getTransformFn())
10281035 I->error("Cannot specify a transform function for a non-input value!");
10481055 DefInit *Val = dynamic_cast(Dest->getLeafValue());
10491056 if (!Val)
10501057 I->error("set destination should be a register!");
1051
1052 if (!Val->getDef()->isSubClassOf("RegisterClass") &&
1053 !Val->getDef()->isSubClassOf("Register"))
1058
1059 if (Val->getDef()->isSubClassOf("RegisterClass")) {
1060 if (Dest->getName().empty())
1061 I->error("set destination must have a name!");
1062 if (InstResults.count(Dest->getName()))
1063 I->error("cannot set '" + Dest->getName() +"' multiple times");
1064 InstResults[Dest->getName()] = Val->getDef();
1065 } else if (Val->getDef()->isSubClassOf("Register")) {
1066 InstImpResults.push_back(Val->getDef());
1067 } else {
10541068 I->error("set destination should be a register!");
1055 if (Dest->getName().empty())
1056 I->error("set destination must have a name!");
1057 if (InstResults.count(Dest->getName()))
1058 I->error("cannot set '" + Dest->getName() +"' multiple times");
1059 InstResults[Dest->getName()] = Val->getDef();
1060
1069 }
1070
10611071 // Verify and collect info from the computation.
10621072 FindPatternInputsAndOutputs(I, Pat->getChild(i+NumValues),
1063 InstInputs, InstResults);
1073 InstInputs, InstResults, InstImpInputs, InstImpResults);
10641074 }
10651075 }
10661076
11341144 }
11351145
11361146 // Create and insert the instruction.
1147 std::vector ImpResults;
1148 std::vector ImpOperands;
11371149 Instructions.insert(std::make_pair(Instrs[i],
1138 DAGInstruction(0, Results, Operands)));
1150 DAGInstruction(0, Results, Operands,
1151 ImpResults, ImpOperands)));
11391152 continue; // no pattern.
11401153 }
11411154
11561169 // InstResults - Keep track of all the virtual registers that are 'set'
11571170 // in the instruction, including what reg class they are.
11581171 std::map InstResults;
1172
1173 std::vector InstImpInputs;
1174 std::vector InstImpResults;
11591175
11601176 // Verify that the top-level forms in the instruction are of void type, and
11611177 // fill in the InstResults map.
11661182 " void types");
11671183
11681184 // Find inputs and outputs, and verify the structure of the uses/defs.
1169 FindPatternInputsAndOutputs(I, Pat, InstInputs, InstResults);
1185 FindPatternInputsAndOutputs(I, Pat, InstInputs, InstResults,
1186 InstImpInputs, InstImpResults);
11701187 }
11711188
11721189 // Now that we have inputs and outputs of the pattern, inspect the operands
12551272 new TreePatternNode(I->getRecord(), ResultNodeOperands);
12561273
12571274 // Create and insert the instruction.
1258 DAGInstruction TheInst(I, Results, Operands);
1275 DAGInstruction TheInst(I, Results, Operands, InstImpResults, InstImpInputs);
12591276 Instructions.insert(std::make_pair(I->getRecord(), TheInst));
12601277
12611278 // Use a temporary tree pattern to infer all types and make sure that the
12831300 }
12841301 TreePatternNode *Pattern = I->getTree(0);
12851302 TreePatternNode *SrcPattern;
1286 if (TheInst.getNumResults() == 0) {
1287 SrcPattern = Pattern;
1288 } else {
1289 if (Pattern->getOperator()->getName() != "set")
1290 continue; // Not a set (store or something?)
1291
1303 if (Pattern->getOperator()->getName() == "set") {
12921304 if (Pattern->getNumChildren() != 2)
12931305 continue; // Not a set of a single value (not handled so far)
12941306
12951307 SrcPattern = Pattern->getChild(1)->clone();
1308 } else{
1309 // Not a set (store or something?)
1310 SrcPattern = Pattern;
12961311 }
12971312
12981313 std::string Reason;
13311346 {
13321347 std::map InstInputs;
13331348 std::map InstResults;
1349 std::vector InstImpInputs;
1350 std::vector InstImpResults;
13341351 FindPatternInputsAndOutputs(Pattern, Pattern->getOnlyTree(),
1335 InstInputs, InstResults);
1352 InstInputs, InstResults,
1353 InstImpInputs, InstImpResults);
13361354 }
13371355
13381356 ListInit *LI = Patterns[i]->getValueAsListInit("ResultInstrs");
16421660 static unsigned getPatternSize(TreePatternNode *P, DAGISelEmitter &ISE) {
16431661 assert(isExtIntegerVT(P->getExtType()) ||
16441662 isExtFloatingPointVT(P->getExtType()) ||
1645 P->getExtType() == MVT::isVoid && "Not a valid pattern node to size!");
1663 P->getExtType() == MVT::isVoid ||
1664 P->getExtType() == MVT::Flag && "Not a valid pattern node to size!");
16461665 unsigned Size = 1; // The node itself.
16471666
16481667 // FIXME: This is a hack to statically increase the priority of patterns
19541973 OS << ";\n";
19551974 OS << " if (!" << Fn << "(" << Val;
19561975 for (unsigned i = 0; i < NumRes; i++)
1957 OS << " , Tmp" << i + ResNo;
1976 OS << ", Tmp" << i + ResNo;
19581977 OS << ")) goto P" << PatternNo << "Fail;\n";
19591978 TmpNo = ResNo + NumRes;
19601979 } else {
20242043 Ops.push_back(NumTemps[i].second + j);
20252044 }
20262045
2027 CodeGenInstruction &II =
2028 ISE.getTargetInfo().getInstruction(Op->getName());
2046 const CodeGenTarget &CGT = ISE.getTargetInfo();
2047 CodeGenInstruction &II = CGT.getInstruction(Op->getName());
20292048
20302049 // Emit all the chain and CopyToReg stuff.
20312050 if (II.hasCtrlDep)
20332052 EmitCopyToRegs(Pattern, "N", II.hasCtrlDep);
20342053
20352054 const DAGInstruction &Inst = ISE.getInstruction(Op);
2055 unsigned NumImpResults = Inst.getNumImpResults();
20362056 unsigned NumResults = Inst.getNumResults();
20372057 unsigned ResNo = TmpNo++;
20382058 if (!isRoot) {
20392059 OS << " SDOperand Tmp" << ResNo << " = CurDAG->getTargetNode("
2040 << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
2041 << getEnumName(N->getType());
2060 << II.Namespace << "::" << II.TheDef->getName();
2061 if (N->getType() != MVT::isVoid)
2062 OS << ", MVT::" << getEnumName(N->getType());
2063 for (unsigned i = 0; i < NumImpResults; i++) {
2064 Record *ImpResult = Inst.getImpResult(i);
2065 MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
2066 OS << ", MVT::" << getEnumName(RVT);
2067 }
2068
20422069 unsigned LastOp = 0;
20432070 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
20442071 LastOp = Ops[i];
20542081 OS << " SDOperand Result = ";
20552082 OS << "CurDAG->getTargetNode("
20562083 << II.Namespace << "::" << II.TheDef->getName();
2057 if (NumResults > 0)
2058 OS << ", MVT::" << getEnumName(N->getType()); // TODO: multiple results?
2084 if (NumResults > 0) {
2085 // TODO: multiple results?
2086 if (N->getType() != MVT::isVoid)
2087 OS << ", MVT::" << getEnumName(N->getType());
2088 }
20592089 OS << ", MVT::Other";
2090 for (unsigned i = 0; i < NumImpResults; i++) {
2091 Record *ImpResult = Inst.getImpResult(i);
2092 MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
2093 OS << ", MVT::" << getEnumName(RVT);
2094 }
20602095 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
20612096 OS << ", Tmp" << Ops[i];
20622097 OS << ", Chain";
20732108 OS << "= CodeGenMap[" << FoldedChains[j] << ".getValue("
20742109 << NumResults << ")] ";
20752110 OS << "= Result.getValue(" << NumResults << ");\n";
2076 if (NumResults == 0)
2111 if (NumResults == 0 && NumImpResults == 0)
20772112 OS << " return Chain;\n";
20782113 else
20792114 OS << " return (N.ResNo) ? Chain : Result.getValue(0);\n";
20822117 // use SelectNodeTo instead of getTargetNode to avoid an allocation.
20832118 OS << " if (N.Val->hasOneUse()) {\n";
20842119 OS << " return CurDAG->SelectNodeTo(N.Val, "
2085 << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
2086 << getEnumName(N->getType());
2120 << II.Namespace << "::" << II.TheDef->getName();
2121 if (N->getType() != MVT::isVoid)
2122 OS << ", MVT::" << getEnumName(N->getType());
2123 for (unsigned i = 0; i < NumImpResults; i++) {
2124 Record *ImpResult = Inst.getImpResult(i);
2125 MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
2126 OS << ", MVT::" << getEnumName(RVT);
2127 }
20872128 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
20882129 OS << ", Tmp" << Ops[i];
20892130 if (InFlag)
20912132 OS << ");\n";
20922133 OS << " } else {\n";
20932134 OS << " return CodeGenMap[N] = CurDAG->getTargetNode("
2094 << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
2095 << getEnumName(N->getType());
2135 << II.Namespace << "::" << II.TheDef->getName();
2136 if (N->getType() != MVT::isVoid)
2137 OS << ", MVT::" << getEnumName(N->getType());
2138 for (unsigned i = 0; i < NumImpResults; i++) {
2139 Record *ImpResult = Inst.getImpResult(i);
2140 MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
2141 OS << ", MVT::" << getEnumName(RVT);
2142 }
20962143 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
20972144 OS << ", Tmp" << Ops[i];
20982145 if (InFlag)
21582205 Record *RR = DI->getDef();
21592206 if (RR->isSubClassOf("Register")) {
21602207 MVT::ValueType RVT = getRegisterValueType(RR, T);
2161 if (HasCtrlDep) {
2208 if (RVT == MVT::Flag) {
2209 OS << " InFlag = Select(" << RootName << OpNo << ");\n";
2210 } else if (HasCtrlDep) {
21622211 OS << " SDOperand " << RootName << "CR" << i << ";\n";
21632212 OS << " " << RootName << "CR" << i
21642213 << " = CurDAG->getCopyToReg(Chain, CurDAG->getRegister("
326326 TreePattern *Pattern;
327327 std::vector Results;
328328 std::vector Operands;
329 std::vector ImpResults;
330 std::vector ImpOperands;
329331 TreePatternNode *ResultPattern;
330332 public:
331333 DAGInstruction(TreePattern *TP,
332334 const std::vector &results,
333 const std::vector &operands)
335 const std::vector &operands,
336 const std::vector &impresults,
337 const std::vector &impoperands)
334338 : Pattern(TP), Results(results), Operands(operands),
339 ImpResults(impresults), ImpOperands(impoperands),
335340 ResultPattern(0) {}
336341
337342 TreePattern *getPattern() const { return Pattern; }
338343 unsigned getNumResults() const { return Results.size(); }
339344 unsigned getNumOperands() const { return Operands.size(); }
345 unsigned getNumImpResults() const { return ImpResults.size(); }
346 unsigned getNumImpOperands() const { return ImpOperands.size(); }
340347
341348 void setResultPattern(TreePatternNode *R) { ResultPattern = R; }
342349
348355 Record *getOperand(unsigned ON) const {
349356 assert(ON < Operands.size());
350357 return Operands[ON];
358 }
359
360 Record *getImpResult(unsigned RN) const {
361 assert(RN < ImpResults.size());
362 return ImpResults[RN];
363 }
364
365 Record *getImpOperand(unsigned ON) const {
366 assert(ON < ImpOperands.size());
367 return ImpOperands[ON];
351368 }
352369 TreePatternNode *getResultPattern() const { return ResultPattern; }
353370 };
433450 void FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat,
434451 std::map
435452 TreePatternNode*> &InstInputs,
436 std::map &InstResults);
453 std::map &InstResults,
454 std::vector &InstImpInputs,
455 std::vector &InstImpResults);
437456 void EmitCodeForPattern(PatternToMatch &Pattern, std::ostream &OS);
438457 void EmitInstructionSelector(std::ostream &OS);
439458 };