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AMDGPU: Print all kernel descriptor directives (including the ones with default values) Change by Tony Tye Differential Revision: https://reviews.llvm.org/D51954 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342077 91177308-0d34-0410-b5e6-96231b3b80d8 Konstantin Zhuravlyov 2 years ago
2 changed file(s) with 93 addition(s) and 106 deletion(s). Raw diff Collapse all Expand all
212212 const MCSubtargetInfo &STI, StringRef KernelName,
213213 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
214214 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
215 amdhsa::kernel_descriptor_t DefaultKD = getDefaultAmdhsaKernelDescriptor();
216
217215 IsaVersion IVersion = getIsaVersion(STI.getCPU());
218216
219217 OS << "\t.amdhsa_kernel " << KernelName << '\n';
220218
221 #define PRINT_IF_NOT_DEFAULT(STREAM, DIRECTIVE, KERNEL_DESC, \
222 DEFAULT_KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
223 if (AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) != \
224 AMDHSA_BITS_GET(DEFAULT_KERNEL_DESC.MEMBER_NAME, FIELD_NAME)) \
225 STREAM << "\t\t" << DIRECTIVE << " " \
226 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
227
228 if (KD.group_segment_fixed_size != DefaultKD.group_segment_fixed_size)
229 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
230 << '\n';
231 if (KD.private_segment_fixed_size != DefaultKD.private_segment_fixed_size)
232 OS << "\t\t.amdhsa_private_segment_fixed_size "
233 << KD.private_segment_fixed_size << '\n';
234
235 PRINT_IF_NOT_DEFAULT(
236 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, DefaultKD,
237 kernel_code_properties,
238 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
239 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, DefaultKD,
240 kernel_code_properties,
241 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
242 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_queue_ptr", KD, DefaultKD,
243 kernel_code_properties,
244 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
245 PRINT_IF_NOT_DEFAULT(
246 OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, DefaultKD,
247 kernel_code_properties,
248 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
249 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_id", KD, DefaultKD,
250 kernel_code_properties,
251 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
252 PRINT_IF_NOT_DEFAULT(
253 OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, DefaultKD,
254 kernel_code_properties,
255 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
256 PRINT_IF_NOT_DEFAULT(
257 OS, ".amdhsa_user_sgpr_private_segment_size", KD, DefaultKD,
258 kernel_code_properties,
259 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
260 PRINT_IF_NOT_DEFAULT(
261 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, DefaultKD,
219 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
220 STREAM << "\t\t" << DIRECTIVE << " " \
221 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
222
223 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
224 << '\n';
225 OS << "\t\t.amdhsa_private_segment_fixed_size "
226 << KD.private_segment_fixed_size << '\n';
227
228 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
229 kernel_code_properties,
230 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
231 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
232 kernel_code_properties,
233 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
234 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
235 kernel_code_properties,
236 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
237 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
238 kernel_code_properties,
239 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
240 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
241 kernel_code_properties,
242 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
243 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
244 kernel_code_properties,
245 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
246 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
247 kernel_code_properties,
248 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
249 PRINT_FIELD(
250 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
262251 compute_pgm_rsrc2,
263252 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
264 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, DefaultKD,
265 compute_pgm_rsrc2,
266 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
267 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, DefaultKD,
268 compute_pgm_rsrc2,
269 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
270 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, DefaultKD,
271 compute_pgm_rsrc2,
272 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
273 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_info", KD, DefaultKD,
274 compute_pgm_rsrc2,
275 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
276 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_vgpr_workitem_id", KD, DefaultKD,
277 compute_pgm_rsrc2,
278 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
253 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
254 compute_pgm_rsrc2,
255 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
256 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
257 compute_pgm_rsrc2,
258 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
259 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
260 compute_pgm_rsrc2,
261 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
262 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
263 compute_pgm_rsrc2,
264 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
265 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
266 compute_pgm_rsrc2,
267 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
279268
280269 // These directives are required.
281270 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
288277 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
289278 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
290279
291 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_32", KD, DefaultKD,
292 compute_pgm_rsrc1,
293 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
294 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_16_64", KD, DefaultKD,
295 compute_pgm_rsrc1,
296 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
297 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_32", KD, DefaultKD,
298 compute_pgm_rsrc1,
299 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
300 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_16_64", KD, DefaultKD,
301 compute_pgm_rsrc1,
302 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
303 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_dx10_clamp", KD, DefaultKD,
304 compute_pgm_rsrc1,
305 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
306 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_ieee_mode", KD, DefaultKD,
307 compute_pgm_rsrc1,
308 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
280 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
281 compute_pgm_rsrc1,
282 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
283 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
284 compute_pgm_rsrc1,
285 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
286 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
287 compute_pgm_rsrc1,
288 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
289 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
290 compute_pgm_rsrc1,
291 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
292 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
293 compute_pgm_rsrc1,
294 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
295 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
296 compute_pgm_rsrc1,
297 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
309298 if (IVersion.Major >= 9)
310 PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_fp16_overflow", KD, DefaultKD,
311 compute_pgm_rsrc1,
312 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
313 PRINT_IF_NOT_DEFAULT(
314 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, DefaultKD,
299 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
300 compute_pgm_rsrc1,
301 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
302 PRINT_FIELD(
303 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
315304 compute_pgm_rsrc2,
316305 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
317 PRINT_IF_NOT_DEFAULT(
318 OS, ".amdhsa_exception_fp_denorm_src", KD, DefaultKD, compute_pgm_rsrc2,
319 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
320 PRINT_IF_NOT_DEFAULT(
321 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, DefaultKD,
306 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
307 compute_pgm_rsrc2,
308 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
309 PRINT_FIELD(
310 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
322311 compute_pgm_rsrc2,
323312 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
324 PRINT_IF_NOT_DEFAULT(
325 OS, ".amdhsa_exception_fp_ieee_overflow", KD, DefaultKD,
326 compute_pgm_rsrc2,
327 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
328 PRINT_IF_NOT_DEFAULT(
329 OS, ".amdhsa_exception_fp_ieee_underflow", KD, DefaultKD,
330 compute_pgm_rsrc2,
331 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
332 PRINT_IF_NOT_DEFAULT(
333 OS, ".amdhsa_exception_fp_ieee_inexact", KD, DefaultKD, compute_pgm_rsrc2,
334 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
335 PRINT_IF_NOT_DEFAULT(
336 OS, ".amdhsa_exception_int_div_zero", KD, DefaultKD, compute_pgm_rsrc2,
337 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
338 #undef PRINT_IF_NOT_DEFAULT
313 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
314 compute_pgm_rsrc2,
315 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
316 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
317 compute_pgm_rsrc2,
318 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
319 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
320 compute_pgm_rsrc2,
321 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
322 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
323 compute_pgm_rsrc2,
324 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
325 #undef PRINT_FIELD
339326
340327 OS << "\t.end_amdhsa_kernel\n";
341328 }
7373 .end_amdhsa_kernel
7474
7575 // ASM: .amdhsa_kernel minimal
76 // ASM-NEXT: .amdhsa_next_free_vgpr 0
76 // ASM: .amdhsa_next_free_vgpr 0
7777 // ASM-NEXT: .amdhsa_next_free_sgpr 0
78 // ASM-NEXT: .end_amdhsa_kernel
78 // ASM: .end_amdhsa_kernel
7979
8080 // Test that we can specify all available directives with non-default values.
8181 .p2align 6
172172 .end_amdhsa_kernel
173173
174174 // ASM: .amdhsa_kernel special_sgpr
175 // ASM-NEXT: .amdhsa_next_free_vgpr 0
175 // ASM: .amdhsa_next_free_vgpr 0
176176 // ASM-NEXT: .amdhsa_next_free_sgpr 27
177177 // ASM-NEXT: .amdhsa_reserve_vcc 0
178178 // ASM-NEXT: .amdhsa_reserve_xnack_mask 0
179 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0
179 // ASM: .amdhsa_float_denorm_mode_16_64 0
180180 // ASM-NEXT: .amdhsa_dx10_clamp 0
181181 // ASM-NEXT: .amdhsa_ieee_mode 0
182 // ASM-NEXT: .end_amdhsa_kernel
182 // ASM: .end_amdhsa_kernel
183183
184184 .section .foo
185185